From 680e94d5fadf4e84b54330838069a4c0ed73c8cb Mon Sep 17 00:00:00 2001 From: Yohan Boujon Date: Sat, 25 Mar 2023 23:16:56 +0100 Subject: [PATCH] Modification of Set_SCLK/Reset_SCLK functions, added gitignore file --- .gitignore | 30 + Etape_2.uvoptx | 62 +- Etape_2.uvprojx | 36 +- FonctionEtape2.asm | 24 +- Listings/Simu_Etape0.map | 549 +++-- Listings/fonctionetape.lst | 16 +- Listings/fonctionetape2.lst | 161 +- Listings/principale.lst | 16 +- Listings/startup_stm32f10x_md.lst | 396 ++-- Objects/Etape_2_Simulé.dep | 44 +- Objects/Simu_Etape0.axf | Bin 269392 -> 266072 bytes Objects/Simu_Etape0.build_log.htm | 70 +- Objects/Simu_Etape0.htm | 80 +- Objects/fonctionetape.o | Bin 2416 -> 2416 bytes Objects/fonctionetape2.o | Bin 2508 -> 2488 bytes Objects/principale.o | Bin 2364 -> 2364 bytes Objects/startup_stm32f10x_md.d | 2 +- Objects/startup_stm32f10x_md.o | Bin 5904 -> 5908 bytes Objects/system_stm32f10x.d | 18 +- Objects/system_stm32f10x.o | Bin 258480 -> 5916 bytes .../STM32F103RB/RTE_Device.h.base@1.1.2 | 1828 +++++++++++++++++ .../startup_stm32f10x_md.s.update@1.0.1 | 308 +++ .../system_stm32f10x.c.update@1.0.1 | 1092 ++++++++++ .../STM32F107VC/RTE_Device.h.base@1.1.2 | 1828 +++++++++++++++++ .../startup_stm32f10x_cl.s.update@1.0.1 | 369 ++++ .../system_stm32f10x.c.update@1.0.1 | 1092 ++++++++++ 26 files changed, 7294 insertions(+), 727 deletions(-) create mode 100644 .gitignore create mode 100644 RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2 create mode 100644 RTE/Device/STM32F103RB/startup_stm32f10x_md.s.update@1.0.1 create mode 100644 RTE/Device/STM32F103RB/system_stm32f10x.c.update@1.0.1 create mode 100644 RTE/Device/STM32F107VC/RTE_Device.h.base@1.1.2 create mode 100644 RTE/Device/STM32F107VC/startup_stm32f10x_cl.s.update@1.0.1 create mode 100644 RTE/Device/STM32F107VC/system_stm32f10x.c.update@1.0.1 diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..43314a8 --- /dev/null +++ b/.gitignore @@ -0,0 +1,30 @@ +*.obj +*.o +*.bin +*.list +*.map +*.mk +*.makefile +*.o +*.su +*.d +*.elf +*.scvd +*.crf +*.map +*.sct +*.dbgconf +*.axf +*.htm +*.lnp +*.dep +*.uvguix.* +*.lst +*.iex +**/Objects/ +**/Listings/ +**/Debug/ + + + + diff --git a/Etape_2.uvoptx b/Etape_2.uvoptx index f320ad8..cb26b33 100644 --- a/Etape_2.uvoptx +++ b/Etape_2.uvoptx @@ -125,7 +125,7 @@ 0 DLGDARM - (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=15,39,661,712,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=1148,258,1639,750,0)(121=1190,75,1611,502,1)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=15,39,661,712,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=1209,244,1630,671,1)(121=1190,75,1611,502,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) 0 @@ -142,9 +142,57 @@ 0 0 + 56 + 1 +
134222432
+ 0 + 0 + 0 + 0 + 0 + 1 + .\FonctionEtape2.asm + + \\Simu_Etape0\FonctionEtape2.asm\56 + + + 1 + 0 + 55 + 1 +
134222428
+ 0 + 0 + 0 + 0 + 0 + 1 + .\FonctionEtape2.asm + + \\Simu_Etape0\FonctionEtape2.asm\55 + + + 2 + 0 + 78 + 1 +
134222464
+ 0 + 0 + 0 + 0 + 0 + 1 + .\FonctionEtape2.asm + + \\Simu_Etape0\FonctionEtape2.asm\78 + + + 3 + 0 87 1 -
134222384
+
134222324
0 0 0 @@ -156,7 +204,7 @@ \\Simu_Etape0\Principale.asm\87 - 1 + 4 0 80 1 @@ -172,7 +220,7 @@ - 2 + 5 0 91 1 @@ -188,7 +236,7 @@ - 3 + 6 0 92 1 @@ -230,7 +278,7 @@ 0 1 - 0 + 1 0 0 0 @@ -244,7 +292,7 @@ 0 0 0 - 1 + 0 0 0 0 diff --git a/Etape_2.uvprojx b/Etape_2.uvprojx index 25e6b72..ae8db7a 100644 --- a/Etape_2.uvprojx +++ b/Etape_2.uvprojx @@ -10,13 +10,13 @@ Simulé 0x4 ARM-ADS - 5060960::V5.06 update 7 (build 960)::.\ARMCC - 0 + 6190000::V6.19::ARMCLANG + 1 STM32F103RB STMicroelectronics - Keil.STM32F1xx_DFP.2.3.0 + Keil.STM32F1xx_DFP.2.4.0 http://www.keil.com/pack/ IRAM(0x20000000,0x5000) IROM(0x08000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE @@ -186,6 +186,7 @@ 0 0 0 + 0 0 0 8 @@ -313,7 +314,7 @@ 1 - 1 + 2 0 0 1 @@ -322,14 +323,14 @@ 0 0 0 - 2 + 3 0 0 1 0 0 - 1 - 1 + 3 + 5 1 1 0 @@ -428,7 +429,7 @@ STM32F107VC STMicroelectronics - Keil.STM32F1xx_DFP.2.3.0 + Keil.STM32F1xx_DFP.2.4.0 http://www.keil.com/pack/ IRAM(0x20000000,0x10000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE @@ -598,6 +599,7 @@ 0 0 0 + 0 0 0 8 @@ -835,15 +837,15 @@ - - + + - + @@ -854,7 +856,7 @@ RTE\Device\STM32F103RB\RTE_Device.h - + @@ -862,7 +864,7 @@ RTE\Device\STM32F103RB\startup_stm32f10x_md.s - + @@ -876,7 +878,7 @@ RTE\Device\STM32F103RB\system_stm32f10x.c - + @@ -884,7 +886,7 @@ RTE\Device\STM32F107VC\RTE_Device.h - + @@ -892,7 +894,7 @@ RTE\Device\STM32F107VC\startup_stm32f10x_cl.s - + @@ -906,7 +908,7 @@ RTE\Device\STM32F107VC\system_stm32f10x.c - + diff --git a/FonctionEtape2.asm b/FonctionEtape2.asm index 3ab66cd..6a64d8e 100644 --- a/FonctionEtape2.asm +++ b/FonctionEtape2.asm @@ -50,22 +50,22 @@ Barette1 DCB 0,1,0 ;************************************************************************** Set_SCLK PROC - PUSH {R12,R0} ;On stocke R12 dans R0 - LDR R12,=GPIOBASEA ;On recupère l'adresse de base - LDR R5,[R12,#MaskSclk] ;Valeur à l'adresse de l'output - ORR R5, R5,#(0x01 << 5) ;OU LOGIQUE pour calculer la valeur a mettre dans l'output - STRH R5,[R12,#0x0C] ;Etat du port B (R5) stocké dans l'output - BX LR ;Retour + PUSH {R0-R2} ;On stocke R0 à R2 + LDR R1,=GPIOBASEA ;R1 -> Adresse de GPIOA + LDRH R2,[R1,#OffsetOutput] ;Valeur à l'adresse d'ODR : R2 = GPIOA->ODR + ORR R2, R2,#(0x01 << 5) ;similaire à GPIOA->ODR |= (1<<5) + STRH R2,[R1,#OffsetOutput] ;Etat du port B (R5) stocké dans ODR + BX LR ;Retour ENDP Reset_SCLK PROC - PUSH {R12,R0} ;On stocke R12 dans R0 - LDR R12,=GPIOBASEB ;On recupère l'adresse de base - LDR R5,[R12,#MaskSclk] ;Valeur à l'adresse de l'SCLK - AND R5, R5,#~(0x01 << 5) ;OU LOGIQUE pour calculer la valeur a mettre dans l'output - STRH R5,[R12,#0x0C] ;Etat du port B (R5) stocké dans l'output - BX LR ;Retour + PUSH {R0-R2} ;On stocke R0 à R2 + LDR R1,=GPIOBASEA ;R1 -> Adresse de GPIOA + LDRH R2,[R1,#OffsetOutput] ;Valeur à l'adresse d'ODR : R2 = GPIOA->ODR + AND R2, R2,#~(0x01 << 5) ;similaire à GPIOA->ODR &= ~(1<<5) + STRH R2,[R1,#OffsetOutput] ;Etat du port B (R5) stocké dans ODR + BX LR ;Retour ENDP diff --git a/Listings/Simu_Etape0.map b/Listings/Simu_Etape0.map index c3458c3..ec9abe5 100644 --- a/Listings/Simu_Etape0.map +++ b/Listings/Simu_Etape0.map @@ -1,4 +1,4 @@ -Component: ARM Compiler 5.06 update 7 (build 960) Tool: armlink [4d3601] +Component: Arm Compiler for Embedded 6.19 Tool: armlink [5e73cb00] ============================================================================== @@ -18,11 +18,12 @@ Section Cross References startup_stm32f10x_md.o(RESET) refers to fonctiontimer.o(i.TIM2_IRQHandler) for TIM2_IRQHandler startup_stm32f10x_md.o(RESET) refers to fonctiontimer.o(i.TIM3_IRQHandler) for TIM3_IRQHandler startup_stm32f10x_md.o(RESET) refers to fonctiontimer.o(i.TIM4_IRQHandler) for TIM4_IRQHandler - startup_stm32f10x_md.o(.text) refers to system_stm32f10x.o(i.SystemInit) for SystemInit + startup_stm32f10x_md.o(.text) refers to system_stm32f10x.o(.text.SystemInit) for SystemInit startup_stm32f10x_md.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main - system_stm32f10x.o(i.SetSysClock) refers to system_stm32f10x.o(i.SetSysClockTo72) for SetSysClockTo72 - system_stm32f10x.o(i.SystemCoreClockUpdate) refers to system_stm32f10x.o(.data) for SystemCoreClock - system_stm32f10x.o(i.SystemInit) refers to system_stm32f10x.o(i.SetSysClock) for SetSysClock + system_stm32f10x.o(.ARM.exidx.text.SystemInit) refers to system_stm32f10x.o(.text.SystemInit) for [Anonymous Symbol] + system_stm32f10x.o(.text.SystemCoreClockUpdate) refers to system_stm32f10x.o(.data.SystemCoreClock) for SystemCoreClock + system_stm32f10x.o(.text.SystemCoreClockUpdate) refers to system_stm32f10x.o(.rodata.AHBPrescTable) for AHBPrescTable + system_stm32f10x.o(.ARM.exidx.text.SystemCoreClockUpdate) refers to system_stm32f10x.o(.text.SystemCoreClockUpdate) for [Anonymous Symbol] initialisation.o(i.Init_Cible) refers to initialisation.o(i.Init_Port) for Init_Port initialisation.o(i.Init_Cible) refers to initialisation.o(i.Init_Dot) for Init_Dot initialisation.o(i.Init_Cible) refers to initialisation.o(i.Init_Timer1) for Init_Timer1 @@ -83,9 +84,8 @@ Section Cross References timer_systick_1.o(i.Systick_Period) refers to dmul.o(.text) for __aeabi_dmul timer_systick_1.o(i.Systick_Period) refers to cdrcmple.o(.text) for __aeabi_cdrcmple timer_systick_1.o(i.Systick_Prio_IT) refers to timer_systick_1.o(.data) for Ptr_Systick - entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000F) for __rt_final_cpp - entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$00000011) for __rt_final_exit - entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry12b.o(.ARM.Collect$$$$0000000E) for __rt_lib_shutdown_fini + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000D) for __rt_final_cpp + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$0000000F) for __rt_final_exit entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry9a.o(.ARM.Collect$$$$0000000B) for _main_init @@ -113,6 +113,8 @@ Section Cross References entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload entry9a.o(.ARM.Collect$$$$0000000B) refers to principale.o(moncode) for main entry9b.o(.ARM.Collect$$$$0000000C) refers to principale.o(moncode) for main + fepilogue.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + depilogue.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp depilogue.o(.text) refers to llshl.o(.text) for __aeabi_llsl depilogue.o(.text) refers to llushr.o(.text) for __aeabi_llsr init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload @@ -125,11 +127,12 @@ Removing Unused input sections from the image. Removing principale.o(mesdonnees), (0 bytes). Removing fonctionetape.o(MesDonnees), (0 bytes). Removing startup_stm32f10x_md.o(HEAP), (512 bytes). - Removing system_stm32f10x.o(.rev16_text), (4 bytes). - Removing system_stm32f10x.o(.revsh_text), (4 bytes). - Removing system_stm32f10x.o(.rrx_text), (6 bytes). - Removing system_stm32f10x.o(i.SystemCoreClockUpdate), (164 bytes). - Removing system_stm32f10x.o(.data), (20 bytes). + Removing system_stm32f10x.o(.text), (0 bytes). + Removing system_stm32f10x.o(.ARM.exidx.text.SystemInit), (8 bytes). + Removing system_stm32f10x.o(.text.SystemCoreClockUpdate), (110 bytes). + Removing system_stm32f10x.o(.ARM.exidx.text.SystemCoreClockUpdate), (8 bytes). + Removing system_stm32f10x.o(.data.SystemCoreClock), (4 bytes). + Removing system_stm32f10x.o(.rodata.AHBPrescTable), (16 bytes). Removing initialisation.o(.rev16_text), (4 bytes). Removing initialisation.o(.revsh_text), (4 bytes). Removing initialisation.o(.rrx_text), (6 bytes). @@ -158,7 +161,7 @@ Removing Unused input sections from the image. Removing timer_systick_1.o(.revsh_text), (4 bytes). Removing timer_systick_1.o(.rrx_text), (6 bytes). -35 unused section(s) (total 1220 bytes) removed from the image. +36 unused section(s) (total 1168 bytes) removed from the image. ============================================================================== @@ -168,23 +171,21 @@ Image Symbol Table Symbol Name Value Ov Type Size Object(Section) - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12b.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12a.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE - ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE ../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE - ../clib/microlib/longlong.c 0x00000000 Number 0 llushr.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE ../clib/microlib/longlong.c 0x00000000 Number 0 llshl.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llushr.o ABSOLUTE ../clib/microlib/stubs.s 0x00000000 Number 0 iusefp.o ABSOLUTE ../fplib/microlib/d2f.c 0x00000000 Number 0 d2f.o ABSOLUTE ../fplib/microlib/f2d.c 0x00000000 Number 0 f2d.o ABSOLUTE @@ -194,8 +195,8 @@ Image Symbol Table ../fplib/microlib/fpepilogue.c 0x00000000 Number 0 depilogue.o ABSOLUTE ../fplib/microlib/fpfix.c 0x00000000 Number 0 ffixui.o ABSOLUTE ../fplib/microlib/fpflt.c 0x00000000 Number 0 ffltui.o ABSOLUTE - ../fplib/microlib/fpmul.c 0x00000000 Number 0 dmul.o ABSOLUTE ../fplib/microlib/fpmul.c 0x00000000 Number 0 fmul.o ABSOLUTE + ../fplib/microlib/fpmul.c 0x00000000 Number 0 dmul.o ABSOLUTE ..\\pilotes\\Sources\\Timer_Systick.c 0x00000000 Number 0 timer_systick_1.o ABSOLUTE ..\\pilotes\\Sources\\pilote_IO.c 0x00000000 Number 0 pilote_io_1.o ABSOLUTE ..\pilotes\Sources\Timer_Systick.c 0x00000000 Number 0 timer_systick_1.o ABSOLUTE @@ -208,15 +209,14 @@ Image Symbol Table Initialisation.c 0x00000000 Number 0 initialisation.o ABSOLUTE Initialisation.c 0x00000000 Number 0 initialisation.o ABSOLUTE Principale.asm 0x00000000 Number 0 principale.o ABSOLUTE - RTE\Device\STM32F103RB\startup_stm32f10x_md.s 0x00000000 Number 0 startup_stm32f10x_md.o ABSOLUTE - RTE\Device\STM32F103RB\system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE - RTE\\Device\\STM32F103RB\\system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE + RTE/Device/STM32F103RB/startup_stm32f10x_md.s 0x00000000 Number 0 startup_stm32f10x_md.o ABSOLUTE Warning.c 0x00000000 Number 0 warning.o ABSOLUTE cdcmple.s 0x00000000 Number 0 cdcmple.o ABSOLUTE cdrcmple.s 0x00000000 Number 0 cdrcmple.o ABSOLUTE dc.s 0x00000000 Number 0 dc.o ABSOLUTE handlers.s 0x00000000 Number 0 handlers.o ABSOLUTE init.s 0x00000000 Number 0 init.o ABSOLUTE + system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE RESET 0x08000000 Section 236 startup_stm32f10x_md.o(RESET) .ARM.Collect$$$$00000000 0x080000ec Section 0 entry.o(.ARM.Collect$$$$00000000) .ARM.Collect$$$$00000001 0x080000ec Section 4 entry2.o(.ARM.Collect$$$$00000001) @@ -224,76 +224,70 @@ Image Symbol Table .ARM.Collect$$$$00000008 0x080000f4 Section 0 entry7b.o(.ARM.Collect$$$$00000008) .ARM.Collect$$$$0000000A 0x080000f4 Section 0 entry8b.o(.ARM.Collect$$$$0000000A) .ARM.Collect$$$$0000000B 0x080000f4 Section 8 entry9a.o(.ARM.Collect$$$$0000000B) - .ARM.Collect$$$$0000000E 0x080000fc Section 4 entry12b.o(.ARM.Collect$$$$0000000E) - .ARM.Collect$$$$0000000F 0x08000100 Section 0 entry10a.o(.ARM.Collect$$$$0000000F) - .ARM.Collect$$$$00000011 0x08000100 Section 0 entry11a.o(.ARM.Collect$$$$00000011) - .ARM.Collect$$$$00002712 0x08000100 Section 4 entry2.o(.ARM.Collect$$$$00002712) - __lit__00000000 0x08000100 Data 4 entry2.o(.ARM.Collect$$$$00002712) - .text 0x08000104 Section 36 startup_stm32f10x_md.o(.text) - .text 0x08000128 Section 0 fmul.o(.text) - .text 0x0800018c Section 0 fdiv.o(.text) - .text 0x08000208 Section 0 dmul.o(.text) - .text 0x080002ec Section 0 ddiv.o(.text) - .text 0x080003ca Section 0 ffltui.o(.text) - .text 0x080003d4 Section 0 ffixui.o(.text) - .text 0x080003fc Section 0 f2d.o(.text) - .text 0x08000424 Section 48 cdcmple.o(.text) - .text 0x08000454 Section 48 cdrcmple.o(.text) - .text 0x08000484 Section 0 d2f.o(.text) - .text 0x080004bc Section 0 fepilogue.o(.text) - .text 0x080004bc Section 0 iusefp.o(.text) - .text 0x0800052a Section 0 depilogue.o(.text) - .text 0x080005e4 Section 36 init.o(.text) - .text 0x08000608 Section 0 llshl.o(.text) - .text 0x08000626 Section 0 llushr.o(.text) - i.Anim 0x08000648 Section 0 fonctiontimer.o(i.Anim) - i.GPIO_Configure 0x08000670 Section 0 pilote_io_1.o(i.GPIO_Configure) - i.Init_Cible 0x080007bc Section 0 initialisation.o(i.Init_Cible) - i.Init_Dot 0x080008c8 Section 0 initialisation.o(i.Init_Dot) - i.Init_Port 0x08000940 Section 0 initialisation.o(i.Init_Port) - i.Init_Timer1 0x080009d0 Section 0 initialisation.o(i.Init_Timer1) - i.Init_Timer2_PWM 0x08000b3c Section 0 initialisation.o(i.Init_Timer2_PWM) - i.Init_Timer3_Slave 0x08000c58 Section 0 initialisation.o(i.Init_Timer3_Slave) - i.Init_Timer4 0x08000cc8 Section 0 initialisation.o(i.Init_Timer4) - i.Port_IO_Reset 0x08000d3c Section 0 pilote_io_1.o(i.Port_IO_Reset) - i.Port_IO_Set 0x08000d4c Section 0 pilote_io_1.o(i.Port_IO_Set) - i.SetSysClock 0x08000d5c Section 0 system_stm32f10x.o(i.SetSysClock) - SetSysClock 0x08000d5d Thumb Code 8 system_stm32f10x.o(i.SetSysClock) - i.SetSysClockTo72 0x08000d64 Section 0 system_stm32f10x.o(i.SetSysClockTo72) - SetSysClockTo72 0x08000d65 Thumb Code 214 system_stm32f10x.o(i.SetSysClockTo72) - i.SysTick_Handler 0x08000e44 Section 0 timer_systick_1.o(i.SysTick_Handler) - i.SystemInit 0x08000e54 Section 0 system_stm32f10x.o(i.SystemInit) - i.Systick_Period 0x08000eb4 Section 0 timer_systick_1.o(i.Systick_Period) - i.Systick_Prio_IT 0x08000fc4 Section 0 timer_systick_1.o(i.Systick_Prio_IT) - i.TIM1_CC_IRQHandler 0x08000fe8 Section 0 fonctiontimer.o(i.TIM1_CC_IRQHandler) - i.TIM1_UP_IRQHandler 0x0800109c Section 0 fonctiontimer.o(i.TIM1_UP_IRQHandler) - i.TIM2_IRQHandler 0x08001148 Section 0 fonctiontimer.o(i.TIM2_IRQHandler) - i.TIM3_IRQHandler 0x0800114c Section 0 fonctiontimer.o(i.TIM3_IRQHandler) - i.TIM4_IRQHandler 0x0800119c Section 0 fonctiontimer.o(i.TIM4_IRQHandler) - i.__scatterload_copy 0x08001208 Section 14 handlers.o(i.__scatterload_copy) - i.__scatterload_null 0x08001216 Section 2 handlers.o(i.__scatterload_null) - i.__scatterload_zeroinit 0x08001218 Section 14 handlers.o(i.__scatterload_zeroinit) - moncode 0x08001228 Section 10 principale.o(moncode) - moncode 0x08001234 Section 92 fonctionetape.o(moncode) - moncode 0x08001290 Section 84 fonctionetape2.o(moncode) - moncode 0x080012e4 Section 200 foncasm.o(moncode) + __lit__00000000 0x080000fc Data 4 entry2.o(.ARM.Collect$$$$00002712) + .ARM.Collect$$$$0000000D 0x080000fc Section 0 entry10a.o(.ARM.Collect$$$$0000000D) + .ARM.Collect$$$$0000000F 0x080000fc Section 0 entry11a.o(.ARM.Collect$$$$0000000F) + .ARM.Collect$$$$00002712 0x080000fc Section 4 entry2.o(.ARM.Collect$$$$00002712) + .text 0x08000100 Section 36 startup_stm32f10x_md.o(.text) + .text 0x08000124 Section 0 fmul.o(.text) + .text 0x08000188 Section 0 fdiv.o(.text) + .text 0x08000204 Section 0 dmul.o(.text) + .text 0x080002e8 Section 0 ddiv.o(.text) + .text 0x080003c6 Section 0 ffltui.o(.text) + .text 0x080003d0 Section 0 ffixui.o(.text) + .text 0x080003f8 Section 0 f2d.o(.text) + .text 0x08000420 Section 48 cdcmple.o(.text) + .text 0x08000450 Section 48 cdrcmple.o(.text) + .text 0x08000480 Section 0 d2f.o(.text) + .text 0x080004b8 Section 0 iusefp.o(.text) + .text 0x080004b8 Section 0 fepilogue.o(.text) + .text 0x08000526 Section 0 depilogue.o(.text) + .text 0x080005e0 Section 36 init.o(.text) + .text 0x08000604 Section 0 llshl.o(.text) + .text 0x08000622 Section 0 llushr.o(.text) + [Anonymous Symbol] 0x08000644 Section 0 system_stm32f10x.o(.text.SystemInit) + i.Anim 0x08000754 Section 0 fonctiontimer.o(i.Anim) + i.GPIO_Configure 0x0800077c Section 0 pilote_io_1.o(i.GPIO_Configure) + i.Init_Cible 0x080008c8 Section 0 initialisation.o(i.Init_Cible) + i.Init_Dot 0x080009d4 Section 0 initialisation.o(i.Init_Dot) + i.Init_Port 0x08000a4c Section 0 initialisation.o(i.Init_Port) + i.Init_Timer1 0x08000adc Section 0 initialisation.o(i.Init_Timer1) + i.Init_Timer2_PWM 0x08000c48 Section 0 initialisation.o(i.Init_Timer2_PWM) + i.Init_Timer3_Slave 0x08000d64 Section 0 initialisation.o(i.Init_Timer3_Slave) + i.Init_Timer4 0x08000dd4 Section 0 initialisation.o(i.Init_Timer4) + i.Port_IO_Reset 0x08000e48 Section 0 pilote_io_1.o(i.Port_IO_Reset) + i.Port_IO_Set 0x08000e58 Section 0 pilote_io_1.o(i.Port_IO_Set) + i.SysTick_Handler 0x08000e68 Section 0 timer_systick_1.o(i.SysTick_Handler) + i.Systick_Period 0x08000e78 Section 0 timer_systick_1.o(i.Systick_Period) + i.Systick_Prio_IT 0x08000f88 Section 0 timer_systick_1.o(i.Systick_Prio_IT) + i.TIM1_CC_IRQHandler 0x08000fac Section 0 fonctiontimer.o(i.TIM1_CC_IRQHandler) + i.TIM1_UP_IRQHandler 0x08001060 Section 0 fonctiontimer.o(i.TIM1_UP_IRQHandler) + i.TIM2_IRQHandler 0x0800110c Section 0 fonctiontimer.o(i.TIM2_IRQHandler) + i.TIM3_IRQHandler 0x08001110 Section 0 fonctiontimer.o(i.TIM3_IRQHandler) + i.TIM4_IRQHandler 0x08001160 Section 0 fonctiontimer.o(i.TIM4_IRQHandler) + i.__scatterload_copy 0x080011cc Section 14 handlers.o(i.__scatterload_copy) + i.__scatterload_null 0x080011da Section 2 handlers.o(i.__scatterload_null) + i.__scatterload_zeroinit 0x080011dc Section 14 handlers.o(i.__scatterload_zeroinit) + moncode 0x080011ec Section 10 principale.o(moncode) + moncode 0x080011f8 Section 92 fonctionetape.o(moncode) + moncode 0x08001254 Section 64 fonctionetape2.o(moncode) + moncode 0x08001294 Section 200 foncasm.o(moncode) .data 0x20000000 Section 19 initialisation.o(.data) .data 0x20000014 Section 24 fonctiontimer.o(.data) incre 0x20000024 Data 4 fonctiontimer.o(.data) Compteur 0x20000028 Data 4 fonctiontimer.o(.data) .data 0x2000002c Section 96 warning.o(.data) - .data 0x2000008c Section 4 timer_systick_1.o(.data) Ptr_Systick 0x2000008c Data 4 timer_systick_1.o(.data) - MesDonnees 0x20000090 Section 21 fonctionetape2.o(MesDonnees) + .data 0x2000008c Section 4 timer_systick_1.o(.data) Barette1 0x20000090 Data 3 fonctionetape2.o(MesDonnees) + MesDonnees 0x20000090 Section 21 fonctionetape2.o(MesDonnees) STACK 0x200000a8 Section 1024 startup_stm32f10x_md.o(STACK) Global Symbols Symbol Name Value Ov Type Size Object(Section) - BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OTIME$ROPI$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE - __arm_fini_ - Undefined Weak Reference + BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$~IW$USESV6$~STKCKD$USESV7$~SHL$OTIME$ROPI$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE __cpp_initialize__aeabi_ - Undefined Weak Reference __cxa_finalize - Undefined Weak Reference __decompress - Undefined Weak Reference @@ -309,112 +303,111 @@ Image Symbol Table _main_clock 0x080000f5 Thumb Code 0 entry7b.o(.ARM.Collect$$$$00000008) _main_cpp_init 0x080000f5 Thumb Code 0 entry8b.o(.ARM.Collect$$$$0000000A) _main_init 0x080000f5 Thumb Code 0 entry9a.o(.ARM.Collect$$$$0000000B) - __rt_lib_shutdown_fini 0x080000fd Thumb Code 0 entry12b.o(.ARM.Collect$$$$0000000E) - __rt_final_cpp 0x08000101 Thumb Code 0 entry10a.o(.ARM.Collect$$$$0000000F) - __rt_final_exit 0x08000101 Thumb Code 0 entry11a.o(.ARM.Collect$$$$00000011) - Reset_Handler 0x08000105 Thumb Code 8 startup_stm32f10x_md.o(.text) - NMI_Handler 0x0800010d Thumb Code 2 startup_stm32f10x_md.o(.text) - HardFault_Handler 0x0800010f Thumb Code 2 startup_stm32f10x_md.o(.text) - MemManage_Handler 0x08000111 Thumb Code 2 startup_stm32f10x_md.o(.text) - BusFault_Handler 0x08000113 Thumb Code 2 startup_stm32f10x_md.o(.text) - UsageFault_Handler 0x08000115 Thumb Code 2 startup_stm32f10x_md.o(.text) - SVC_Handler 0x08000117 Thumb Code 2 startup_stm32f10x_md.o(.text) - DebugMon_Handler 0x08000119 Thumb Code 2 startup_stm32f10x_md.o(.text) - PendSV_Handler 0x0800011b Thumb Code 2 startup_stm32f10x_md.o(.text) - ADC1_2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - CAN1_RX1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - CAN1_SCE_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - DMA1_Channel1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - DMA1_Channel2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - DMA1_Channel3_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - DMA1_Channel4_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - DMA1_Channel5_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - DMA1_Channel6_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - DMA1_Channel7_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - EXTI0_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - EXTI15_10_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - EXTI1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - EXTI2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - EXTI3_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - EXTI4_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - EXTI9_5_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - FLASH_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - I2C1_ER_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - I2C1_EV_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - I2C2_ER_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - I2C2_EV_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - PVD_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - RCC_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - RTCAlarm_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - RTC_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - SPI1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - SPI2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - TAMPER_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - TIM1_BRK_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - TIM1_TRG_COM_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - USART1_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - USART2_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - USART3_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - USBWakeUp_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - USB_HP_CAN1_TX_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - USB_LP_CAN1_RX0_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - WWDG_IRQHandler 0x0800011f Thumb Code 0 startup_stm32f10x_md.o(.text) - __aeabi_fmul 0x08000129 Thumb Code 100 fmul.o(.text) - __aeabi_fdiv 0x0800018d Thumb Code 124 fdiv.o(.text) - __aeabi_dmul 0x08000209 Thumb Code 228 dmul.o(.text) - __aeabi_ddiv 0x080002ed Thumb Code 222 ddiv.o(.text) - __aeabi_ui2f 0x080003cb Thumb Code 10 ffltui.o(.text) - __aeabi_f2uiz 0x080003d5 Thumb Code 40 ffixui.o(.text) - __aeabi_f2d 0x080003fd Thumb Code 38 f2d.o(.text) - __aeabi_cdcmpeq 0x08000425 Thumb Code 0 cdcmple.o(.text) - __aeabi_cdcmple 0x08000425 Thumb Code 48 cdcmple.o(.text) - __aeabi_cdrcmple 0x08000455 Thumb Code 48 cdrcmple.o(.text) - __aeabi_d2f 0x08000485 Thumb Code 56 d2f.o(.text) - __I$use$fp 0x080004bd Thumb Code 0 iusefp.o(.text) - _float_round 0x080004bd Thumb Code 18 fepilogue.o(.text) - _float_epilogue 0x080004cf Thumb Code 92 fepilogue.o(.text) - _double_round 0x0800052b Thumb Code 30 depilogue.o(.text) - _double_epilogue 0x08000549 Thumb Code 156 depilogue.o(.text) - __scatterload 0x080005e5 Thumb Code 28 init.o(.text) - __scatterload_rt2 0x080005e5 Thumb Code 0 init.o(.text) - __aeabi_llsl 0x08000609 Thumb Code 30 llshl.o(.text) - _ll_shift_l 0x08000609 Thumb Code 0 llshl.o(.text) - __aeabi_llsr 0x08000627 Thumb Code 32 llushr.o(.text) - _ll_ushift_r 0x08000627 Thumb Code 0 llushr.o(.text) - Anim 0x08000649 Thumb Code 32 fonctiontimer.o(i.Anim) - GPIO_Configure 0x08000671 Thumb Code 314 pilote_io_1.o(i.GPIO_Configure) - Init_Cible 0x080007bd Thumb Code 218 initialisation.o(i.Init_Cible) - Init_Dot 0x080008c9 Thumb Code 112 initialisation.o(i.Init_Dot) - Init_Port 0x08000941 Thumb Code 134 initialisation.o(i.Init_Port) - Init_Timer1 0x080009d1 Thumb Code 328 initialisation.o(i.Init_Timer1) - Init_Timer2_PWM 0x08000b3d Thumb Code 262 initialisation.o(i.Init_Timer2_PWM) - Init_Timer3_Slave 0x08000c59 Thumb Code 94 initialisation.o(i.Init_Timer3_Slave) - Init_Timer4 0x08000cc9 Thumb Code 100 initialisation.o(i.Init_Timer4) - Port_IO_Reset 0x08000d3d Thumb Code 16 pilote_io_1.o(i.Port_IO_Reset) - Port_IO_Set 0x08000d4d Thumb Code 16 pilote_io_1.o(i.Port_IO_Set) - SysTick_Handler 0x08000e45 Thumb Code 10 timer_systick_1.o(i.SysTick_Handler) - SystemInit 0x08000e55 Thumb Code 78 system_stm32f10x.o(i.SystemInit) - Systick_Period 0x08000eb5 Thumb Code 256 timer_systick_1.o(i.Systick_Period) - Systick_Prio_IT 0x08000fc5 Thumb Code 28 timer_systick_1.o(i.Systick_Prio_IT) - TIM1_CC_IRQHandler 0x08000fe9 Thumb Code 158 fonctiontimer.o(i.TIM1_CC_IRQHandler) - TIM1_UP_IRQHandler 0x0800109d Thumb Code 134 fonctiontimer.o(i.TIM1_UP_IRQHandler) - TIM2_IRQHandler 0x08001149 Thumb Code 4 fonctiontimer.o(i.TIM2_IRQHandler) - TIM3_IRQHandler 0x0800114d Thumb Code 68 fonctiontimer.o(i.TIM3_IRQHandler) - TIM4_IRQHandler 0x0800119d Thumb Code 84 fonctiontimer.o(i.TIM4_IRQHandler) - __scatterload_copy 0x08001209 Thumb Code 14 handlers.o(i.__scatterload_copy) - __scatterload_null 0x08001217 Thumb Code 2 handlers.o(i.__scatterload_null) - __scatterload_zeroinit 0x08001219 Thumb Code 14 handlers.o(i.__scatterload_zeroinit) - main 0x08001229 Thumb Code 10 principale.o(moncode) - Eteint_LED 0x08001235 Thumb Code 22 fonctionetape.o(moncode) - Allume_LED 0x0800124b Thumb Code 22 fonctionetape.o(moncode) - Inverse_LED 0x08001261 Thumb Code 42 fonctionetape.o(moncode) - Set_SCLK 0x08001291 Thumb Code 22 fonctionetape2.o(moncode) - Reset_SCLK 0x080012a7 Thumb Code 22 fonctionetape2.o(moncode) - DriverGlobal 0x080012bd Thumb Code 26 fonctionetape2.o(moncode) - Envoie192Boucle 0x080012e5 Thumb Code 108 foncasm.o(moncode) - Envoie96Dot 0x08001351 Thumb Code 78 foncasm.o(moncode) - Region$$Table$$Base 0x080013ac Number 0 anon$$obj.o(Region$$Table) - Region$$Table$$Limit 0x080013cc Number 0 anon$$obj.o(Region$$Table) + __rt_final_cpp 0x080000fd Thumb Code 0 entry10a.o(.ARM.Collect$$$$0000000D) + __rt_final_exit 0x080000fd Thumb Code 0 entry11a.o(.ARM.Collect$$$$0000000F) + Reset_Handler 0x08000101 Thumb Code 8 startup_stm32f10x_md.o(.text) + NMI_Handler 0x08000109 Thumb Code 2 startup_stm32f10x_md.o(.text) + HardFault_Handler 0x0800010b Thumb Code 2 startup_stm32f10x_md.o(.text) + MemManage_Handler 0x0800010d Thumb Code 2 startup_stm32f10x_md.o(.text) + BusFault_Handler 0x0800010f Thumb Code 2 startup_stm32f10x_md.o(.text) + UsageFault_Handler 0x08000111 Thumb Code 2 startup_stm32f10x_md.o(.text) + SVC_Handler 0x08000113 Thumb Code 2 startup_stm32f10x_md.o(.text) + DebugMon_Handler 0x08000115 Thumb Code 2 startup_stm32f10x_md.o(.text) + PendSV_Handler 0x08000117 Thumb Code 2 startup_stm32f10x_md.o(.text) + ADC1_2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + CAN1_RX1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + CAN1_SCE_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel3_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel4_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel5_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel6_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + DMA1_Channel7_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI0_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI15_10_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI3_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI4_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + EXTI9_5_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + FLASH_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + I2C1_ER_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + I2C1_EV_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + I2C2_ER_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + I2C2_EV_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + PVD_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + RCC_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + RTCAlarm_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + RTC_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + SPI1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + SPI2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + TAMPER_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + TIM1_BRK_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + TIM1_TRG_COM_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + USART1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + USART2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + USART3_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + USBWakeUp_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + USB_HP_CAN1_TX_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + USB_LP_CAN1_RX0_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + WWDG_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f10x_md.o(.text) + __aeabi_fmul 0x08000125 Thumb Code 100 fmul.o(.text) + __aeabi_fdiv 0x08000189 Thumb Code 124 fdiv.o(.text) + __aeabi_dmul 0x08000205 Thumb Code 228 dmul.o(.text) + __aeabi_ddiv 0x080002e9 Thumb Code 222 ddiv.o(.text) + __aeabi_ui2f 0x080003c7 Thumb Code 10 ffltui.o(.text) + __aeabi_f2uiz 0x080003d1 Thumb Code 40 ffixui.o(.text) + __aeabi_f2d 0x080003f9 Thumb Code 38 f2d.o(.text) + __aeabi_cdcmpeq 0x08000421 Thumb Code 0 cdcmple.o(.text) + __aeabi_cdcmple 0x08000421 Thumb Code 48 cdcmple.o(.text) + __aeabi_cdrcmple 0x08000451 Thumb Code 48 cdrcmple.o(.text) + __aeabi_d2f 0x08000481 Thumb Code 56 d2f.o(.text) + __I$use$fp 0x080004b9 Thumb Code 0 iusefp.o(.text) + _float_round 0x080004b9 Thumb Code 18 fepilogue.o(.text) + _float_epilogue 0x080004cb Thumb Code 92 fepilogue.o(.text) + _double_round 0x08000527 Thumb Code 30 depilogue.o(.text) + _double_epilogue 0x08000545 Thumb Code 156 depilogue.o(.text) + __scatterload 0x080005e1 Thumb Code 28 init.o(.text) + __scatterload_rt2 0x080005e1 Thumb Code 0 init.o(.text) + __aeabi_llsl 0x08000605 Thumb Code 30 llshl.o(.text) + _ll_shift_l 0x08000605 Thumb Code 0 llshl.o(.text) + __aeabi_llsr 0x08000623 Thumb Code 32 llushr.o(.text) + _ll_ushift_r 0x08000623 Thumb Code 0 llushr.o(.text) + SystemInit 0x08000645 Thumb Code 272 system_stm32f10x.o(.text.SystemInit) + Anim 0x08000755 Thumb Code 32 fonctiontimer.o(i.Anim) + GPIO_Configure 0x0800077d Thumb Code 314 pilote_io_1.o(i.GPIO_Configure) + Init_Cible 0x080008c9 Thumb Code 218 initialisation.o(i.Init_Cible) + Init_Dot 0x080009d5 Thumb Code 112 initialisation.o(i.Init_Dot) + Init_Port 0x08000a4d Thumb Code 134 initialisation.o(i.Init_Port) + Init_Timer1 0x08000add Thumb Code 328 initialisation.o(i.Init_Timer1) + Init_Timer2_PWM 0x08000c49 Thumb Code 262 initialisation.o(i.Init_Timer2_PWM) + Init_Timer3_Slave 0x08000d65 Thumb Code 94 initialisation.o(i.Init_Timer3_Slave) + Init_Timer4 0x08000dd5 Thumb Code 100 initialisation.o(i.Init_Timer4) + Port_IO_Reset 0x08000e49 Thumb Code 16 pilote_io_1.o(i.Port_IO_Reset) + Port_IO_Set 0x08000e59 Thumb Code 16 pilote_io_1.o(i.Port_IO_Set) + SysTick_Handler 0x08000e69 Thumb Code 10 timer_systick_1.o(i.SysTick_Handler) + Systick_Period 0x08000e79 Thumb Code 256 timer_systick_1.o(i.Systick_Period) + Systick_Prio_IT 0x08000f89 Thumb Code 28 timer_systick_1.o(i.Systick_Prio_IT) + TIM1_CC_IRQHandler 0x08000fad Thumb Code 158 fonctiontimer.o(i.TIM1_CC_IRQHandler) + TIM1_UP_IRQHandler 0x08001061 Thumb Code 134 fonctiontimer.o(i.TIM1_UP_IRQHandler) + TIM2_IRQHandler 0x0800110d Thumb Code 4 fonctiontimer.o(i.TIM2_IRQHandler) + TIM3_IRQHandler 0x08001111 Thumb Code 68 fonctiontimer.o(i.TIM3_IRQHandler) + TIM4_IRQHandler 0x08001161 Thumb Code 84 fonctiontimer.o(i.TIM4_IRQHandler) + __scatterload_copy 0x080011cd Thumb Code 14 handlers.o(i.__scatterload_copy) + __scatterload_null 0x080011db Thumb Code 2 handlers.o(i.__scatterload_null) + __scatterload_zeroinit 0x080011dd Thumb Code 14 handlers.o(i.__scatterload_zeroinit) + main 0x080011ed Thumb Code 10 principale.o(moncode) + Eteint_LED 0x080011f9 Thumb Code 22 fonctionetape.o(moncode) + Allume_LED 0x0800120f Thumb Code 22 fonctionetape.o(moncode) + Inverse_LED 0x08001225 Thumb Code 42 fonctionetape.o(moncode) + Set_SCLK 0x08001255 Thumb Code 14 fonctionetape2.o(moncode) + Reset_SCLK 0x08001263 Thumb Code 14 fonctionetape2.o(moncode) + DriverGlobal 0x08001271 Thumb Code 26 fonctionetape2.o(moncode) + Envoie192Boucle 0x08001295 Thumb Code 108 foncasm.o(moncode) + Envoie96Dot 0x08001301 Thumb Code 78 foncasm.o(moncode) + Region$$Table$$Base 0x0800135c Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x0800137c Number 0 anon$$obj.o(Region$$Table) PrtSurImage 0x20000000 Data 4 initialisation.o(.data) BarretEnCours 0x20000004 Data 4 initialisation.o(.data) DataSend 0x20000008 Data 1 initialisation.o(.data) @@ -435,87 +428,84 @@ Memory Map of the image Image Entry point : 0x080000ed - Load Region LR_IROM1 (Base: 0x08000000, Size: 0x00001474, Max: 0x00020000, ABSOLUTE) + Load Region LR_IROM1 (Base: 0x08000000, Size: 0x00001428, Max: 0x00020000, ABSOLUTE) - Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x000013cc, Max: 0x00020000, ABSOLUTE) + Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x0000137c, Max: 0x00020000, ABSOLUTE) Exec Addr Load Addr Size Type Attr Idx E Section Name Object 0x08000000 0x08000000 0x000000ec Data RO 20 RESET startup_stm32f10x_md.o - 0x080000ec 0x080000ec 0x00000000 Code RO 447 * .ARM.Collect$$$$00000000 mc_w.l(entry.o) - 0x080000ec 0x080000ec 0x00000004 Code RO 470 .ARM.Collect$$$$00000001 mc_w.l(entry2.o) - 0x080000f0 0x080000f0 0x00000004 Code RO 473 .ARM.Collect$$$$00000004 mc_w.l(entry5.o) - 0x080000f4 0x080000f4 0x00000000 Code RO 475 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o) - 0x080000f4 0x080000f4 0x00000000 Code RO 477 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o) - 0x080000f4 0x080000f4 0x00000008 Code RO 478 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o) - 0x080000fc 0x080000fc 0x00000004 Code RO 485 .ARM.Collect$$$$0000000E mc_w.l(entry12b.o) - 0x08000100 0x08000100 0x00000000 Code RO 480 .ARM.Collect$$$$0000000F mc_w.l(entry10a.o) - 0x08000100 0x08000100 0x00000000 Code RO 482 .ARM.Collect$$$$00000011 mc_w.l(entry11a.o) - 0x08000100 0x08000100 0x00000004 Code RO 471 .ARM.Collect$$$$00002712 mc_w.l(entry2.o) - 0x08000104 0x08000104 0x00000024 Code RO 21 .text startup_stm32f10x_md.o - 0x08000128 0x08000128 0x00000064 Code RO 450 .text mf_w.l(fmul.o) - 0x0800018c 0x0800018c 0x0000007c Code RO 452 .text mf_w.l(fdiv.o) - 0x08000208 0x08000208 0x000000e4 Code RO 454 .text mf_w.l(dmul.o) - 0x080002ec 0x080002ec 0x000000de Code RO 456 .text mf_w.l(ddiv.o) - 0x080003ca 0x080003ca 0x0000000a Code RO 458 .text mf_w.l(ffltui.o) - 0x080003d4 0x080003d4 0x00000028 Code RO 460 .text mf_w.l(ffixui.o) - 0x080003fc 0x080003fc 0x00000026 Code RO 462 .text mf_w.l(f2d.o) - 0x08000422 0x08000422 0x00000002 PAD - 0x08000424 0x08000424 0x00000030 Code RO 464 .text mf_w.l(cdcmple.o) - 0x08000454 0x08000454 0x00000030 Code RO 466 .text mf_w.l(cdrcmple.o) - 0x08000484 0x08000484 0x00000038 Code RO 468 .text mf_w.l(d2f.o) - 0x080004bc 0x080004bc 0x00000000 Code RO 486 .text mc_w.l(iusefp.o) - 0x080004bc 0x080004bc 0x0000006e Code RO 487 .text mf_w.l(fepilogue.o) - 0x0800052a 0x0800052a 0x000000ba Code RO 489 .text mf_w.l(depilogue.o) - 0x080005e4 0x080005e4 0x00000024 Code RO 491 .text mc_w.l(init.o) - 0x08000608 0x08000608 0x0000001e Code RO 493 .text mc_w.l(llshl.o) - 0x08000626 0x08000626 0x00000020 Code RO 495 .text mc_w.l(llushr.o) - 0x08000646 0x08000646 0x00000002 PAD - 0x08000648 0x08000648 0x00000028 Code RO 223 i.Anim Matos.lib(fonctiontimer.o) - 0x08000670 0x08000670 0x0000014c Code RO 346 i.GPIO_Configure Matos.lib(pilote_io_1.o) - 0x080007bc 0x080007bc 0x0000010c Code RO 97 i.Init_Cible Matos.lib(initialisation.o) - 0x080008c8 0x080008c8 0x00000078 Code RO 98 i.Init_Dot Matos.lib(initialisation.o) - 0x08000940 0x08000940 0x00000090 Code RO 99 i.Init_Port Matos.lib(initialisation.o) - 0x080009d0 0x080009d0 0x0000016c Code RO 101 i.Init_Timer1 Matos.lib(initialisation.o) - 0x08000b3c 0x08000b3c 0x0000011c Code RO 102 i.Init_Timer2_PWM Matos.lib(initialisation.o) - 0x08000c58 0x08000c58 0x00000070 Code RO 103 i.Init_Timer3_Slave Matos.lib(initialisation.o) - 0x08000cc8 0x08000cc8 0x00000074 Code RO 104 i.Init_Timer4 Matos.lib(initialisation.o) - 0x08000d3c 0x08000d3c 0x00000010 Code RO 352 i.Port_IO_Reset Matos.lib(pilote_io_1.o) - 0x08000d4c 0x08000d4c 0x00000010 Code RO 353 i.Port_IO_Set Matos.lib(pilote_io_1.o) - 0x08000d5c 0x08000d5c 0x00000008 Code RO 28 i.SetSysClock system_stm32f10x.o - 0x08000d64 0x08000d64 0x000000e0 Code RO 29 i.SetSysClockTo72 system_stm32f10x.o - 0x08000e44 0x08000e44 0x00000010 Code RO 412 i.SysTick_Handler Matos.lib(timer_systick_1.o) - 0x08000e54 0x08000e54 0x00000060 Code RO 31 i.SystemInit system_stm32f10x.o - 0x08000eb4 0x08000eb4 0x00000110 Code RO 413 i.Systick_Period Matos.lib(timer_systick_1.o) - 0x08000fc4 0x08000fc4 0x00000024 Code RO 414 i.Systick_Prio_IT Matos.lib(timer_systick_1.o) - 0x08000fe8 0x08000fe8 0x000000b4 Code RO 232 i.TIM1_CC_IRQHandler Matos.lib(fonctiontimer.o) - 0x0800109c 0x0800109c 0x000000ac Code RO 233 i.TIM1_UP_IRQHandler Matos.lib(fonctiontimer.o) - 0x08001148 0x08001148 0x00000004 Code RO 234 i.TIM2_IRQHandler Matos.lib(fonctiontimer.o) - 0x0800114c 0x0800114c 0x00000050 Code RO 235 i.TIM3_IRQHandler Matos.lib(fonctiontimer.o) - 0x0800119c 0x0800119c 0x0000006c Code RO 236 i.TIM4_IRQHandler Matos.lib(fonctiontimer.o) - 0x08001208 0x08001208 0x0000000e Code RO 499 i.__scatterload_copy mc_w.l(handlers.o) - 0x08001216 0x08001216 0x00000002 Code RO 500 i.__scatterload_null mc_w.l(handlers.o) - 0x08001218 0x08001218 0x0000000e Code RO 501 i.__scatterload_zeroinit mc_w.l(handlers.o) - 0x08001226 0x08001226 0x00000002 PAD - 0x08001228 0x08001228 0x0000000a Code RO 2 moncode principale.o - 0x08001232 0x08001232 0x00000002 PAD - 0x08001234 0x08001234 0x0000005c Code RO 9 moncode fonctionetape.o - 0x08001290 0x08001290 0x00000054 Code RO 14 moncode fonctionetape2.o - 0x080012e4 0x080012e4 0x000000c8 Code RO 339 moncode Matos.lib(foncasm.o) - 0x080013ac 0x080013ac 0x00000020 Data RO 497 Region$$Table anon$$obj.o + 0x080000ec 0x080000ec 0x00000000 Code RO 393 * .ARM.Collect$$$$00000000 mc_w.l(entry.o) + 0x080000ec 0x080000ec 0x00000004 Code RO 416 .ARM.Collect$$$$00000001 mc_w.l(entry2.o) + 0x080000f0 0x080000f0 0x00000004 Code RO 419 .ARM.Collect$$$$00000004 mc_w.l(entry5.o) + 0x080000f4 0x080000f4 0x00000000 Code RO 421 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o) + 0x080000f4 0x080000f4 0x00000000 Code RO 423 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o) + 0x080000f4 0x080000f4 0x00000008 Code RO 424 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o) + 0x080000fc 0x080000fc 0x00000000 Code RO 426 .ARM.Collect$$$$0000000D mc_w.l(entry10a.o) + 0x080000fc 0x080000fc 0x00000000 Code RO 428 .ARM.Collect$$$$0000000F mc_w.l(entry11a.o) + 0x080000fc 0x080000fc 0x00000004 Code RO 417 .ARM.Collect$$$$00002712 mc_w.l(entry2.o) + 0x08000100 0x08000100 0x00000024 Code RO 21 .text startup_stm32f10x_md.o + 0x08000124 0x08000124 0x00000064 Code RO 396 .text mf_w.l(fmul.o) + 0x08000188 0x08000188 0x0000007c Code RO 398 .text mf_w.l(fdiv.o) + 0x08000204 0x08000204 0x000000e4 Code RO 400 .text mf_w.l(dmul.o) + 0x080002e8 0x080002e8 0x000000de Code RO 402 .text mf_w.l(ddiv.o) + 0x080003c6 0x080003c6 0x0000000a Code RO 404 .text mf_w.l(ffltui.o) + 0x080003d0 0x080003d0 0x00000028 Code RO 406 .text mf_w.l(ffixui.o) + 0x080003f8 0x080003f8 0x00000026 Code RO 408 .text mf_w.l(f2d.o) + 0x0800041e 0x0800041e 0x00000002 PAD + 0x08000420 0x08000420 0x00000030 Code RO 410 .text mf_w.l(cdcmple.o) + 0x08000450 0x08000450 0x00000030 Code RO 412 .text mf_w.l(cdrcmple.o) + 0x08000480 0x08000480 0x00000038 Code RO 414 .text mf_w.l(d2f.o) + 0x080004b8 0x080004b8 0x00000000 Code RO 430 .text mc_w.l(iusefp.o) + 0x080004b8 0x080004b8 0x0000006e Code RO 431 .text mf_w.l(fepilogue.o) + 0x08000526 0x08000526 0x000000ba Code RO 433 .text mf_w.l(depilogue.o) + 0x080005e0 0x080005e0 0x00000024 Code RO 435 .text mc_w.l(init.o) + 0x08000604 0x08000604 0x0000001e Code RO 437 .text mc_w.l(llshl.o) + 0x08000622 0x08000622 0x00000020 Code RO 439 .text mc_w.l(llushr.o) + 0x08000642 0x08000642 0x00000002 PAD + 0x08000644 0x08000644 0x00000110 Code RO 26 .text.SystemInit system_stm32f10x.o + 0x08000754 0x08000754 0x00000028 Code RO 169 i.Anim Matos.lib(fonctiontimer.o) + 0x0800077c 0x0800077c 0x0000014c Code RO 292 i.GPIO_Configure Matos.lib(pilote_io_1.o) + 0x080008c8 0x080008c8 0x0000010c Code RO 42 i.Init_Cible Matos.lib(initialisation.o) + 0x080009d4 0x080009d4 0x00000078 Code RO 43 i.Init_Dot Matos.lib(initialisation.o) + 0x08000a4c 0x08000a4c 0x00000090 Code RO 44 i.Init_Port Matos.lib(initialisation.o) + 0x08000adc 0x08000adc 0x0000016c Code RO 46 i.Init_Timer1 Matos.lib(initialisation.o) + 0x08000c48 0x08000c48 0x0000011c Code RO 47 i.Init_Timer2_PWM Matos.lib(initialisation.o) + 0x08000d64 0x08000d64 0x00000070 Code RO 48 i.Init_Timer3_Slave Matos.lib(initialisation.o) + 0x08000dd4 0x08000dd4 0x00000074 Code RO 49 i.Init_Timer4 Matos.lib(initialisation.o) + 0x08000e48 0x08000e48 0x00000010 Code RO 298 i.Port_IO_Reset Matos.lib(pilote_io_1.o) + 0x08000e58 0x08000e58 0x00000010 Code RO 299 i.Port_IO_Set Matos.lib(pilote_io_1.o) + 0x08000e68 0x08000e68 0x00000010 Code RO 358 i.SysTick_Handler Matos.lib(timer_systick_1.o) + 0x08000e78 0x08000e78 0x00000110 Code RO 359 i.Systick_Period Matos.lib(timer_systick_1.o) + 0x08000f88 0x08000f88 0x00000024 Code RO 360 i.Systick_Prio_IT Matos.lib(timer_systick_1.o) + 0x08000fac 0x08000fac 0x000000b4 Code RO 178 i.TIM1_CC_IRQHandler Matos.lib(fonctiontimer.o) + 0x08001060 0x08001060 0x000000ac Code RO 179 i.TIM1_UP_IRQHandler Matos.lib(fonctiontimer.o) + 0x0800110c 0x0800110c 0x00000004 Code RO 180 i.TIM2_IRQHandler Matos.lib(fonctiontimer.o) + 0x08001110 0x08001110 0x00000050 Code RO 181 i.TIM3_IRQHandler Matos.lib(fonctiontimer.o) + 0x08001160 0x08001160 0x0000006c Code RO 182 i.TIM4_IRQHandler Matos.lib(fonctiontimer.o) + 0x080011cc 0x080011cc 0x0000000e Code RO 443 i.__scatterload_copy mc_w.l(handlers.o) + 0x080011da 0x080011da 0x00000002 Code RO 444 i.__scatterload_null mc_w.l(handlers.o) + 0x080011dc 0x080011dc 0x0000000e Code RO 445 i.__scatterload_zeroinit mc_w.l(handlers.o) + 0x080011ea 0x080011ea 0x00000002 PAD + 0x080011ec 0x080011ec 0x0000000a Code RO 2 moncode principale.o + 0x080011f6 0x080011f6 0x00000002 PAD + 0x080011f8 0x080011f8 0x0000005c Code RO 9 moncode fonctionetape.o + 0x08001254 0x08001254 0x00000040 Code RO 14 moncode fonctionetape2.o + 0x08001294 0x08001294 0x000000c8 Code RO 285 moncode Matos.lib(foncasm.o) + 0x0800135c 0x0800135c 0x00000020 Data RO 442 Region$$Table anon$$obj.o - Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x080013cc, Size: 0x000004a8, Max: 0x00005000, ABSOLUTE) + Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x08001380, Size: 0x000004a8, Max: 0x00005000, ABSOLUTE) Exec Addr Load Addr Size Type Attr Idx E Section Name Object - 0x20000000 0x080013cc 0x00000013 Data RW 105 .data Matos.lib(initialisation.o) - 0x20000013 0x080013df 0x00000001 PAD - 0x20000014 0x080013e0 0x00000018 Data RW 237 .data Matos.lib(fonctiontimer.o) - 0x2000002c 0x080013f8 0x00000060 Data RW 329 .data Matos.lib(warning.o) - 0x2000008c 0x08001458 0x00000004 Data RW 415 .data Matos.lib(timer_systick_1.o) - 0x20000090 0x0800145c 0x00000015 Data RW 13 MesDonnees fonctionetape2.o - 0x200000a5 0x08001471 0x00000003 PAD + 0x20000000 0x08001380 0x00000013 Data RW 50 .data Matos.lib(initialisation.o) + 0x20000013 0x08001393 0x00000001 PAD + 0x20000014 0x08001394 0x00000018 Data RW 183 .data Matos.lib(fonctiontimer.o) + 0x2000002c 0x080013ac 0x00000060 Data RW 275 .data Matos.lib(warning.o) + 0x2000008c 0x0800140c 0x00000004 Data RW 361 .data Matos.lib(timer_systick_1.o) + 0x20000090 0x08001410 0x00000015 Data RW 13 MesDonnees fonctionetape2.o + 0x200000a5 0x08001425 0x00000003 PAD 0x200000a8 - 0x00000400 Zero RW 18 STACK startup_stm32f10x_md.o @@ -527,13 +517,13 @@ Image component sizes Code (inc. data) RO Data RW Data ZI Data Debug Object Name 92 6 0 0 0 408 fonctionetape.o - 84 14 0 21 0 400 fonctionetape2.o + 64 10 0 21 0 400 fonctionetape2.o 10 0 0 0 0 328 principale.o 36 8 236 0 1024 796 startup_stm32f10x_md.o - 328 28 0 0 0 6425 system_stm32f10x.o + 272 0 0 0 0 2781 system_stm32f10x.o ---------------------------------------------------------------------- - 552 56 268 24 1024 8357 Object Totals + 476 24 268 24 1024 4713 Object Totals 0 0 32 0 0 0 (incl. Generated) 2 0 0 3 0 0 (incl. Padding) @@ -543,14 +533,13 @@ Image component sizes 200 14 0 0 0 460 foncasm.o 584 104 0 24 0 3481 fonctiontimer.o - 1408 160 0 19 0 228380 initialisation.o + 1408 160 0 19 0 229824 initialisation.o 364 18 0 0 0 2487 pilote_io_1.o 324 30 0 4 0 2509 timer_systick_1.o 0 0 0 96 0 582 warning.o 0 0 0 0 0 0 entry.o 0 0 0 0 0 0 entry10a.o 0 0 0 0 0 0 entry11a.o - 4 0 0 0 0 0 entry12b.o 8 4 0 0 0 0 entry2.o 4 0 0 0 0 0 entry5.o 0 0 0 0 0 0 entry7b.o @@ -575,19 +564,19 @@ Image component sizes 100 0 0 0 0 76 fmul.o ---------------------------------------------------------------------- - 4248 342 0 144 0 239235 Library Totals + 4244 342 0 144 0 240679 Library Totals 6 0 0 1 0 0 (incl. Padding) ---------------------------------------------------------------------- Code (inc. data) RO Data RW Data ZI Data Debug Library Name - 2880 326 0 143 0 237899 Matos.lib - 152 16 0 0 0 204 mc_w.l + 2880 326 0 143 0 239343 Matos.lib + 148 16 0 0 0 204 mc_w.l 1210 0 0 0 0 1132 mf_w.l ---------------------------------------------------------------------- - 4248 342 0 144 0 239235 Library Totals + 4244 342 0 144 0 240679 Library Totals ---------------------------------------------------------------------- @@ -596,15 +585,15 @@ Image component sizes Code (inc. data) RO Data RW Data ZI Data Debug - 4800 398 268 168 1024 245872 Grand Totals - 4800 398 268 168 1024 245872 ELF Image Totals - 4800 398 268 168 0 0 ROM Totals + 4720 366 268 168 1024 243828 Grand Totals + 4720 366 268 168 1024 243828 ELF Image Totals + 4720 366 268 168 0 0 ROM Totals ============================================================================== - Total RO Size (Code + RO Data) 5068 ( 4.95kB) + Total RO Size (Code + RO Data) 4988 ( 4.87kB) Total RW Size (RW Data + ZI Data) 1192 ( 1.16kB) - Total ROM Size (Code + RO Data + RW Data) 5236 ( 5.11kB) + Total ROM Size (Code + RO Data + RW Data) 5156 ( 5.04kB) ============================================================================== diff --git a/Listings/fonctionetape.lst b/Listings/fonctionetape.lst index aa9084d..c9f1c35 100644 --- a/Listings/fonctionetape.lst +++ b/Listings/fonctionetape.lst @@ -294,14 +294,14 @@ ARM Macro Assembler Page 5 ******************* 119 00000056 END 00 00 40010C00 -Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw -ork --depend=.\objects\fonctionetape.d -o.\objects\fonctionetape.o -I.\RTE\Devi -ce\STM32F103RB -I.\RTE\_Simul_ -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\ -CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Dev -ice\Include --predefine="__EVAL SETA 1" --predefine="__MICROLIB SETA 1" --prede -fine="__UVISION_VERSION SETA 534" --predefine="_RTE_ SETA 1" --predefine="STM32 -F10X_MD SETA 1" --predefine="_RTE_ SETA 1" --predefine="STM32F10X_MD SETA 1" -- -list=.\listings\fonctionetape.lst FonctionEtape.asm +Command Line: --debug --xref --diag_suppress=9931,A1950W --cpu=Cortex-M3 --depe +nd=.\objects\fonctionetape.d -o.\objects\fonctionetape.o -I.\RTE\Device\STM32F1 +03RB -I.\RTE\_Simul_ -IC:\Users\alzyo\AppData\Local\Arm\Packs\ARM\CMSIS\5.9.0\C +MSIS\Core\Include -IC:\Users\alzyo\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2 +.4.0\Device\Include --predefine="__EVAL SETA 1" --predefine="__MICROLIB SETA 1" + --predefine="__UVISION_VERSION SETA 538" --predefine="_RTE_ SETA 1" --predefin +e="STM32F10X_MD SETA 1" --predefine="_RTE_ SETA 1" --predefine="STM32F10X_MD SE +TA 1" --list=.\listings\fonctionetape.lst FonctionEtape.asm diff --git a/Listings/fonctionetape2.lst b/Listings/fonctionetape2.lst index 512ea31..9ec0381 100644 --- a/Listings/fonctionetape2.lst +++ b/Listings/fonctionetape2.lst @@ -172,90 +172,86 @@ ARM Macro Assembler Page 3 51 00000000 52 00000000 Set_SCLK PROC - 53 00000000 E92D 1001 PUSH {R12,R0} ;On stocke R12 dans - R0 - 54 00000004 F8DF C040 LDR R12,=GPIOBASEA ;On recupère l'a - dresse de base - 55 00000008 F8DC 5020 LDR R5,[R12,#MaskSclk] ;Valeur à l' - adresse de l'output - - 56 0000000C F045 0520 ORR R5, R5,#(0x01 << 5) ;OU LOGIQUE - pour calculer la v - aleur a mettre dans - l'output - 57 00000010 F8AC 500C STRH R5,[R12,#0x0C] ;Etat du port B - (R5) stocké dans l' - output - 58 00000014 4770 BX LR ;Retour - 59 00000016 - 60 00000016 ENDP - 61 00000016 - 62 00000016 Reset_SCLK + 53 00000000 B407 PUSH {R0-R2} ;On stocke R0 à R2 + 54 00000002 490D LDR R1,=GPIOBASEA ;R1 -> Adresse de + GPIOA + 55 00000004 898A LDRH R2,[R1,#OffsetOutput] ;Valeur à + l'adresse d'ODR : + R2 = GPIOA->ODR + 56 00000006 F042 0220 ORR R2, R2,#(0x01 << 5) ;similaire + à GPIOA->ODR |= (1< + <5) + 57 0000000A 818A STRH R2,[R1,#OffsetOutput] ;Etat du + port B (R5) stocké + dans ODR + 58 0000000C 4770 BX LR ;Retour + 59 0000000E + 60 0000000E ENDP + 61 0000000E + 62 0000000E Reset_SCLK PROC - 63 00000016 E92D 1001 PUSH {R12,R0} ;On stocke R12 dans + 63 0000000E B407 PUSH {R0-R2} ;On stocke R0 à R2 + 64 00000010 4909 LDR R1,=GPIOBASEA ;R1 -> Adresse de + GPIOA ARM Macro Assembler Page 4 - R0 - 64 0000001A F8DF C030 LDR R12,=GPIOBASEB ;On recupère l'a - dresse de base - 65 0000001E F8DC 5020 LDR R5,[R12,#MaskSclk] ;Valeur à l' - adresse de l'SCLK - 66 00000022 F025 0520 AND R5, R5,#~(0x01 << 5) ;OU LOGIQU - E pour calculer la - valeur a mettre dan - s l'output - 67 00000026 F8AC 500C STRH R5,[R12,#0x0C] ;Etat du port B - (R5) stocké dans l' - output - 68 0000002A 4770 BX LR ;Retour - 69 0000002C - 70 0000002C ENDP - 71 0000002C - 72 0000002C ;******************************************************* + 65 00000012 898A LDRH R2,[R1,#OffsetOutput] ;Valeur à + l'adresse d'ODR : + R2 = GPIOA->ODR + 66 00000014 F022 0220 AND R2, R2,#~(0x01 << 5) ;similaire + à GPIOA->ODR &= ~( + 1<<5) + 67 00000018 818A STRH R2,[R1,#OffsetOutput] ;Etat du + port B (R5) stocké + dans ODR + 68 0000001A 4770 BX LR ;Retour + 69 0000001C + 70 0000001C ENDP + 71 0000001C + 72 0000001C ;******************************************************* ********************* - 73 0000002C ;R6 = NBLed - 74 0000002C ;R7 = *ValCourante - 75 0000002C ;R8 = ValCourante[NBLed] - 76 0000002C ;******************************************************* + 73 0000001C ;R6 = NBLed + 74 0000001C ;R7 = *ValCourante + 75 0000001C ;R8 = ValCourante[NBLed] + 76 0000001C ;******************************************************* ********************* - 77 0000002C DriverGlobal + 77 0000001C DriverGlobal PROC - 78 0000002C F7FF FFFE BL Set_SCLK ; - 79 00000030 F04F 0600 MOV R6, #0 ; - 80 00000034 WHILE_NBLED - 81 00000034 ;Pour NbLed = 1 à 48 - 82 00000034 4F06 LDR R7,=Barette1 ;On recupère l'adr + 78 0000001C F7FF FFFE BL Set_SCLK ; + 79 00000020 F04F 0600 MOV R6, #0 ; + 80 00000024 WHILE_NBLED + 81 00000024 ;Pour NbLed = 1 à 48 + 82 00000024 4F05 LDR R7,=Barette1 ;On recupère l'adr esse de base - 83 00000036 F817 8006 LDRB R8,[R7,R6] ;R8 = ValCourante[. + 83 00000026 F817 8006 LDRB R8,[R7,R6] ;R8 = ValCourante[. ..NBLed] - 84 0000003A - 85 0000003A EA4F 6808 LSL R8,#24 ;ValCourante[NBLed] + 84 0000002A + 85 0000002A EA4F 6808 LSL R8,#24 ;ValCourante[NBLed] <<24 - 86 0000003E - 87 0000003E F106 0601 ADD R6, R6, #1 ;On incrémente R6 - 88 00000042 2E2F CMP R6, #47 ; SI R6==47 alors o + 86 0000002E + 87 0000002E F106 0601 ADD R6, R6, #1 ;On incrémente R6 + 88 00000032 2E2F CMP R6, #47 ; SI R6==47 alors o n arrête la boucle - 89 00000044 D1F6 BNE WHILE_NBLED - 90 00000046 ENDP - 91 00000046 - 92 00000046 ;******************************************************* + 89 00000034 D1F6 BNE WHILE_NBLED + 90 00000036 ENDP + 91 00000036 + 92 00000036 ;******************************************************* ******************* - 93 00000046 END + 93 00000036 END 00 00 40010800 - 40010C00 00000000 -Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw -ork --depend=.\objects\fonctionetape2.d -o.\objects\fonctionetape2.o -I.\RTE\De -vice\STM32F103RB -I.\RTE\_Simul_ -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7. -0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\D -evice\Include --predefine="__EVAL SETA 1" --predefine="__MICROLIB SETA 1" --pre -define="__UVISION_VERSION SETA 534" --predefine="_RTE_ SETA 1" --predefine="STM -32F10X_MD SETA 1" --predefine="_RTE_ SETA 1" --predefine="STM32F10X_MD SETA 1" ---list=.\listings\fonctionetape2.lst FonctionEtape2.asm +Command Line: --debug --xref --diag_suppress=9931,A1950W --cpu=Cortex-M3 --depe +nd=.\objects\fonctionetape2.d -o.\objects\fonctionetape2.o -I.\RTE\Device\STM32 +F103RB -I.\RTE\_Simul_ -IC:\Users\alzyo\AppData\Local\Arm\Packs\ARM\CMSIS\5.9.0 +\CMSIS\Core\Include -IC:\Users\alzyo\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP +\2.4.0\Device\Include --predefine="__EVAL SETA 1" --predefine="__MICROLIB SETA +1" --predefine="__UVISION_VERSION SETA 538" --predefine="_RTE_ SETA 1" --predef +ine="STM32F10X_MD SETA 1" --predefine="_RTE_ SETA 1" --predefine="STM32F10X_MD +SETA 1" --list=.\listings\fonctionetape2.lst FonctionEtape2.asm @@ -285,7 +281,7 @@ Comment: MesDonnees unused ARM Macro Assembler Page 1 Alphabetic symbol ordering Relocatable symbols -DriverGlobal 0000002C +DriverGlobal 0000001C Symbol: DriverGlobal Definitions @@ -293,7 +289,7 @@ Symbol: DriverGlobal Uses At line 16 in file FonctionEtape2.asm Comment: DriverGlobal used once -Reset_SCLK 00000016 +Reset_SCLK 0000000E Symbol: Reset_SCLK Definitions @@ -310,7 +306,7 @@ Symbol: Set_SCLK At line 14 in file FonctionEtape2.asm At line 78 in file FonctionEtape2.asm -WHILE_NBLED 00000034 +WHILE_NBLED 00000024 Symbol: WHILE_NBLED Definitions @@ -340,15 +336,16 @@ Symbol: GPIOBASEA At line 24 in file REG_UTILES.inc Uses At line 54 in file FonctionEtape2.asm -Comment: GPIOBASEA used once + At line 64 in file FonctionEtape2.asm + GPIOBASEB 40010C00 Symbol: GPIOBASEB Definitions At line 25 in file REG_UTILES.inc Uses - At line 64 in file FonctionEtape2.asm -Comment: GPIOBASEB used once + None +Comment: GPIOBASEB unused MaskBlank 00000004 Symbol: MaskBlank @@ -379,9 +376,8 @@ Symbol: MaskSclk Definitions At line 38 in file REG_UTILES.inc Uses - At line 55 in file FonctionEtape2.asm - At line 65 in file FonctionEtape2.asm - + None +Comment: MaskSclk unused MaskSerial_Dots 00000080 Symbol: MaskSerial_Dots @@ -434,8 +430,11 @@ Symbol: OffsetOutput Definitions At line 28 in file REG_UTILES.inc Uses - None -Comment: OffsetOutput unused + At line 55 in file FonctionEtape2.asm + At line 57 in file FonctionEtape2.asm + At line 65 in file FonctionEtape2.asm + At line 67 in file FonctionEtape2.asm + OffsetReset 00000014 Symbol: OffsetReset @@ -454,15 +453,15 @@ Symbol: OffsetSet Comment: OffsetSet unused SCB_VTOR E000ED08 -Symbol: SCB_VTOR - Definitions - At line 43 in file REG_UTILES.inc ARM Macro Assembler Page 3 Alphabetic symbol ordering Absolute symbols +Symbol: SCB_VTOR + Definitions + At line 43 in file REG_UTILES.inc Uses None Comment: SCB_VTOR unused diff --git a/Listings/principale.lst b/Listings/principale.lst index 4d2efb0..ccef911 100644 --- a/Listings/principale.lst +++ b/Listings/principale.lst @@ -223,14 +223,14 @@ ARM Macro Assembler Page 4 88 0000000A ENDP 89 0000000A 90 0000000A END -Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw -ork --depend=.\objects\principale.d -o.\objects\principale.o -I.\RTE\Device\STM -32F103RB -I.\RTE\_Simul_ -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\ -Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\In -clude --predefine="__EVAL SETA 1" --predefine="__MICROLIB SETA 1" --predefine=" -__UVISION_VERSION SETA 534" --predefine="_RTE_ SETA 1" --predefine="STM32F10X_M -D SETA 1" --predefine="_RTE_ SETA 1" --predefine="STM32F10X_MD SETA 1" --list=. -\listings\principale.lst Principale.asm +Command Line: --debug --xref --diag_suppress=9931,A1950W --cpu=Cortex-M3 --depe +nd=.\objects\principale.d -o.\objects\principale.o -I.\RTE\Device\STM32F103RB - +I.\RTE\_Simul_ -IC:\Users\alzyo\AppData\Local\Arm\Packs\ARM\CMSIS\5.9.0\CMSIS\C +ore\Include -IC:\Users\alzyo\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.0\D +evice\Include --predefine="__EVAL SETA 1" --predefine="__MICROLIB SETA 1" --pre +define="__UVISION_VERSION SETA 538" --predefine="_RTE_ SETA 1" --predefine="STM +32F10X_MD SETA 1" --predefine="_RTE_ SETA 1" --predefine="STM32F10X_MD SETA 1" +--list=.\listings\principale.lst Principale.asm diff --git a/Listings/startup_stm32f10x_md.lst b/Listings/startup_stm32f10x_md.lst index 3bdf3da..b08f478 100644 --- a/Listings/startup_stm32f10x_md.lst +++ b/Listings/startup_stm32f10x_md.lst @@ -463,15 +463,15 @@ ARM Macro Assembler Page 8 305 0000001C END 00000000 00000000 -Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw -ork --depend=.\objects\startup_stm32f10x_md.d -o.\objects\startup_stm32f10x_md. -o -I.\RTE\Device\STM32F103RB -I.\RTE\_Simul_ -IC:\Programdata\Keil\Arm\Packs\AR -M\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx -_DFP\2.3.0\Device\Include --predefine="__EVAL SETA 1" --predefine="__MICROLIB S -ETA 1" --predefine="__UVISION_VERSION SETA 534" --predefine="_RTE_ SETA 1" --pr -edefine="STM32F10X_MD SETA 1" --predefine="_RTE_ SETA 1" --predefine="STM32F10X -_MD SETA 1" --list=.\listings\startup_stm32f10x_md.lst RTE\Device\STM32F103RB\s -tartup_stm32f10x_md.s +Command Line: --debug --xref --diag_suppress=9931,A1950W --cpu=Cortex-M3 --depe +nd=.\objects\startup_stm32f10x_md.d -o.\objects\startup_stm32f10x_md.o -I.\RTE\ +Device\STM32F103RB -I.\RTE\_Simul_ -IC:\Users\alzyo\AppData\Local\Arm\Packs\ARM +\CMSIS\5.9.0\CMSIS\Core\Include -IC:\Users\alzyo\AppData\Local\Arm\Packs\Keil\S +TM32F1xx_DFP\2.4.0\Device\Include --predefine="__EVAL SETA 1" --predefine="__MI +CROLIB SETA 1" --predefine="__UVISION_VERSION SETA 538" --predefine="_RTE_ SETA + 1" --predefine="STM32F10X_MD SETA 1" --predefine="_RTE_ SETA 1" --predefine="S +TM32F10X_MD SETA 1" --list=.\listings\startup_stm32f10x_md.lst RTE/Device/STM32 +F103RB/startup_stm32f10x_md.s @@ -482,7 +482,7 @@ STACK 00000000 Symbol: STACK Definitions - At line 35 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 35 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses None Comment: STACK unused @@ -490,7 +490,7 @@ Stack_Mem 00000000 Symbol: Stack_Mem Definitions - At line 36 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 36 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses None Comment: Stack_Mem unused @@ -498,10 +498,10 @@ __initial_sp 00000400 Symbol: __initial_sp Definitions - At line 37 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 37 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 61 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 284 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 61 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 284 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s 3 symbols @@ -514,7 +514,7 @@ HEAP 00000000 Symbol: HEAP Definitions - At line 46 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 46 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses None Comment: HEAP unused @@ -522,7 +522,7 @@ Heap_Mem 00000000 Symbol: Heap_Mem Definitions - At line 48 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 48 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses None Comment: Heap_Mem unused @@ -530,17 +530,17 @@ __heap_base 00000000 Symbol: __heap_base Definitions - At line 47 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 47 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 285 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 285 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Comment: __heap_base used once __heap_limit 00000200 Symbol: __heap_limit Definitions - At line 49 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 49 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 286 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 286 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Comment: __heap_limit used once 4 symbols @@ -553,7 +553,7 @@ RESET 00000000 Symbol: RESET Definitions - At line 56 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 56 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses None Comment: RESET unused @@ -561,19 +561,19 @@ __Vectors 00000000 Symbol: __Vectors Definitions - At line 61 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 61 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 57 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 57 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 124 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s __Vectors_End 000000EC Symbol: __Vectors_End Definitions - At line 122 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 122 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 58 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 58 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 124 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s 3 symbols @@ -586,7 +586,7 @@ Relocatable symbols Symbol: .text Definitions - At line 126 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 126 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses None Comment: .text unused @@ -594,52 +594,52 @@ ADC1_2_IRQHandler 0000001A Symbol: ADC1_2_IRQHandler Definitions - At line 247 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 247 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 97 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 203 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 97 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 203 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s BusFault_Handler 0000000E Symbol: BusFault_Handler Definitions - At line 156 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 156 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 66 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 157 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 66 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 157 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s CAN1_RX1_IRQHandler 0000001A Symbol: CAN1_RX1_IRQHandler Definitions - At line 250 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 250 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 100 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 206 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 100 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 206 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s CAN1_SCE_IRQHandler 0000001A Symbol: CAN1_SCE_IRQHandler Definitions - At line 251 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 251 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 101 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 207 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 101 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 207 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s DMA1_Channel1_IRQHandler 0000001A Symbol: DMA1_Channel1_IRQHandler Definitions - At line 240 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 240 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 90 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 196 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 90 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 196 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s DMA1_Channel2_IRQHandler 0000001A Symbol: DMA1_Channel2_IRQHandler Definitions - At line 241 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 241 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses @@ -647,62 +647,62 @@ Symbol: DMA1_Channel2_IRQHandler ARM Macro Assembler Page 2 Alphabetic symbol ordering Relocatable symbols - At line 91 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 197 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 91 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 197 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s DMA1_Channel3_IRQHandler 0000001A Symbol: DMA1_Channel3_IRQHandler Definitions - At line 242 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 242 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 92 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 198 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 92 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 198 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s DMA1_Channel4_IRQHandler 0000001A Symbol: DMA1_Channel4_IRQHandler Definitions - At line 243 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 243 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 93 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 199 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 93 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 199 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s DMA1_Channel5_IRQHandler 0000001A Symbol: DMA1_Channel5_IRQHandler Definitions - At line 244 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 244 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 94 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 200 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 94 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 200 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s DMA1_Channel6_IRQHandler 0000001A Symbol: DMA1_Channel6_IRQHandler Definitions - At line 245 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 245 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 95 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 201 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 95 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 201 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s DMA1_Channel7_IRQHandler 0000001A Symbol: DMA1_Channel7_IRQHandler Definitions - At line 246 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 246 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 96 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 202 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 96 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 202 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s DebugMon_Handler 00000014 Symbol: DebugMon_Handler Definitions - At line 170 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 170 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 73 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 171 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 73 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 171 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Default_Handler 0000001A @@ -714,7 +714,7 @@ Relocatable symbols Symbol: Default_Handler Definitions - At line 183 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 183 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses None Comment: Default_Handler unused @@ -722,55 +722,55 @@ EXTI0_IRQHandler 0000001A Symbol: EXTI0_IRQHandler Definitions - At line 235 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 235 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 85 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 191 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 85 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 191 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s EXTI15_10_IRQHandler 0000001A Symbol: EXTI15_10_IRQHandler Definitions - At line 269 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 269 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 119 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 225 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 119 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 225 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s EXTI1_IRQHandler 0000001A Symbol: EXTI1_IRQHandler Definitions - At line 236 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 236 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 86 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 192 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 86 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 192 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s EXTI2_IRQHandler 0000001A Symbol: EXTI2_IRQHandler Definitions - At line 237 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 237 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 87 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 193 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 87 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 193 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s EXTI3_IRQHandler 0000001A Symbol: EXTI3_IRQHandler Definitions - At line 238 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 238 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 88 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 194 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 88 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 194 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s EXTI4_IRQHandler 0000001A Symbol: EXTI4_IRQHandler Definitions - At line 239 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 239 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 89 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 195 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 89 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 195 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s @@ -782,55 +782,55 @@ EXTI9_5_IRQHandler 0000001A Symbol: EXTI9_5_IRQHandler Definitions - At line 252 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 252 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 102 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 208 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 102 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 208 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s FLASH_IRQHandler 0000001A Symbol: FLASH_IRQHandler Definitions - At line 233 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 233 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 83 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 189 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 83 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 189 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s HardFault_Handler 0000000A Symbol: HardFault_Handler Definitions - At line 146 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 146 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 64 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 147 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 64 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 147 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s I2C1_ER_IRQHandler 0000001A Symbol: I2C1_ER_IRQHandler Definitions - At line 261 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 261 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 111 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 217 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 111 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 217 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s I2C1_EV_IRQHandler 0000001A Symbol: I2C1_EV_IRQHandler Definitions - At line 260 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 260 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 110 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 216 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 110 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 216 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s I2C2_ER_IRQHandler 0000001A Symbol: I2C2_ER_IRQHandler Definitions - At line 263 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 263 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 113 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 219 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 113 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 219 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s I2C2_EV_IRQHandler 0000001A @@ -842,64 +842,64 @@ Symbol: I2C2_EV_IRQHandler ARM Macro Assembler Page 5 Alphabetic symbol ordering Relocatable symbols - At line 262 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 262 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 112 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 218 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 112 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 218 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s MemManage_Handler 0000000C Symbol: MemManage_Handler Definitions - At line 151 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 151 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 65 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 152 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 65 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 152 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s NMI_Handler 00000008 Symbol: NMI_Handler Definitions - At line 141 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 141 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 63 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 142 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 63 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 142 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s PVD_IRQHandler 0000001A Symbol: PVD_IRQHandler Definitions - At line 230 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 230 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 80 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 186 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 80 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 186 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s PendSV_Handler 00000016 Symbol: PendSV_Handler Definitions - At line 174 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 174 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 75 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 175 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 75 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 175 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s RCC_IRQHandler 0000001A Symbol: RCC_IRQHandler Definitions - At line 234 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 234 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 84 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 190 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 84 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 190 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s RTCAlarm_IRQHandler 0000001A Symbol: RTCAlarm_IRQHandler Definitions - At line 270 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 270 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 120 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 226 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 120 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 226 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s @@ -911,61 +911,61 @@ RTC_IRQHandler 0000001A Symbol: RTC_IRQHandler Definitions - At line 232 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 232 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 82 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 188 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 82 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 188 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Reset_Handler 00000000 Symbol: Reset_Handler Definitions - At line 129 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 129 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 62 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 130 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 62 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 130 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s SPI1_IRQHandler 0000001A Symbol: SPI1_IRQHandler Definitions - At line 264 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 264 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 114 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 220 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 114 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 220 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s SPI2_IRQHandler 0000001A Symbol: SPI2_IRQHandler Definitions - At line 265 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 265 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 115 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 221 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 115 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 221 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s SVC_Handler 00000012 Symbol: SVC_Handler Definitions - At line 165 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 165 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 72 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 166 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 72 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 166 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s SysTick_Handler 00000018 Symbol: SysTick_Handler Definitions - At line 178 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 178 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 76 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 179 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 76 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 179 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s TAMPER_IRQHandler 0000001A Symbol: TAMPER_IRQHandler Definitions - At line 231 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 231 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s @@ -973,62 +973,62 @@ ARM Macro Assembler Page 7 Alphabetic symbol ordering Relocatable symbols Uses - At line 81 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 187 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 81 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 187 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s TIM1_BRK_IRQHandler 0000001A Symbol: TIM1_BRK_IRQHandler Definitions - At line 253 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 253 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 103 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 209 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 103 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 209 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s TIM1_CC_IRQHandler 0000001A Symbol: TIM1_CC_IRQHandler Definitions - At line 256 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 256 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 106 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 212 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 106 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 212 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s TIM1_TRG_COM_IRQHandler 0000001A Symbol: TIM1_TRG_COM_IRQHandler Definitions - At line 255 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 255 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 105 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 211 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 105 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 211 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s TIM1_UP_IRQHandler 0000001A Symbol: TIM1_UP_IRQHandler Definitions - At line 254 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 254 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 104 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 210 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 104 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 210 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s TIM2_IRQHandler 0000001A Symbol: TIM2_IRQHandler Definitions - At line 257 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 257 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 107 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 213 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 107 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 213 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s TIM3_IRQHandler 0000001A Symbol: TIM3_IRQHandler Definitions - At line 258 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 258 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 108 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 214 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 108 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 214 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s TIM4_IRQHandler 0000001A @@ -1040,61 +1040,61 @@ Relocatable symbols Symbol: TIM4_IRQHandler Definitions - At line 259 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 259 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 109 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 215 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 109 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 215 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s USART1_IRQHandler 0000001A Symbol: USART1_IRQHandler Definitions - At line 266 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 266 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 116 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 222 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 116 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 222 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s USART2_IRQHandler 0000001A Symbol: USART2_IRQHandler Definitions - At line 267 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 267 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 117 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 223 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 117 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 223 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s USART3_IRQHandler 0000001A Symbol: USART3_IRQHandler Definitions - At line 268 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 268 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 118 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 224 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 118 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 224 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s USBWakeUp_IRQHandler 0000001A Symbol: USBWakeUp_IRQHandler Definitions - At line 271 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 271 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 121 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 227 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 121 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 227 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s USB_HP_CAN1_TX_IRQHandler 0000001A Symbol: USB_HP_CAN1_TX_IRQHandler Definitions - At line 248 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 248 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 98 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 204 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 98 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 204 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s USB_LP_CAN1_RX0_IRQHandler 0000001A Symbol: USB_LP_CAN1_RX0_IRQHandler Definitions - At line 249 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 249 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses @@ -1102,26 +1102,26 @@ Symbol: USB_LP_CAN1_RX0_IRQHandler ARM Macro Assembler Page 9 Alphabetic symbol ordering Relocatable symbols - At line 99 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 205 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 99 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 205 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s UsageFault_Handler 00000010 Symbol: UsageFault_Handler Definitions - At line 161 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 161 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 67 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 162 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 67 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 162 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s WWDG_IRQHandler 0000001A Symbol: WWDG_IRQHandler Definitions - At line 229 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 229 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 79 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s - At line 185 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 79 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s + At line 185 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s 55 symbols @@ -1134,25 +1134,25 @@ Heap_Size 00000200 Symbol: Heap_Size Definitions - At line 44 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 44 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 48 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 48 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Comment: Heap_Size used once Stack_Size 00000400 Symbol: Stack_Size Definitions - At line 33 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 33 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 36 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 36 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Comment: Stack_Size used once __Vectors_Size 000000EC Symbol: __Vectors_Size Definitions - At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 124 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 59 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 59 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Comment: __Vectors_Size used once 3 symbols @@ -1165,17 +1165,17 @@ SystemInit 00000000 Symbol: SystemInit Definitions - At line 132 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 132 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 133 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 133 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Comment: SystemInit used once __main 00000000 Symbol: __main Definitions - At line 131 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 131 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Uses - At line 135 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 135 in file RTE/Device/STM32F103RB/startup_stm32f10x_md.s Comment: __main used once 2 symbols 407 symbols in table diff --git a/Objects/Etape_2_Simulé.dep b/Objects/Etape_2_Simulé.dep index 7083c57..22341a5 100644 --- a/Objects/Etape_2_Simulé.dep +++ b/Objects/Etape_2_Simulé.dep @@ -1,23 +1,23 @@ Dependencies for Project 'Etape_2', Target 'Simulé': (DO NOT MODIFY !) -CompilerVersion: 5060960::V5.06 update 7 (build 960)::.\ARMCC -F (.\Principale.asm)(0x6412F558)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1" -I.\RTE\Device\STM32F103RB -I.\RTE\_Simul_ -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include --pd "__UVISION_VERSION SETA 534" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --list .\listings\principale.lst --xref -o .\objects\principale.o --depend .\objects\principale.d) -I (REG_UTILES.inc)(0x6412D4E6) -F (.\FonctionEtape.asm)(0x6412F33B)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1" -I.\RTE\Device\STM32F103RB -I.\RTE\_Simul_ -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include --pd "__UVISION_VERSION SETA 534" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --list .\listings\fonctionetape.lst --xref -o .\objects\fonctionetape.o --depend .\objects\fonctionetape.d) -I (REG_UTILES.inc)(0x6412D4E6) -F (.\FonctionEtape2.asm)(0x6412F95B)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1" -I.\RTE\Device\STM32F103RB -I.\RTE\_Simul_ -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include --pd "__UVISION_VERSION SETA 534" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --list .\listings\fonctionetape2.lst --xref -o .\objects\fonctionetape2.o --depend .\objects\fonctionetape2.d) -I (REG_UTILES.inc)(0x6412D4E6) -F (.\Matos.lib)(0x6412D4E6)() -F (RTE\Device\STM32F103RB\RTE_Device.h)(0x6412D4E6)() -F (RTE\Device\STM32F103RB\startup_stm32f10x_md.s)(0x6412D4E6)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1" -I.\RTE\Device\STM32F103RB -I.\RTE\_Simul_ -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include --pd "__UVISION_VERSION SETA 534" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --list .\listings\startup_stm32f10x_md.lst --xref -o .\objects\startup_stm32f10x_md.o --depend .\objects\startup_stm32f10x_md.d) -F (RTE\Device\STM32F103RB\system_stm32f10x.c)(0x6412D4E6)(--c99 -c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\pilotes\Include -I.\RTE\Device\STM32F103RB -I.\RTE\_Simul_ -IC:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -DSTM32F10X_MD -o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d) -I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\stm32f10x.h)(0x58258CCC) -I (.\RTE\_Simul_\RTE_Components.h)(0x6412EA84) -I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F2582) -I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8E9122) -I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F2582) -I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E835B22) -I (C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F2582) -I (C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h)(0x58258CCC) -F (RTE\Device\STM32F107VC\RTE_Device.h)(0x6412D4E6)() -F (RTE\Device\STM32F107VC\startup_stm32f10x_cl.s)(0x6412D4E6)() -F (RTE\Device\STM32F107VC\system_stm32f10x.c)(0x6412D4E6)() +CompilerVersion: 6190000::V6.19::ARMCLANG +F (.\Principale.asm)(0x641F19F4)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --pd "__MICROLIB SETA 1" --diag_suppress=A1950W -I.\RTE\Device\STM32F103RB -I.\RTE\_Simul_ -IC:\Users\alzyo\AppData\Local\Arm\Packs\ARM\CMSIS\5.9.0\CMSIS\Core\Include -IC:\Users\alzyo\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.0\Device\Include --pd "__UVISION_VERSION SETA 538" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --list .\listings\principale.lst --xref -o .\objects\principale.o --depend .\objects\principale.d) +I (REG_UTILES.inc)(0x641EB32F) +F (.\FonctionEtape.asm)(0x641F19F4)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --pd "__MICROLIB SETA 1" --diag_suppress=A1950W -I.\RTE\Device\STM32F103RB -I.\RTE\_Simul_ -IC:\Users\alzyo\AppData\Local\Arm\Packs\ARM\CMSIS\5.9.0\CMSIS\Core\Include -IC:\Users\alzyo\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.0\Device\Include --pd "__UVISION_VERSION SETA 538" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --list .\listings\fonctionetape.lst --xref -o .\objects\fonctionetape.o --depend .\objects\fonctionetape.d) +I (REG_UTILES.inc)(0x641EB32F) +F (.\FonctionEtape2.asm)(0x641F71D7)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --pd "__MICROLIB SETA 1" --diag_suppress=A1950W -I.\RTE\Device\STM32F103RB -I.\RTE\_Simul_ -IC:\Users\alzyo\AppData\Local\Arm\Packs\ARM\CMSIS\5.9.0\CMSIS\Core\Include -IC:\Users\alzyo\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.0\Device\Include --pd "__UVISION_VERSION SETA 538" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --list .\listings\fonctionetape2.lst --xref -o .\objects\fonctionetape2.o --depend .\objects\fonctionetape2.d) +I (REG_UTILES.inc)(0x641EB32F) +F (.\Matos.lib)(0x641EB32F)() +F (RTE/Device/STM32F103RB/RTE_Device.h)(0x641EB32F)() +F (RTE/Device/STM32F103RB/startup_stm32f10x_md.s)(0x641EB32F)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --pd "__MICROLIB SETA 1" --diag_suppress=A1950W -I.\RTE\Device\STM32F103RB -I.\RTE\_Simul_ -IC:\Users\alzyo\AppData\Local\Arm\Packs\ARM\CMSIS\5.9.0\CMSIS\Core\Include -IC:\Users\alzyo\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.0\Device\Include --pd "__UVISION_VERSION SETA 538" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --list .\listings\startup_stm32f10x_md.lst --xref -o .\objects\startup_stm32f10x_md.o --depend .\objects\startup_stm32f10x_md.d) +F (RTE/Device/STM32F103RB/system_stm32f10x.c)(0x641EB32F)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m3 -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -D__EVAL -D__MICROLIB -gdwarf-4 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../pilotes/Include -I./RTE/Device/STM32F103RB -I./RTE/_Simul_ -IC:/Users/alzyo/AppData/Local/Arm/Packs/ARM/CMSIS/5.9.0/CMSIS/Core/Include -IC:/Users/alzyo/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.0/Device/Include -D__UVISION_VERSION="538" -D_RTE_ -DSTM32F10X_MD -D_RTE_ -DSTM32F10X_MD -o ./objects/system_stm32f10x.o -MD) +I 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µVision Build Log

 
Tool Versions:

-IDE-Version: µVision V5.34.0.0
-Copyright (C) 2021 ARM Ltd and ARM Germany GmbH. All rights reserved.
-License Information: CSN CSN, INSA de Toulouse, LIC=----
+IDE-Version: µVision V5.38.0.0
+Copyright (C) 2022 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: Yohan Boujon, INSA, LIC=----
  
 Tool Versions:
-Toolchain:       MDK-Lite  Version: 5.34.0.0
-Toolchain Path:  C:\Keil_v5\ARM\ARMCC\Bin
-C Compiler:      Armcc.exe V5.06 update 7 (build 960)
-Assembler:       Armasm.exe V5.06 update 7 (build 960)
-Linker/Locator:  ArmLink.exe V5.06 update 7 (build 960)
-Library Manager: ArmAr.exe V5.06 update 7 (build 960)
-Hex Converter:   FromElf.exe V5.06 update 7 (build 960)
-CPU DLL:         SARMCM3.DLL V5.34.0.0
-Dialog DLL:      DARMSTM.DLL V1.68.0.0
-Target DLL:      UL2CM3.DLL V1.163.9.0
-Dialog DLL:      TCM.DLL V1.48.0.0
+Toolchain:       MDK-Lite  Version: 5.38.0.0
+Toolchain Path:  C:\Keil_v5\ARM\ARMCLANG\Bin
+C Compiler:      ArmClang.exe V6.19
+Assembler:       Armasm.exe V6.19
+Linker/Locator:  ArmLink.exe V6.19
+Library Manager: ArmAr.exe V6.19
+Hex Converter:   FromElf.exe V6.19
+CPU DLL:         SARMCM3.DLL V5.38.0.0
+Dialog DLL:      DARMSTM.DLL V1.69.1.0
+Target DLL:      UL2CM3.DLL V1.164.8.0
+Dialog DLL:      TCM.DLL V1.56.4.0
  
 
Project:

-U:\Windows\Bureau\roue_assembler\Etape_2.uvprojx
-Project File Date:  03/16/2023
+C:\Users\alzyo\Desktop\roue_assembler\Etape_2.uvprojx
+Project File Date:  03/25/2023
 
 
Output:

-*** Using Compiler 'V5.06 update 7 (build 960)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
+*** Using Compiler 'V6.19', folder: 'C:\Keil_v5\ARM\ARMCLANG\Bin'
 Rebuild target 'Simulé'
 assembling Principale.asm...
 assembling FonctionEtape.asm...
 FonctionEtape.asm(119): warning: A1581W: Added 2 bytes of padding at address 0x56
 assembling FonctionEtape2.asm...
-FonctionEtape2.asm(93): warning: A1581W: Added 2 bytes of padding at address 0x46
+FonctionEtape2.asm(93): warning: A1581W: Added 2 bytes of padding at address 0x36
 assembling startup_stm32f10x_md.s...
 compiling system_stm32f10x.c...
 linking...
-Program Size: Code=4800 RO-data=268 RW-data=168 ZI-data=1024  
+Program Size: Code=4720 RO-data=268 RW-data=168 ZI-data=1024  
 ".\Objects\Simu_Etape0.axf" - 0 Error(s), 2 Warning(s).
 
 
Software Packages used:

 
 Package Vendor: ARM
-                http://www.keil.com/pack/ARM.CMSIS.5.7.0.pack
-                ARM.CMSIS.5.7.0
-                CMSIS (Cortex Microcontroller Software Interface Standard)
-   * Component: CORE Version: 5.4.0
+                http://www.keil.com/pack/ARM.CMSIS.5.9.0.pack
+                ARM.CMSIS.5.9.0
+                CMSIS (Common Microcontroller Software Interface Standard)
+   * Component: CORE Version: 5.6.0
 
 Package Vendor: Keil
-                http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.3.0.pack
-                Keil.STM32F1xx_DFP.2.3.0
+                http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.4.0.pack
+                Keil.STM32F1xx_DFP.2.4.0
                 STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
    * Component: Startup Version: 1.0.0
 
 
Collection of Component include folders:

-  .\RTE\Device\STM32F103RB
-  .\RTE\_Simul_
-  C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-  C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
+  ./RTE/Device/STM32F103RB
+  ./RTE/_Simul_
+  C:/Users/alzyo/AppData/Local/Arm/Packs/ARM/CMSIS/5.9.0/CMSIS/Core/Include
+  C:/Users/alzyo/AppData/Local/Arm/Packs/Keil/STM32F1xx_DFP/2.4.0/Device/Include
 
 
Collection of Component Files used:

 
-   * Component: ARM::CMSIS:CORE:5.4.0
+   * Component: ARM::CMSIS:CORE:5.6.0
 
    * Component: Keil::Device:Startup:1.0.0
-      Source file:   Device\Source\system_stm32f10x.c
-      Include file:  RTE_Driver\Config\RTE_Device.h
-      Source file:   Device\Source\ARM\STM32F1xx_OPT.s
-      Source file:   Device\Source\ARM\startup_stm32f10x_md.s
-Build Time Elapsed:  00:00:02
+      Source file:   Device/Source/ARM/startup_stm32f10x_md.s
+      Source file:   Device/Source/system_stm32f10x.c
+      Include file:  RTE_Driver/Config/RTE_Device.h
+      Source file:   Device/Source/ARM/STM32F1xx_OPT.s
+Build Time Elapsed:  00:00:01
diff --git a/Objects/Simu_Etape0.htm b/Objects/Simu_Etape0.htm index 7947965..2a311cd 100644 --- a/Objects/Simu_Etape0.htm +++ b/Objects/Simu_Etape0.htm @@ -3,7 +3,7 @@ Static Call Graph - [.\Objects\Simu_Etape0.axf]

Static Call Graph for image .\Objects\Simu_Etape0.axf

-

#<CALLGRAPH># ARM Linker, 5060960: Last Updated: Thu Mar 16 12:11:26 2023 +

#<CALLGRAPH># ARM Linker, 6190004: Last Updated: Sat Mar 25 23:12:52 2023

Maximum Stack Usage = 168 bytes + Unknown(Cycles, Untraceable Function Pointers)

Call chain for Maximum Stack Depth:

@@ -63,7 +63,7 @@ Function Pointers
  • SPI2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
  • SVC_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
  • SysTick_Handler from timer_systick_1.o(i.SysTick_Handler) referenced from startup_stm32f10x_md.o(RESET) -
  • SystemInit from system_stm32f10x.o(i.SystemInit) referenced from startup_stm32f10x_md.o(.text) +
  • SystemInit from system_stm32f10x.o(.text.SystemInit) referenced from startup_stm32f10x_md.o(.text)
  • TAMPER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
  • TIM1_BRK_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
  • TIM1_CC_IRQHandler from fonctiontimer.o(i.TIM1_CC_IRQHandler) referenced from startup_stm32f10x_md.o(RESET) @@ -90,7 +90,7 @@ Global Symbols

    __main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
    [Address Reference Count : 1]

    • startup_stm32f10x_md.o(.text)
    -

    _main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001)) +

    _main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))

    _main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))

    [Calls]

    • >>   __scatterload @@ -100,17 +100,15 @@ Global Symbols

      [Called By]
      • >>   __scatterload
      -

      _main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008)) +

      _main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008)) -

      _main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A)) +

      _main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A)) -

      _main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B)) +

      _main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B)) -

      __rt_lib_shutdown_fini (Thumb, 0 bytes, Stack size unknown bytes, entry12b.o(.ARM.Collect$$$$0000000E)) +

      __rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000D)) -

      __rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000F)) - -

      __rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$00000011)) +

      __rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$0000000F))

      Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
      [Address Reference Count : 1]

      • startup_stm32f10x_md.o(RESET) @@ -347,7 +345,7 @@ Global Symbols
      • >>   Init_Timer1
      -

      __aeabi_cdcmpeq (Thumb, 0 bytes, Stack size 0 bytes, cdcmple.o(.text), UNUSED) +

      __aeabi_cdcmpeq (Thumb, 0 bytes, Stack size 0 bytes, cdcmple.o(.text), UNUSED)

      __aeabi_cdcmple (Thumb, 48 bytes, Stack size 0 bytes, cdcmple.o(.text))

      [Called By]

      • >>   Init_Timer1 @@ -366,7 +364,7 @@ Global Symbols
      • >>   Init_Timer1
      -

      __I$use$fp (Thumb, 0 bytes, Stack size 0 bytes, iusefp.o(.text), UNUSED) +

      __I$use$fp (Thumb, 0 bytes, Stack size 0 bytes, iusefp.o(.text), UNUSED)

      _float_round (Thumb, 18 bytes, Stack size 0 bytes, fepilogue.o(.text))

      [Called By]

      • >>   __aeabi_fdiv @@ -401,20 +399,25 @@ Global Symbols
        [Called By]
        • >>   _main_scatterload
        -

        __scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED) +

        __scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)

        __aeabi_llsl (Thumb, 30 bytes, Stack size 0 bytes, llshl.o(.text))

        [Called By]

        • >>   _double_epilogue
        -

        _ll_shift_l (Thumb, 0 bytes, Stack size 0 bytes, llshl.o(.text), UNUSED) +

        _ll_shift_l (Thumb, 0 bytes, Stack size 0 bytes, llshl.o(.text), UNUSED)

        __aeabi_llsr (Thumb, 32 bytes, Stack size 0 bytes, llushr.o(.text))

        [Called By]

        • >>   _double_epilogue
        -

        _ll_ushift_r (Thumb, 0 bytes, Stack size 0 bytes, llushr.o(.text), UNUSED) +

        _ll_ushift_r (Thumb, 0 bytes, Stack size 0 bytes, llushr.o(.text), UNUSED) +

        SystemInit (Thumb, 272 bytes, Stack size 8 bytes, system_stm32f10x.o(.text.SystemInit)) +

        [Stack]

        • Max Depth = 8
        • Call Chain = SystemInit +
        +
        [Address Reference Count : 1]
        • startup_stm32f10x_md.o(.text) +

        Anim (Thumb, 32 bytes, Stack size 0 bytes, fonctiontimer.o(i.Anim))
        [Address Reference Count : 1]

        • initialisation.o(i.Init_Cible)
        @@ -515,13 +518,6 @@ Global Symbols

      [Address Reference Count : 1]
      • startup_stm32f10x_md.o(RESET)
      -

      SystemInit (Thumb, 78 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SystemInit)) -

      [Stack]

      • Max Depth = 28
      • Call Chain = SystemInit ⇒ SetSysClock ⇒ SetSysClockTo72 -
      -
      [Calls]
      • >>   SetSysClock -
      -
      [Address Reference Count : 1]
      • startup_stm32f10x_md.o(.text) -

      Systick_Period (Thumb, 256 bytes, Stack size 48 bytes, timer_systick_1.o(i.Systick_Period))

      [Stack]

      • Max Depth = 136
      • Call Chain = Systick_Period ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ _double_round
      @@ -570,34 +566,34 @@ Global Symbols

    [Address Reference Count : 1]
    • startup_stm32f10x_md.o(RESET)
    -

    __scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED) +

    __scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED) -

    __scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED) +

    __scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED) -

    __scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED) +

    __scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)

    main (Thumb, 10 bytes, Stack size 0 bytes, principale.o(moncode))

    [Stack]

    • Max Depth = 168
    • Call Chain = main ⇒ Init_Cible ⇒ Init_Timer1 ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ _double_round

    [Calls]
    • >>   Init_Cible -
    • >>   DriverGlobal +
    • >>   DriverGlobal

    [Address Reference Count : 1]
    • entry9a.o(.ARM.Collect$$$$0000000B)
    -

    Eteint_LED (Thumb, 22 bytes, Stack size 0 bytes, fonctionetape.o(moncode), UNUSED) +

    Eteint_LED (Thumb, 22 bytes, Stack size 0 bytes, fonctionetape.o(moncode), UNUSED) -

    Allume_LED (Thumb, 22 bytes, Stack size 0 bytes, fonctionetape.o(moncode), UNUSED) +

    Allume_LED (Thumb, 22 bytes, Stack size 0 bytes, fonctionetape.o(moncode), UNUSED) -

    Inverse_LED (Thumb, 42 bytes, Stack size 0 bytes, fonctionetape.o(moncode), UNUSED) +

    Inverse_LED (Thumb, 42 bytes, Stack size 0 bytes, fonctionetape.o(moncode), UNUSED) -

    Set_SCLK (Thumb, 22 bytes, Stack size 0 bytes, fonctionetape2.o(moncode)) -

    [Called By]

    • >>   DriverGlobal +

      Set_SCLK (Thumb, 14 bytes, Stack size 0 bytes, fonctionetape2.o(moncode)) +

      [Called By]

      • >>   DriverGlobal
      -

      Reset_SCLK (Thumb, 22 bytes, Stack size 0 bytes, fonctionetape2.o(moncode), UNUSED) +

      Reset_SCLK (Thumb, 14 bytes, Stack size 0 bytes, fonctionetape2.o(moncode), UNUSED) -

      DriverGlobal (Thumb, 26 bytes, Stack size 0 bytes, fonctionetape2.o(moncode)) -

      [Calls]

      • >>   Set_SCLK +

        DriverGlobal (Thumb, 26 bytes, Stack size 0 bytes, fonctionetape2.o(moncode)) +

        [Calls]

        • >>   Set_SCLK

        [Called By]
        • >>   main
        @@ -614,21 +610,7 @@ Global Symbols

        Local Symbols -

        -

        SetSysClock (Thumb, 8 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SetSysClock)) -

        [Stack]

        • Max Depth = 20
        • Call Chain = SetSysClock ⇒ SetSysClockTo72 -
        -
        [Calls]
        • >>   SetSysClockTo72 -
        -
        [Called By]
        • >>   SystemInit -
        - -

        SetSysClockTo72 (Thumb, 214 bytes, Stack size 12 bytes, system_stm32f10x.o(i.SetSysClockTo72)) -

        [Stack]

        • Max Depth = 12
        • Call Chain = SetSysClockTo72 -
        -
        [Called By]
        • >>   SetSysClock -
        -

        +

        Undefined Global Symbols

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C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h -.\objects\system_stm32f10x.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h -.\objects\system_stm32f10x.o: C:\Programdata\Keil\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h -.\objects\system_stm32f10x.o: C:\Programdata\Keil\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include\system_stm32f10x.h +./objects/system_stm32f10x.o: RTE\Device\STM32F103RB\system_stm32f10x.c \ + C:\Users\alzyo\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.0\Device\Include\stm32f10x.h \ + RTE\_Simul_\RTE_Components.h \ + C:\Users\alzyo\AppData\Local\Arm\Packs\ARM\CMSIS\5.9.0\CMSIS\Core\Include\core_cm3.h \ + C:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + C:\Users\alzyo\AppData\Local\Arm\Packs\ARM\CMSIS\5.9.0\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\alzyo\AppData\Local\Arm\Packs\ARM\CMSIS\5.9.0\CMSIS\Core\Include\cmsis_compiler.h \ + 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z@G9h*%+D~e(?yVnC7n}7{u%&{K|V-NNSYWO6N>^^!y+`yR-YwzFPp}`d>jxL9+$HY zQD-r>z#{#ukizLjlI&6YBwqQvqZCml{|U&13bW@S@0Yf!V`^10t|`0%wgtgB{LB!Npb`K9JGWa7ybh zl4h}KiWtYaXf4<-c29B3!mQK4Y#7A;9+{O-p)#TA5D-%=Qvm5_O-tA_|3Ebj+?ZD= zWs(F!x|B+xo$Li0!8!(Wj`c+Q?{y4QNe@WymREE1qbe3yg1;vX3FlR!!$NFF6b&y$ zPj*Jum@>}p6c@SLrH!U)&q_p8na!;+2OHz+8YRjpek=j)u>PXpNkNz6Y&zjboPxfi zSelrY7&#H<6AO2mOl34x;9{SVt{k4yTw$4~n2JN>0bv=Ruw?H|F2lI(MHcO3iSt;2 zj}%2(S&<4VpeH3UEgE7ulCbMN7BdT{r&dBVMPcK&&~ZvZ$yl(Ig2+x=!}3B(H~`qUt)3prP!$9OGsTS%xyy#t1;ohfgAg4K*a$y zrt#3=1BqVGR!mO{sZ0#8xd4$lP<1$@tRHz8zqd&pkv;dQiap}PWD=`h0!#)8AawZX z2R(xM!s03V%VUOP&&{S!EUK`D=aRodh+Ry6Vbc@Bk~a3M^>9HMgpBX1_(}%~(A6Wg z1>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT(num) \ + ((num == 0) ? GPIOA : \ + (num == 1) ? GPIOB : \ + (num == 2) ? GPIOC : \ + (num == 3) ? GPIOD : \ + (num == 4) ? GPIOE : \ + (num == 5) ? GPIOF : \ + (num == 6) ? GPIOG : \ + NULL) + + +// Clock Configuration +// High-speed Internal Clock <1-999999999> +#define RTE_HSI 8000000 +// High-speed External Clock <1-999999999> +#define RTE_HSE 25000000 +// System Clock <1-999999999> +#define RTE_SYSCLK 72000000 +// HCLK Clock <1-999999999> +#define RTE_HCLK 72000000 +// APB1 Clock <1-999999999> +#define RTE_PCLK1 36000000 +// APB2 Clock <1-999999999> +#define RTE_PCLK2 72000000 +// ADC Clock <1-999999999> +#define RTE_ADCCLK 36000000 +// USB Clock +#define RTE_USBCLK 48000000 +// + + +// USART1 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + +// USART1_TX Pin <0=>Not Used <1=>PA9 +#define RTE_USART1_TX_PORT_ID_DEF 0 +#if (RTE_USART1_TX_PORT_ID_DEF == 0) +#define RTE_USART1_TX_DEF 0 +#elif (RTE_USART1_TX_PORT_ID_DEF == 1) +#define RTE_USART1_TX_DEF 1 +#define RTE_USART1_TX_PORT_DEF GPIOA +#define RTE_USART1_TX_BIT_DEF 9 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PA10 +#define RTE_USART1_RX_PORT_ID_DEF 0 +#if (RTE_USART1_RX_PORT_ID_DEF == 0) +#define RTE_USART1_RX_DEF 0 +#elif (RTE_USART1_RX_PORT_ID_DEF == 1) +#define RTE_USART1_RX_DEF 1 +#define RTE_USART1_RX_PORT_DEF GPIOA +#define RTE_USART1_RX_BIT_DEF 10 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// USART1_CK Pin <0=>Not Used <1=>PA8 +#define RTE_USART1_CK_PORT_ID_DEF 0 +#if (RTE_USART1_CK_PORT_ID_DEF == 0) +#define RTE_USART1_CK 0 +#elif (RTE_USART1_CK_PORT_ID_DEF == 1) +#define RTE_USART1_CK 1 +#define RTE_USART1_CK_PORT_DEF GPIOA +#define RTE_USART1_CK_BIT_DEF 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// USART1_CTS Pin <0=>Not Used <1=>PA11 +#define RTE_USART1_CTS_PORT_ID_DEF 0 +#if (RTE_USART1_CTS_PORT_ID_DEF == 0) +#define RTE_USART1_CTS 0 +#elif (RTE_USART1_CTS_PORT_ID_DEF == 1) +#define RTE_USART1_CTS 1 +#define RTE_USART1_CTS_PORT_DEF GPIOA +#define RTE_USART1_CTS_BIT_DEF 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif + +// USART1_RTS Pin <0=>Not Used <1=>PA12 +#define RTE_USART1_RTS_PORT_ID_DEF 0 +#if (RTE_USART1_RTS_PORT_ID_DEF == 0) +#define RTE_USART1_RTS 0 +#elif (RTE_USART1_RTS_PORT_ID_DEF == 1) +#define RTE_USART1_RTS 1 +#define RTE_USART1_RTS_PORT_DEF GPIOA +#define RTE_USART1_RTS_BIT_DEF 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// USART1 Pin Remap +// Enable USART1 Pin Remapping +#define RTE_USART1_REMAP_FULL 0 + +// USART1_TX Pin <0=>Not Used <1=>PB6 +#define RTE_USART1_TX_PORT_ID_FULL 0 +#if (RTE_USART1_TX_PORT_ID_FULL == 0) +#define RTE_USART1_TX_FULL 0 +#elif (RTE_USART1_TX_PORT_ID_FULL == 1) +#define RTE_USART1_TX_FULL 1 +#define RTE_USART1_TX_PORT_FULL GPIOB +#define RTE_USART1_TX_BIT_FULL 6 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PB7 +#define RTE_USART1_RX_PORT_ID_FULL 0 +#if (RTE_USART1_RX_PORT_ID_FULL == 0) +#define RTE_USART1_RX_FULL 0 +#elif (RTE_USART1_RX_PORT_ID_FULL == 1) +#define RTE_USART1_RX_FULL 1 +#define RTE_USART1_RX_PORT_FULL GPIOB +#define RTE_USART1_RX_BIT_FULL 7 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif +// + +#if (RTE_USART1_REMAP_FULL) +#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP +#define RTE_USART1_TX RTE_USART1_TX_FULL +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL +#define RTE_USART1_RX RTE_USART1_RX_FULL +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#else +#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP +#define RTE_USART1_TX RTE_USART1_TX_DEF +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF +#define RTE_USART1_RX RTE_USART1_RX_DEF +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_RX_DMA 0 +#define RTE_USART1_RX_DMA_NUMBER 1 +#define RTE_USART1_RX_DMA_CHANNEL 5 +#define RTE_USART1_RX_DMA_PRIORITY 0 +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_TX_DMA 0 +#define RTE_USART1_TX_DMA_NUMBER 1 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_USART2 0 + +// USART2_TX Pin <0=>Not Used <1=>PA2 +#define RTE_USART2_TX_PORT_ID_DEF 0 +#if (RTE_USART2_TX_PORT_ID_DEF == 0) +#define RTE_USART2_TX_DEF 0 +#elif (RTE_USART2_TX_PORT_ID_DEF == 1) +#define RTE_USART2_TX_DEF 1 +#define RTE_USART2_TX_PORT_DEF GPIOA +#define RTE_USART2_TX_BIT_DEF 2 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PA3 +#define RTE_USART2_RX_PORT_ID_DEF 0 +#if (RTE_USART2_RX_PORT_ID_DEF == 0) +#define RTE_USART2_RX_DEF 0 +#elif (RTE_USART2_RX_PORT_ID_DEF == 1) +#define RTE_USART2_RX_DEF 1 +#define RTE_USART2_RX_PORT_DEF GPIOA +#define RTE_USART2_RX_BIT_DEF 3 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PA4 +#define RTE_USART2_CK_PORT_ID_DEF 0 +#if (RTE_USART2_CK_PORT_ID_DEF == 0) +#define RTE_USART2_CK_DEF 0 +#elif (RTE_USART2_CK_PORT_ID_DEF == 1) +#define RTE_USART2_CK_DEF 1 +#define RTE_USART2_CK_PORT_DEF GPIOA +#define RTE_USART2_CK_BIT_DEF 4 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PA0 +#define RTE_USART2_CTS_PORT_ID_DEF 0 +#if (RTE_USART2_CTS_PORT_ID_DEF == 0) +#define RTE_USART2_CTS_DEF 0 +#elif (RTE_USART2_CTS_PORT_ID_DEF == 1) +#define RTE_USART2_CTS_DEF 1 +#define RTE_USART2_CTS_PORT_DEF GPIOA +#define RTE_USART2_CTS_BIT_DEF 0 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PA1 +#define RTE_USART2_RTS_PORT_ID_DEF 0 +#if (RTE_USART2_RTS_PORT_ID_DEF == 0) +#define RTE_USART2_RTS_DEF 0 +#elif (RTE_USART2_RTS_PORT_ID_DEF == 1) +#define RTE_USART2_RTS_DEF 1 +#define RTE_USART2_RTS_PORT_DEF GPIOA +#define RTE_USART2_RTS_BIT_DEF 1 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// USART2 Pin Remap +// Enable USART2 Pin Remapping +#define RTE_USART2_REMAP_FULL 0 + +// USART2_TX Pin <0=>Not Used <1=>PD5 +#define RTE_USART2_TX_PORT_ID_FULL 0 +#if (RTE_USART2_TX_PORT_ID_FULL == 0) +#define RTE_USART2_TX_FULL 0 +#elif (RTE_USART2_TX_PORT_ID_FULL == 1) +#define RTE_USART2_TX_FULL 1 +#define RTE_USART2_TX_PORT_FULL GPIOD +#define RTE_USART2_TX_BIT_FULL 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PD6 +#define RTE_USART2_RX_PORT_ID_FULL 0 +#if (RTE_USART2_RX_PORT_ID_FULL == 0) +#define RTE_USART2_RX_FULL 0 +#elif (RTE_USART2_RX_PORT_ID_FULL == 1) +#define RTE_USART2_RX_FULL 1 +#define RTE_USART2_RX_PORT_FULL GPIOD +#define RTE_USART2_RX_BIT_FULL 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PD7 +#define RTE_USART2_CK_PORT_ID_FULL 0 +#if (RTE_USART2_CK_PORT_ID_FULL == 0) +#define RTE_USART2_CK_FULL 0 +#elif (RTE_USART2_CK_PORT_ID_FULL == 1) +#define RTE_USART2_CK_FULL 1 +#define RTE_USART2_CK_PORT_FULL GPIOD +#define RTE_USART2_CK_BIT_FULL 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PD3 +#define RTE_USART2_CTS_PORT_ID_FULL 0 +#if (RTE_USART2_CTS_PORT_ID_FULL == 0) +#define RTE_USART2_CTS_FULL 0 +#elif (RTE_USART2_CTS_PORT_ID_FULL == 1) +#define RTE_USART2_CTS_FULL 1 +#define RTE_USART2_CTS_PORT_FULL GPIOD +#define RTE_USART2_CTS_BIT_FULL 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PD4 +#define RTE_USART2_RTS_PORT_ID_FULL 0 +#if (RTE_USART2_RTS_PORT_ID_FULL == 0) +#define RTE_USART2_RTS_FULL 0 +#elif (RTE_USART2_RTS_PORT_ID_FULL == 1) +#define RTE_USART2_RTS_FULL 1 +#define RTE_USART2_RTS_PORT_FULL GPIOD +#define RTE_USART2_RTS_BIT_FULL 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif +// + +#if (RTE_USART2_REMAP_FULL) +#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP +#define RTE_USART2_TX RTE_USART2_TX_FULL +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL +#define RTE_USART2_RX RTE_USART2_RX_FULL +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL +#define RTE_USART2_CK RTE_USART2_CK_FULL +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL +#define RTE_USART2_CTS RTE_USART2_CTS_FULL +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL +#define RTE_USART2_RTS RTE_USART2_RTS_FULL +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL +#else +#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP +#define RTE_USART2_TX RTE_USART2_TX_DEF +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF +#define RTE_USART2_RX RTE_USART2_RX_DEF +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF +#define RTE_USART2_CK RTE_USART2_CK_DEF +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF +#define RTE_USART2_CTS RTE_USART2_CTS_DEF +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF +#define RTE_USART2_RTS RTE_USART2_RTS_DEF +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_RX_DMA 0 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_CHANNEL 6 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_TX_DMA 0 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_CHANNEL 7 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>Not Used <1=>PB10 +#define RTE_USART3_TX_PORT_ID_DEF 0 +#if (RTE_USART3_TX_PORT_ID_DEF == 0) +#define RTE_USART3_TX_DEF 0 +#elif (RTE_USART3_TX_PORT_ID_DEF == 1) +#define RTE_USART3_TX_DEF 1 +#define RTE_USART3_TX_PORT_DEF GPIOB +#define RTE_USART3_TX_BIT_DEF 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PB11 +#define RTE_USART3_RX_PORT_ID_DEF 0 +#if (RTE_USART3_RX_PORT_ID_DEF == 0) +#define RTE_USART3_RX_DEF 0 +#elif (RTE_USART3_RX_PORT_ID_DEF == 1) +#define RTE_USART3_RX_DEF 1 +#define RTE_USART3_RX_PORT_DEF GPIOB +#define RTE_USART3_RX_BIT_DEF 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PB12 +#define RTE_USART3_CK_PORT_ID_DEF 0 +#if (RTE_USART3_CK_PORT_ID_DEF == 0) +#define RTE_USART3_CK_DEF 0 +#elif (RTE_USART3_CK_PORT_ID_DEF == 1) +#define RTE_USART3_CK_DEF 1 +#define RTE_USART3_CK_PORT_DEF GPIOB +#define RTE_USART3_CK_BIT_DEF 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PB13 +#define RTE_USART3_CTS_PORT_ID_DEF 0 +#if (RTE_USART3_CTS_PORT_ID_DEF == 0) +#define RTE_USART3_CTS_DEF 0 +#elif (RTE_USART3_CTS_PORT_ID_DEF == 1) +#define RTE_USART3_CTS_DEF 1 +#define RTE_USART3_CTS_PORT_DEF GPIOB +#define RTE_USART3_CTS_BIT_DEF 13 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PB14 +#define RTE_USART3_RTS_PORT_ID_DEF 0 +#if (RTE_USART3_RTS_PORT_ID_DEF == 0) +#define RTE_USART3_RTS_DEF 0 +#elif (RTE_USART3_RTS_PORT_ID_DEF == 1) +#define RTE_USART3_RTS_DEF 1 +#define RTE_USART3_RTS_PORT_DEF GPIOB +#define RTE_USART3_RTS_BIT_DEF 14 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// USART3 Partial Pin Remap +// Enable USART3 Partial Pin Remapping +#define RTE_USART3_REMAP_PARTIAL 0 + +// USART3_TX Pin <0=>Not Used <1=>PC10 +#define RTE_USART3_TX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_TX_PARTIAL 0 +#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_TX_PARTIAL 1 +#define RTE_USART3_TX_PORT_PARTIAL GPIOC +#define RTE_USART3_TX_BIT_PARTIAL 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PC11 +#define RTE_USART3_RX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_RX_PARTIAL 0 +#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_RX_PARTIAL 1 +#define RTE_USART3_RX_PORT_PARTIAL GPIOC +#define RTE_USART3_RX_BIT_PARTIAL 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PC12 +#define RTE_USART3_CK_PORT_ID_PARTIAL 0 +#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0) +#define RTE_USART3_CK_PARTIAL 0 +#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1) +#define RTE_USART3_CK_PARTIAL 1 +#define RTE_USART3_CK_PORT_PARTIAL GPIOC +#define RTE_USART3_CK_BIT_PARTIAL 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif +// + +// USART3 Full Pin Remap +// Enable USART3 Full Pin Remapping +#define RTE_USART3_REMAP_FULL 0 + +// USART3_TX Pin <0=>Not Used <1=>PD8 +#define RTE_USART3_TX_PORT_ID_FULL 0 +#if (RTE_USART3_TX_PORT_ID_FULL == 0) +#define RTE_USART3_TX_FULL 0 +#elif (RTE_USART3_TX_PORT_ID_FULL == 1) +#define RTE_USART3_TX_FULL 1 +#define RTE_USART3_TX_PORT_FULL GPIOD +#define RTE_USART3_TX_BIT_FULL 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PD9 +#define RTE_USART3_RX_PORT_ID_FULL 0 +#if (RTE_USART3_RX_PORT_ID_FULL == 0) +#define RTE_USART3_RX_FULL 0 +#elif (RTE_USART3_RX_PORT_ID_FULL == 1) +#define RTE_USART3_RX_FULL 1 +#define RTE_USART3_RX_PORT_FULL GPIOD +#define RTE_USART3_RX_BIT_FULL 9 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PD10 +#define RTE_USART3_CK_PORT_ID_FULL 0 +#if (RTE_USART3_CK_PORT_ID_FULL == 0) +#define RTE_USART3_CK_FULL 0 +#elif (RTE_USART3_CK_PORT_ID_FULL == 1) +#define RTE_USART3_CK_FULL 1 +#define RTE_USART3_CK_PORT_FULL GPIOD +#define RTE_USART3_CK_BIT_FULL 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PD11 +#define RTE_USART3_CTS_PORT_ID_FULL 0 +#if (RTE_USART3_CTS_PORT_ID_FULL == 0) +#define RTE_USART3_CTS_FULL 0 +#elif (RTE_USART3_CTS_PORT_ID_FULL == 1) +#define RTE_USART3_CTS_FULL 1 +#define RTE_USART3_CTS_PORT_FULL GPIOD +#define RTE_USART3_CTS_BIT_FULL 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PD12 +#define RTE_USART3_RTS_PORT_ID_FULL 0 +#if (RTE_USART3_RTS_PORT_ID_FULL == 0) +#define RTE_USART3_RTS_FULL 0 +#elif (RTE_USART3_RTS_PORT_ID_FULL == 1) +#define RTE_USART3_RTS_FULL 1 +#define RTE_USART3_RTS_PORT_FULL GPIOD +#define RTE_USART3_RTS_BIT_FULL 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif +// + +#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1)) +#error "Invalid USART3 Pin Remap Configuration!" +#endif + +#if (RTE_USART3_REMAP_FULL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL +#define RTE_USART3_TX RTE_USART3_TX_FULL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL +#define RTE_USART3_RX RTE_USART3_RX_FULL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL +#define RTE_USART3_CK RTE_USART3_CK_FULL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL +#define RTE_USART3_CTS RTE_USART3_CTS_FULL +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL +#define RTE_USART3_RTS RTE_USART3_RTS_FULL +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL +#elif (RTE_USART3_REMAP_PARTIAL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL +#define RTE_USART3_TX RTE_USART3_TX_PARTIAL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL +#define RTE_USART3_RX RTE_USART3_RX_PARTIAL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL +#define RTE_USART3_CK RTE_USART3_CK_PARTIAL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#else +#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP +#define RTE_USART3_TX RTE_USART3_TX_DEF +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF +#define RTE_USART3_RX RTE_USART3_RX_DEF +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF +#define RTE_USART3_CK RTE_USART3_CK_DEF +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_RX_DMA 0 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_CHANNEL 3 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_TX_DMA 0 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_CHANNEL 2 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART +#define RTE_UART4 0 +#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART4_TX Pin <0=>Not Used <1=>PC10 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>Not Used <1=>PC11 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX 0 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_RX_DMA 0 +#define RTE_UART4_RX_DMA_NUMBER 2 +#define RTE_UART4_RX_DMA_CHANNEL 3 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_TX_DMA 0 +#define RTE_UART4_TX_DMA_NUMBER 2 +#define RTE_UART4_TX_DMA_CHANNEL 5 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART +#define RTE_UART5 0 +#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART5_TX Pin <0=>Not Used <1=>PC12 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX 0 +#elif (RTE_UART5_TX_ID == 1) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>Not Used <1=>PD2 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX 0 +#elif (RTE_UART5_RX_ID == 1) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif +// + + +// I2C1 (Inter-integrated Circuit Interface 1) +// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 +#define RTE_I2C1_SCL_PORT_ID_DEF 0 +#if (RTE_I2C1_SCL_PORT_ID_DEF == 0) +#define RTE_I2C1_SCL_PORT_DEF GPIOB +#define RTE_I2C1_SCL_BIT_DEF 6 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 +#define RTE_I2C1_SDA_PORT_ID_DEF 0 +#if (RTE_I2C1_SDA_PORT_ID_DEF == 0) +#define RTE_I2C1_SDA_PORT_DEF GPIOB +#define RTE_I2C1_SDA_BIT_DEF 7 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1 Pin Remap +// Enable I2C1 Pin Remapping +#define RTE_I2C1_REMAP_FULL 0 + +// I2C1_SCL Pin <0=>PB8 +#define RTE_I2C1_SCL_PORT_ID_FULL 0 +#if (RTE_I2C1_SCL_PORT_ID_FULL == 0) +#define RTE_I2C1_SCL_PORT_FULL GPIOB +#define RTE_I2C1_SCL_BIT_FULL 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB9 +#define RTE_I2C1_SDA_PORT_ID_FULL 0 +#if (RTE_I2C1_SDA_PORT_ID_FULL == 0) +#define RTE_I2C1_SDA_PORT_FULL GPIOB +#define RTE_I2C1_SDA_BIT_FULL 9 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// + +#if (RTE_I2C1_REMAP_FULL) +#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL +#else +#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF +#endif + + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 0 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_CHANNEL 7 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 0 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_CHANNEL 6 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) +// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C +#define RTE_I2C2 0 +#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// I2C2_SCL Pin <0=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PB11 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 1 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_CHANNEL 5 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 1 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_CHANNEL 4 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI +#define RTE_SPI1 0 + +// SPI1_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIO_PORT(0) +#define RTE_SPI1_NSS_BIT 4 + +// SPI1_SCK Pin <0=>PA5 +#define RTE_SPI1_SCK_PORT_ID_DEF 0 +#if (RTE_SPI1_SCK_PORT_ID_DEF == 0) +#define RTE_SPI1_SCK_PORT_DEF GPIOA +#define RTE_SPI1_SCK_BIT_DEF 5 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PA6 +#define RTE_SPI1_MISO_PORT_ID_DEF 0 +#if (RTE_SPI1_MISO_PORT_ID_DEF == 0) +#define RTE_SPI1_MISO_DEF 0 +#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1) +#define RTE_SPI1_MISO_DEF 1 +#define RTE_SPI1_MISO_PORT_DEF GPIOA +#define RTE_SPI1_MISO_BIT_DEF 6 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>Not Used <1=>PA7 +#define RTE_SPI1_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI1_MOSI_DEF 0 +#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI1_MOSI_DEF 1 +#define RTE_SPI1_MOSI_PORT_DEF GPIOA +#define RTE_SPI1_MOSI_BIT_DEF 7 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1 Pin Remap +// Enable SPI1 Pin Remapping. +#define RTE_SPI1_REMAP 0 + +// SPI1_SCK Pin <0=>PB3 +#define RTE_SPI1_SCK_PORT_ID_FULL 0 +#if (RTE_SPI1_SCK_PORT_ID_FULL == 0) +#define RTE_SPI1_SCK_PORT_FULL GPIOB +#define RTE_SPI1_SCK_BIT_FULL 3 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI1_MISO_PORT_ID_FULL 0 +#if (RTE_SPI1_MISO_PORT_ID_FULL == 0) +#define RTE_SPI1_MISO_FULL 0 +#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1) +#define RTE_SPI1_MISO_FULL 1 +#define RTE_SPI1_MISO_PORT_FULL GPIOB +#define RTE_SPI1_MISO_BIT_FULL 4 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif +// SPI1_MOSI Pin <0=>Not Used <1=>PB5 +#define RTE_SPI1_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI1_MOSI_FULL 0 +#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI1_MOSI_FULL 1 +#define RTE_SPI1_MOSI_PORT_FULL GPIOB +#define RTE_SPI1_MOSI_BIT_FULL 5 +#else +#error "Invalid SPI1_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI1_REMAP) +#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL +#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL +#else +#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF +#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_RX_DMA 0 +#define RTE_SPI1_RX_DMA_NUMBER 1 +#define RTE_SPI1_RX_DMA_CHANNEL 2 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_TX_DMA 0 +#define RTE_SPI1_TX_DMA_NUMBER 1 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI +#define RTE_SPI2 0 + +// SPI2_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIO_PORT(1) +#define RTE_SPI2_NSS_BIT 12 + +// SPI2_SCK Pin <0=>PB13 +#define RTE_SPI2_SCK_PORT_ID 0 +#if (RTE_SPI2_SCK_PORT_ID == 0) +#define RTE_SPI2_SCK_PORT GPIOB +#define RTE_SPI2_SCK_BIT 13 +#define RTE_SPI2_SCK_REMAP 0 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_MISO Pin <0=>Not Used <1=>PB14 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO 0 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#define RTE_SPI2_MISO_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>Not Used <1=>PB15 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI 0 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#define RTE_SPI2_MOSI_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 0 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_CHANNEL 4 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 0 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_CHANNEL 5 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI +#define RTE_SPI3 0 + +// SPI3_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIO_PORT(0) +#define RTE_SPI3_NSS_BIT 15 + +// SPI3_SCK Pin <0=>PB3 +#define RTE_SPI3_SCK_PORT_ID_DEF 0 +#if (RTE_SPI3_SCK_PORT_ID_DEF == 0) +#define RTE_SPI3_SCK_PORT_DEF GPIOB +#define RTE_SPI3_SCK_BIT_DEF 3 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI3_MISO_PORT_ID_DEF 0 +#if (RTE_SPI3_MISO_PORT_ID_DEF == 0) +#define RTE_SPI3_MISO_DEF 0 +#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1) +#define RTE_SPI3_MISO_DEF 1 +#define RTE_SPI3_MISO_PORT_DEF GPIOB +#define RTE_SPI3_MISO_BIT_DEF 4 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI <0=>Not Used Pin <1=>PB5 +#define RTE_SPI3_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI3_MOSI_DEF 0 +#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI3_MOSI_DEF 1 +#define RTE_SPI3_MOSI_PORT_DEF GPIOB +#define RTE_SPI3_MOSI_BIT_DEF 5 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// SPI3 Pin Remap +// Enable SPI3 Pin Remapping. +// SPI 3 Pin Remapping is available only in connectivity line devices! +#define RTE_SPI3_REMAP 0 + +// SPI3_SCK Pin <0=>PC10 +#define RTE_SPI3_SCK_PORT_ID_FULL 0 +#if (RTE_SPI3_SCK_PORT_ID_FULL == 0) +#define RTE_SPI3_SCK_PORT_FULL GPIOC +#define RTE_SPI3_SCK_BIT_FULL 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PC11 +#define RTE_SPI3_MISO_PORT_ID_FULL 0 +#if (RTE_SPI3_MISO_PORT_ID_FULL == 0) +#define RTE_SPI3_MISO_FULL 0 +#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1) +#define RTE_SPI3_MISO_FULL 1 +#define RTE_SPI3_MISO_PORT_FULL GPIOC +#define RTE_SPI3_MISO_BIT_FULL 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif +// SPI3_MOSI Pin <0=>Not Used <1=>PC12 +#define RTE_SPI3_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI3_MOSI_FULL 0 +#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI3_MOSI_FULL 1 +#define RTE_SPI3_MOSI_PORT_FULL GPIOC +#define RTE_SPI3_MOSI_BIT_FULL 12 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI3_REMAP) +#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL +#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL +#else +#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF +#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 0 +#define RTE_SPI3_RX_DMA_NUMBER 2 +#define RTE_SPI3_RX_DMA_CHANNEL 1 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 0 +#define RTE_SPI3_TX_DMA_NUMBER 2 +#define RTE_SPI3_TX_DMA_CHANNEL 2 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SDIO (Secure Digital Input/Output) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI +#define RTE_SDIO 0 + +// SDIO Peripheral Bus +// SDIO_CK Pin <0=>PC12 +#define RTE_SDIO_CK_PORT_ID 0 +#if (RTE_SDIO_CK_PORT_ID == 0) + #define RTE_SDIO_CK_PORT GPIOC + #define RTE_SDIO_CK_PIN 12 +#else + #error "Invalid SDIO_CLK Pin Configuration!" +#endif +// SDIO_CMD Pin <0=>PD2 +#define RTE_SDIO_CMD_PORT_ID 0 +#if (RTE_SDIO_CMD_PORT_ID == 0) + #define RTE_SDIO_CMD_PORT GPIOD + #define RTE_SDIO_CMD_PIN 2 +#else + #error "Invalid SDIO_CMD Pin Configuration!" +#endif +// SDIO_D0 Pin <0=>PC8 +#define RTE_SDIO_D0_PORT_ID 0 +#if (RTE_SDIO_D0_PORT_ID == 0) + #define RTE_SDIO_D0_PORT GPIOC + #define RTE_SDIO_D0_PIN 8 +#else + #error "Invalid SDIO_DAT0 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +#define RTE_SDIO_BUS_WIDTH_4 1 +// SDIO_D1 Pin <0=>PC9 +#define RTE_SDIO_D1_PORT_ID 0 +#if (RTE_SDIO_D1_PORT_ID == 0) + #define RTE_SDIO_D1_PORT GPIOC + #define RTE_SDIO_D1_PIN 9 +#else + #error "Invalid SDIO_D1 Pin Configuration!" +#endif +// SDIO_D2 Pin <0=>PC10 +#define RTE_SDIO_D2_PORT_ID 0 +#if (RTE_SDIO_D2_PORT_ID == 0) + #define RTE_SDIO_D2_PORT GPIOC + #define RTE_SDIO_D2_PIN 10 +#else + #error "Invalid SDIO_D2 Pin Configuration!" +#endif +// SDIO_D3 Pin <0=>PC11 +#define RTE_SDIO_D3_PORT_ID 0 +#if (RTE_SDIO_D3_PORT_ID == 0) + #define RTE_SDIO_D3_PORT GPIOC + #define RTE_SDIO_D3_PIN 11 +#else + #error "Invalid SDIO_D3 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +// SDIO_D[4 .. 7] +#define RTE_SDIO_BUS_WIDTH_8 0 +// SDIO_D4 Pin <0=>PB8 +#define RTE_SDIO_D4_PORT_ID 0 +#if (RTE_SDIO_D4_PORT_ID == 0) + #define RTE_SDIO_D4_PORT GPIOB + #define RTE_SDIO_D4_PIN 8 +#else + #error "Invalid SDIO_D4 Pin Configuration!" +#endif +// SDIO_D5 Pin <0=>PB9 +#define RTE_SDIO_D5_PORT_ID 0 +#if (RTE_SDIO_D5_PORT_ID == 0) + #define RTE_SDIO_D5_PORT GPIOB + #define RTE_SDIO_D5_PIN 9 +#else + #error "Invalid SDIO_D5 Pin Configuration!" +#endif +// SDIO_D6 Pin <0=>PC6 +#define RTE_SDIO_D6_PORT_ID 0 +#if (RTE_SDIO_D6_PORT_ID == 0) + #define RTE_SDIO_D6_PORT GPIOC + #define RTE_SDIO_D6_PIN 6 +#else + #error "Invalid SDIO_D6 Pin Configuration!" +#endif +// SDIO_D7 Pin <0=>PC7 +#define RTE_SDIO_D7_PORT_ID 0 +#if (RTE_SDIO_D7_PORT_ID == 0) + #define RTE_SDIO_D7_PORT GPIOC + #define RTE_SDIO_D7_PIN 7 +#else + #error "Invalid SDIO_D7 Pin Configuration!" +#endif +// SDIO_D[4 .. 7] +// SDIO Peripheral Bus + +// Card Detect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_CD_EN 1 +#define RTE_SDIO_CD_ACTIVE 0 +#define RTE_SDIO_CD_PORT GPIO_PORT(5) +#define RTE_SDIO_CD_PIN 11 + +// Write Protect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_WP_EN 0 +#define RTE_SDIO_WP_ACTIVE 1 +#define RTE_SDIO_WP_PORT GPIO_PORT(0) +#define RTE_SDIO_WP_PIN 10 + +// DMA +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_DMA_NUMBER 2 +#define RTE_SDIO_DMA_CHANNEL 4 +#define RTE_SDIO_DMA_PRIORITY 0 + +// + + +// CAN1 (Controller Area Network 1) [Driver_CAN1] +// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN +#define RTE_CAN1 0 + +// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 +#define RTE_CAN1_RX_PORT_ID 0 +#if (RTE_CAN1_RX_PORT_ID == 0) +#define RTE_CAN1_RX_PORT GPIOA +#define RTE_CAN1_RX_BIT 11 +#elif (RTE_CAN1_RX_PORT_ID == 1) +#define RTE_CAN1_RX_PORT GPIOB +#define RTE_CAN1_RX_BIT 8 +#elif (RTE_CAN1_RX_PORT_ID == 2) +#define RTE_CAN1_RX_PORT GPIOD +#define RTE_CAN1_RX_BIT 0 +#else +#error "Invalid CAN1_RX Pin Configuration!" +#endif + +// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 +#define RTE_CAN1_TX_PORT_ID 0 +#if (RTE_CAN1_TX_PORT_ID == 0) +#define RTE_CAN1_TX_PORT GPIOA +#define RTE_CAN1_TX_BIT 12 +#elif (RTE_CAN1_TX_PORT_ID == 1) +#define RTE_CAN1_TX_PORT GPIOB +#define RTE_CAN1_TX_BIT 9 +#elif (RTE_CAN1_TX_PORT_ID == 2) +#define RTE_CAN1_TX_PORT GPIOD +#define RTE_CAN1_TX_BIT 1 +#else +#error "Invalid CAN1_TX Pin Configuration!" +#endif + +// + + +// CAN2 (Controller Area Network 2) [Driver_CAN2] +// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN +#define RTE_CAN2 0 + +// CAN2_RX Pin <0=>PB5 <1=>PB12 +#define RTE_CAN2_RX_PORT_ID 0 +#if (RTE_CAN2_RX_PORT_ID == 0) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 5 +#elif (RTE_CAN2_RX_PORT_ID == 1) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 12 +#else +#error "Invalid CAN2_RX Pin Configuration!" +#endif + +// CAN2_TX Pin <0=>PB6 <1=>PB13 +#define RTE_CAN2_TX_PORT_ID 0 +#if (RTE_CAN2_TX_PORT_ID == 0) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 6 +#elif (RTE_CAN2_TX_PORT_ID == 1) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 13 +#else +#error "Invalid CAN2_TX Pin Configuration!" +#endif + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC +#define RTE_ETH 0 + +// MII (Media Independent Interface) +// Enable Media Independent Interface pin configuration +#define RTE_ETH_MII 0 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_DEF 0 + +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_DEF 0 + +// ETH_MII_RXD2 Pin <0=>PB0 +#define RTE_ETH_MII_RXD2_DEF 0 + +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12 +#define RTE_ETH_MII_RXD3_DEF 0 + +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_DEF 0 + +// ETH_MII_RX_ER Pin <0=>PB10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>PA0 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>PA3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_MII_REMAP 0 + +// ETH_MII_RXD0 Pin <1=>PD9 +#define RTE_ETH_MII_RXD0_REMAP 1 + +// ETH_MII_RXD1 Pin <1=>PD10 +#define RTE_ETH_MII_RXD1_REMAP 1 + +// ETH_MII_RXD2 Pin <1=>PD11 +#define RTE_ETH_MII_RXD2_REMAP 1 + +// ETH_MII_RXD3 Pin <1=>PD12 +#define RTE_ETH_MII_RXD3_REMAP 1 + +// ETH_MII_RX_DV Pin <1=>PD8 +#define RTE_ETH_MII_RX_DV_REMAP 1 +// + +// + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0)) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1)) +#define RTE_ETH_MII_RXD0_PORT GPIOD +#define RTE_ETH_MII_RXD0_PIN 9 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0)) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1)) +#define RTE_ETH_MII_RXD1_PORT GPIOD +#define RTE_ETH_MII_RXD1_PIN 10 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0)) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1)) +#define RTE_ETH_MII_RXD2_PORT GPIOD +#define RTE_ETH_MII_RXD2_PIN 11 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0)) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1)) +#define RTE_ETH_MII_RXD3_PORT GPIOD +#define RTE_ETH_MII_RXD3_PIN 12 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0)) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1)) +#define RTE_ETH_MII_RX_DV_PORT GPIOD +#define RTE_ETH_MII_RX_DV_PIN 8 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 0 + +// ETH_RMII_TXD0 Pin <0=>PB12 +#define RTE_ETH_RMII_TXD0_PORT_ID 0 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 +#define RTE_ETH_RMII_TXD1_PORT_ID 0 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 0 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_DEF 0 + +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_DEF 0 + +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_DEF 0 + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_RMII_REMAP 0 +// ETH_RMII_RXD0 Pin <1=>PD9 +#define RTE_ETH_RMII_RXD0_REMAP 1 + +// ETH_RMII_RXD1 Pin <1=>PD10 +#define RTE_ETH_RMII_RXD1_REMAP 1 + +// ETH_RMII_CRS_DV Pin <1=>PD8 +#define RTE_ETH_RMII_CRS_DV_REMAP 1 +// + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0)) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1)) +#define RTE_ETH_RMII_RXD0_PORT GPIOD +#define RTE_ETH_RMII_RXD0_PIN 9 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0)) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1)) +#define RTE_ETH_RMII_RXD1_PORT GPIOD +#define RTE_ETH_RMII_RXD1_PIN 10 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOD +#define RTE_ETH_RMII_CRS_DV_PIN 8 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// Management Data Interface +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_MDI_MDC_PORT_ID 0 +#if (RTE_ETH_MDI_MDC_PORT_ID == 0) +#define RTE_ETH_MDI_MDC_PORT GPIOC +#define RTE_ETH_MDI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_MDI_MDIO_PORT_ID 0 +#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) +#define RTE_ETH_MDI_MDIO_PORT GPIOA +#define RTE_ETH_MDI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled +#define RTE_ETH_REF_CLOCK_ID 0 +#if (RTE_ETH_REF_CLOCK_ID == 0) +#define RTE_ETH_REF_CLOCK 0 +#elif (RTE_ETH_REF_CLOCK_ID == 1) +#define RTE_ETH_REF_CLOCK 1 +#else +#error "Invalid MCO Ethernet Reference Clock Configuration!" +#endif +// + + +// USB Device Full-speed +// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device +#define RTE_USB_DEVICE 0 + +// CON On/Off Pin +// Configure Pin for driving D+ pull-up +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_USB_DEVICE_CON_PIN 1 +#define RTE_USB_DEVICE_CON_ACTIVE 0 +#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1) +#define RTE_USB_DEVICE_CON_BIT 14 + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host + +#define RTE_USB_OTG_FS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 1 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2) +#define RTE_OTG_FS_VBUS_BIT 9 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 1 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(4) +#define RTE_OTG_FS_OC_BIT 1 +// + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.update@1.0.1 b/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.update@1.0.1 new file mode 100644 index 0000000..1ab7096 --- /dev/null +++ b/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.update@1.0.1 @@ -0,0 +1,308 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.5.1 +;* Date : 08-September-2021 +;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Copyright (c) 2011 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/RTE/Device/STM32F103RB/system_stm32f10x.c.update@1.0.1 b/RTE/Device/STM32F103RB/system_stm32f10x.c.update@1.0.1 new file mode 100644 index 0000000..9e31f67 --- /dev/null +++ b/RTE/Device/STM32F103RB/system_stm32f10x.c.update@1.0.1 @@ -0,0 +1,1092 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.5.1 + * @date 08-September-2021 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2011 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depending on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/RTE/Device/STM32F107VC/RTE_Device.h.base@1.1.2 b/RTE/Device/STM32F107VC/RTE_Device.h.base@1.1.2 new file mode 100644 index 0000000..0d10ed8 --- /dev/null +++ b/RTE/Device/STM32F107VC/RTE_Device.h.base@1.1.2 @@ -0,0 +1,1828 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2016 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 09. September 2016 + * $Revision: V1.1.2 + * + * Project: RTE Device Configuration for STMicroelectronics STM32F1xx + * + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT(num) \ + ((num == 0) ? GPIOA : \ + (num == 1) ? GPIOB : \ + (num == 2) ? GPIOC : \ + (num == 3) ? GPIOD : \ + (num == 4) ? GPIOE : \ + (num == 5) ? GPIOF : \ + (num == 6) ? GPIOG : \ + NULL) + + +// Clock Configuration +// High-speed Internal Clock <1-999999999> +#define RTE_HSI 8000000 +// High-speed External Clock <1-999999999> +#define RTE_HSE 25000000 +// System Clock <1-999999999> +#define RTE_SYSCLK 72000000 +// HCLK Clock <1-999999999> +#define RTE_HCLK 72000000 +// APB1 Clock <1-999999999> +#define RTE_PCLK1 36000000 +// APB2 Clock <1-999999999> +#define RTE_PCLK2 72000000 +// ADC Clock <1-999999999> +#define RTE_ADCCLK 36000000 +// USB Clock +#define RTE_USBCLK 48000000 +// + + +// USART1 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + +// USART1_TX Pin <0=>Not Used <1=>PA9 +#define RTE_USART1_TX_PORT_ID_DEF 0 +#if (RTE_USART1_TX_PORT_ID_DEF == 0) +#define RTE_USART1_TX_DEF 0 +#elif (RTE_USART1_TX_PORT_ID_DEF == 1) +#define RTE_USART1_TX_DEF 1 +#define RTE_USART1_TX_PORT_DEF GPIOA +#define RTE_USART1_TX_BIT_DEF 9 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PA10 +#define RTE_USART1_RX_PORT_ID_DEF 0 +#if (RTE_USART1_RX_PORT_ID_DEF == 0) +#define RTE_USART1_RX_DEF 0 +#elif (RTE_USART1_RX_PORT_ID_DEF == 1) +#define RTE_USART1_RX_DEF 1 +#define RTE_USART1_RX_PORT_DEF GPIOA +#define RTE_USART1_RX_BIT_DEF 10 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// USART1_CK Pin <0=>Not Used <1=>PA8 +#define RTE_USART1_CK_PORT_ID_DEF 0 +#if (RTE_USART1_CK_PORT_ID_DEF == 0) +#define RTE_USART1_CK 0 +#elif (RTE_USART1_CK_PORT_ID_DEF == 1) +#define RTE_USART1_CK 1 +#define RTE_USART1_CK_PORT_DEF GPIOA +#define RTE_USART1_CK_BIT_DEF 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// USART1_CTS Pin <0=>Not Used <1=>PA11 +#define RTE_USART1_CTS_PORT_ID_DEF 0 +#if (RTE_USART1_CTS_PORT_ID_DEF == 0) +#define RTE_USART1_CTS 0 +#elif (RTE_USART1_CTS_PORT_ID_DEF == 1) +#define RTE_USART1_CTS 1 +#define RTE_USART1_CTS_PORT_DEF GPIOA +#define RTE_USART1_CTS_BIT_DEF 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif + +// USART1_RTS Pin <0=>Not Used <1=>PA12 +#define RTE_USART1_RTS_PORT_ID_DEF 0 +#if (RTE_USART1_RTS_PORT_ID_DEF == 0) +#define RTE_USART1_RTS 0 +#elif (RTE_USART1_RTS_PORT_ID_DEF == 1) +#define RTE_USART1_RTS 1 +#define RTE_USART1_RTS_PORT_DEF GPIOA +#define RTE_USART1_RTS_BIT_DEF 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// USART1 Pin Remap +// Enable USART1 Pin Remapping +#define RTE_USART1_REMAP_FULL 0 + +// USART1_TX Pin <0=>Not Used <1=>PB6 +#define RTE_USART1_TX_PORT_ID_FULL 0 +#if (RTE_USART1_TX_PORT_ID_FULL == 0) +#define RTE_USART1_TX_FULL 0 +#elif (RTE_USART1_TX_PORT_ID_FULL == 1) +#define RTE_USART1_TX_FULL 1 +#define RTE_USART1_TX_PORT_FULL GPIOB +#define RTE_USART1_TX_BIT_FULL 6 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PB7 +#define RTE_USART1_RX_PORT_ID_FULL 0 +#if (RTE_USART1_RX_PORT_ID_FULL == 0) +#define RTE_USART1_RX_FULL 0 +#elif (RTE_USART1_RX_PORT_ID_FULL == 1) +#define RTE_USART1_RX_FULL 1 +#define RTE_USART1_RX_PORT_FULL GPIOB +#define RTE_USART1_RX_BIT_FULL 7 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif +// + +#if (RTE_USART1_REMAP_FULL) +#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP +#define RTE_USART1_TX RTE_USART1_TX_FULL +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL +#define RTE_USART1_RX RTE_USART1_RX_FULL +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#else +#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP +#define RTE_USART1_TX RTE_USART1_TX_DEF +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF +#define RTE_USART1_RX RTE_USART1_RX_DEF +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_RX_DMA 0 +#define RTE_USART1_RX_DMA_NUMBER 1 +#define RTE_USART1_RX_DMA_CHANNEL 5 +#define RTE_USART1_RX_DMA_PRIORITY 0 +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_TX_DMA 0 +#define RTE_USART1_TX_DMA_NUMBER 1 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_USART2 0 + +// USART2_TX Pin <0=>Not Used <1=>PA2 +#define RTE_USART2_TX_PORT_ID_DEF 0 +#if (RTE_USART2_TX_PORT_ID_DEF == 0) +#define RTE_USART2_TX_DEF 0 +#elif (RTE_USART2_TX_PORT_ID_DEF == 1) +#define RTE_USART2_TX_DEF 1 +#define RTE_USART2_TX_PORT_DEF GPIOA +#define RTE_USART2_TX_BIT_DEF 2 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PA3 +#define RTE_USART2_RX_PORT_ID_DEF 0 +#if (RTE_USART2_RX_PORT_ID_DEF == 0) +#define RTE_USART2_RX_DEF 0 +#elif (RTE_USART2_RX_PORT_ID_DEF == 1) +#define RTE_USART2_RX_DEF 1 +#define RTE_USART2_RX_PORT_DEF GPIOA +#define RTE_USART2_RX_BIT_DEF 3 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PA4 +#define RTE_USART2_CK_PORT_ID_DEF 0 +#if (RTE_USART2_CK_PORT_ID_DEF == 0) +#define RTE_USART2_CK_DEF 0 +#elif (RTE_USART2_CK_PORT_ID_DEF == 1) +#define RTE_USART2_CK_DEF 1 +#define RTE_USART2_CK_PORT_DEF GPIOA +#define RTE_USART2_CK_BIT_DEF 4 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PA0 +#define RTE_USART2_CTS_PORT_ID_DEF 0 +#if (RTE_USART2_CTS_PORT_ID_DEF == 0) +#define RTE_USART2_CTS_DEF 0 +#elif (RTE_USART2_CTS_PORT_ID_DEF == 1) +#define RTE_USART2_CTS_DEF 1 +#define RTE_USART2_CTS_PORT_DEF GPIOA +#define RTE_USART2_CTS_BIT_DEF 0 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PA1 +#define RTE_USART2_RTS_PORT_ID_DEF 0 +#if (RTE_USART2_RTS_PORT_ID_DEF == 0) +#define RTE_USART2_RTS_DEF 0 +#elif (RTE_USART2_RTS_PORT_ID_DEF == 1) +#define RTE_USART2_RTS_DEF 1 +#define RTE_USART2_RTS_PORT_DEF GPIOA +#define RTE_USART2_RTS_BIT_DEF 1 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// USART2 Pin Remap +// Enable USART2 Pin Remapping +#define RTE_USART2_REMAP_FULL 0 + +// USART2_TX Pin <0=>Not Used <1=>PD5 +#define RTE_USART2_TX_PORT_ID_FULL 0 +#if (RTE_USART2_TX_PORT_ID_FULL == 0) +#define RTE_USART2_TX_FULL 0 +#elif (RTE_USART2_TX_PORT_ID_FULL == 1) +#define RTE_USART2_TX_FULL 1 +#define RTE_USART2_TX_PORT_FULL GPIOD +#define RTE_USART2_TX_BIT_FULL 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PD6 +#define RTE_USART2_RX_PORT_ID_FULL 0 +#if (RTE_USART2_RX_PORT_ID_FULL == 0) +#define RTE_USART2_RX_FULL 0 +#elif (RTE_USART2_RX_PORT_ID_FULL == 1) +#define RTE_USART2_RX_FULL 1 +#define RTE_USART2_RX_PORT_FULL GPIOD +#define RTE_USART2_RX_BIT_FULL 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PD7 +#define RTE_USART2_CK_PORT_ID_FULL 0 +#if (RTE_USART2_CK_PORT_ID_FULL == 0) +#define RTE_USART2_CK_FULL 0 +#elif (RTE_USART2_CK_PORT_ID_FULL == 1) +#define RTE_USART2_CK_FULL 1 +#define RTE_USART2_CK_PORT_FULL GPIOD +#define RTE_USART2_CK_BIT_FULL 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PD3 +#define RTE_USART2_CTS_PORT_ID_FULL 0 +#if (RTE_USART2_CTS_PORT_ID_FULL == 0) +#define RTE_USART2_CTS_FULL 0 +#elif (RTE_USART2_CTS_PORT_ID_FULL == 1) +#define RTE_USART2_CTS_FULL 1 +#define RTE_USART2_CTS_PORT_FULL GPIOD +#define RTE_USART2_CTS_BIT_FULL 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PD4 +#define RTE_USART2_RTS_PORT_ID_FULL 0 +#if (RTE_USART2_RTS_PORT_ID_FULL == 0) +#define RTE_USART2_RTS_FULL 0 +#elif (RTE_USART2_RTS_PORT_ID_FULL == 1) +#define RTE_USART2_RTS_FULL 1 +#define RTE_USART2_RTS_PORT_FULL GPIOD +#define RTE_USART2_RTS_BIT_FULL 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif +// + +#if (RTE_USART2_REMAP_FULL) +#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP +#define RTE_USART2_TX RTE_USART2_TX_FULL +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL +#define RTE_USART2_RX RTE_USART2_RX_FULL +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL +#define RTE_USART2_CK RTE_USART2_CK_FULL +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL +#define RTE_USART2_CTS RTE_USART2_CTS_FULL +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL +#define RTE_USART2_RTS RTE_USART2_RTS_FULL +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL +#else +#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP +#define RTE_USART2_TX RTE_USART2_TX_DEF +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF +#define RTE_USART2_RX RTE_USART2_RX_DEF +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF +#define RTE_USART2_CK RTE_USART2_CK_DEF +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF +#define RTE_USART2_CTS RTE_USART2_CTS_DEF +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF +#define RTE_USART2_RTS RTE_USART2_RTS_DEF +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_RX_DMA 0 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_CHANNEL 6 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_TX_DMA 0 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_CHANNEL 7 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>Not Used <1=>PB10 +#define RTE_USART3_TX_PORT_ID_DEF 0 +#if (RTE_USART3_TX_PORT_ID_DEF == 0) +#define RTE_USART3_TX_DEF 0 +#elif (RTE_USART3_TX_PORT_ID_DEF == 1) +#define RTE_USART3_TX_DEF 1 +#define RTE_USART3_TX_PORT_DEF GPIOB +#define RTE_USART3_TX_BIT_DEF 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PB11 +#define RTE_USART3_RX_PORT_ID_DEF 0 +#if (RTE_USART3_RX_PORT_ID_DEF == 0) +#define RTE_USART3_RX_DEF 0 +#elif (RTE_USART3_RX_PORT_ID_DEF == 1) +#define RTE_USART3_RX_DEF 1 +#define RTE_USART3_RX_PORT_DEF GPIOB +#define RTE_USART3_RX_BIT_DEF 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PB12 +#define RTE_USART3_CK_PORT_ID_DEF 0 +#if (RTE_USART3_CK_PORT_ID_DEF == 0) +#define RTE_USART3_CK_DEF 0 +#elif (RTE_USART3_CK_PORT_ID_DEF == 1) +#define RTE_USART3_CK_DEF 1 +#define RTE_USART3_CK_PORT_DEF GPIOB +#define RTE_USART3_CK_BIT_DEF 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PB13 +#define RTE_USART3_CTS_PORT_ID_DEF 0 +#if (RTE_USART3_CTS_PORT_ID_DEF == 0) +#define RTE_USART3_CTS_DEF 0 +#elif (RTE_USART3_CTS_PORT_ID_DEF == 1) +#define RTE_USART3_CTS_DEF 1 +#define RTE_USART3_CTS_PORT_DEF GPIOB +#define RTE_USART3_CTS_BIT_DEF 13 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PB14 +#define RTE_USART3_RTS_PORT_ID_DEF 0 +#if (RTE_USART3_RTS_PORT_ID_DEF == 0) +#define RTE_USART3_RTS_DEF 0 +#elif (RTE_USART3_RTS_PORT_ID_DEF == 1) +#define RTE_USART3_RTS_DEF 1 +#define RTE_USART3_RTS_PORT_DEF GPIOB +#define RTE_USART3_RTS_BIT_DEF 14 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// USART3 Partial Pin Remap +// Enable USART3 Partial Pin Remapping +#define RTE_USART3_REMAP_PARTIAL 0 + +// USART3_TX Pin <0=>Not Used <1=>PC10 +#define RTE_USART3_TX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_TX_PARTIAL 0 +#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_TX_PARTIAL 1 +#define RTE_USART3_TX_PORT_PARTIAL GPIOC +#define RTE_USART3_TX_BIT_PARTIAL 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PC11 +#define RTE_USART3_RX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_RX_PARTIAL 0 +#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_RX_PARTIAL 1 +#define RTE_USART3_RX_PORT_PARTIAL GPIOC +#define RTE_USART3_RX_BIT_PARTIAL 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PC12 +#define RTE_USART3_CK_PORT_ID_PARTIAL 0 +#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0) +#define RTE_USART3_CK_PARTIAL 0 +#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1) +#define RTE_USART3_CK_PARTIAL 1 +#define RTE_USART3_CK_PORT_PARTIAL GPIOC +#define RTE_USART3_CK_BIT_PARTIAL 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif +// + +// USART3 Full Pin Remap +// Enable USART3 Full Pin Remapping +#define RTE_USART3_REMAP_FULL 0 + +// USART3_TX Pin <0=>Not Used <1=>PD8 +#define RTE_USART3_TX_PORT_ID_FULL 0 +#if (RTE_USART3_TX_PORT_ID_FULL == 0) +#define RTE_USART3_TX_FULL 0 +#elif (RTE_USART3_TX_PORT_ID_FULL == 1) +#define RTE_USART3_TX_FULL 1 +#define RTE_USART3_TX_PORT_FULL GPIOD +#define RTE_USART3_TX_BIT_FULL 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PD9 +#define RTE_USART3_RX_PORT_ID_FULL 0 +#if (RTE_USART3_RX_PORT_ID_FULL == 0) +#define RTE_USART3_RX_FULL 0 +#elif (RTE_USART3_RX_PORT_ID_FULL == 1) +#define RTE_USART3_RX_FULL 1 +#define RTE_USART3_RX_PORT_FULL GPIOD +#define RTE_USART3_RX_BIT_FULL 9 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PD10 +#define RTE_USART3_CK_PORT_ID_FULL 0 +#if (RTE_USART3_CK_PORT_ID_FULL == 0) +#define RTE_USART3_CK_FULL 0 +#elif (RTE_USART3_CK_PORT_ID_FULL == 1) +#define RTE_USART3_CK_FULL 1 +#define RTE_USART3_CK_PORT_FULL GPIOD +#define RTE_USART3_CK_BIT_FULL 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PD11 +#define RTE_USART3_CTS_PORT_ID_FULL 0 +#if (RTE_USART3_CTS_PORT_ID_FULL == 0) +#define RTE_USART3_CTS_FULL 0 +#elif (RTE_USART3_CTS_PORT_ID_FULL == 1) +#define RTE_USART3_CTS_FULL 1 +#define RTE_USART3_CTS_PORT_FULL GPIOD +#define RTE_USART3_CTS_BIT_FULL 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PD12 +#define RTE_USART3_RTS_PORT_ID_FULL 0 +#if (RTE_USART3_RTS_PORT_ID_FULL == 0) +#define RTE_USART3_RTS_FULL 0 +#elif (RTE_USART3_RTS_PORT_ID_FULL == 1) +#define RTE_USART3_RTS_FULL 1 +#define RTE_USART3_RTS_PORT_FULL GPIOD +#define RTE_USART3_RTS_BIT_FULL 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif +// + +#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1)) +#error "Invalid USART3 Pin Remap Configuration!" +#endif + +#if (RTE_USART3_REMAP_FULL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL +#define RTE_USART3_TX RTE_USART3_TX_FULL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL +#define RTE_USART3_RX RTE_USART3_RX_FULL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL +#define RTE_USART3_CK RTE_USART3_CK_FULL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL +#define RTE_USART3_CTS RTE_USART3_CTS_FULL +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL +#define RTE_USART3_RTS RTE_USART3_RTS_FULL +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL +#elif (RTE_USART3_REMAP_PARTIAL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL +#define RTE_USART3_TX RTE_USART3_TX_PARTIAL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL +#define RTE_USART3_RX RTE_USART3_RX_PARTIAL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL +#define RTE_USART3_CK RTE_USART3_CK_PARTIAL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#else +#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP +#define RTE_USART3_TX RTE_USART3_TX_DEF +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF +#define RTE_USART3_RX RTE_USART3_RX_DEF +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF +#define RTE_USART3_CK RTE_USART3_CK_DEF +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_RX_DMA 0 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_CHANNEL 3 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_TX_DMA 0 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_CHANNEL 2 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART +#define RTE_UART4 0 +#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART4_TX Pin <0=>Not Used <1=>PC10 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>Not Used <1=>PC11 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX 0 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_RX_DMA 0 +#define RTE_UART4_RX_DMA_NUMBER 2 +#define RTE_UART4_RX_DMA_CHANNEL 3 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_TX_DMA 0 +#define RTE_UART4_TX_DMA_NUMBER 2 +#define RTE_UART4_TX_DMA_CHANNEL 5 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART +#define RTE_UART5 0 +#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART5_TX Pin <0=>Not Used <1=>PC12 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX 0 +#elif (RTE_UART5_TX_ID == 1) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>Not Used <1=>PD2 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX 0 +#elif (RTE_UART5_RX_ID == 1) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif +// + + +// I2C1 (Inter-integrated Circuit Interface 1) +// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 +#define RTE_I2C1_SCL_PORT_ID_DEF 0 +#if (RTE_I2C1_SCL_PORT_ID_DEF == 0) +#define RTE_I2C1_SCL_PORT_DEF GPIOB +#define RTE_I2C1_SCL_BIT_DEF 6 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 +#define RTE_I2C1_SDA_PORT_ID_DEF 0 +#if (RTE_I2C1_SDA_PORT_ID_DEF == 0) +#define RTE_I2C1_SDA_PORT_DEF GPIOB +#define RTE_I2C1_SDA_BIT_DEF 7 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1 Pin Remap +// Enable I2C1 Pin Remapping +#define RTE_I2C1_REMAP_FULL 0 + +// I2C1_SCL Pin <0=>PB8 +#define RTE_I2C1_SCL_PORT_ID_FULL 0 +#if (RTE_I2C1_SCL_PORT_ID_FULL == 0) +#define RTE_I2C1_SCL_PORT_FULL GPIOB +#define RTE_I2C1_SCL_BIT_FULL 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB9 +#define RTE_I2C1_SDA_PORT_ID_FULL 0 +#if (RTE_I2C1_SDA_PORT_ID_FULL == 0) +#define RTE_I2C1_SDA_PORT_FULL GPIOB +#define RTE_I2C1_SDA_BIT_FULL 9 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// + +#if (RTE_I2C1_REMAP_FULL) +#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL +#else +#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF +#endif + + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 0 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_CHANNEL 7 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 0 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_CHANNEL 6 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) +// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C +#define RTE_I2C2 0 +#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// I2C2_SCL Pin <0=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PB11 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 1 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_CHANNEL 5 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 1 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_CHANNEL 4 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI +#define RTE_SPI1 0 + +// SPI1_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIO_PORT(0) +#define RTE_SPI1_NSS_BIT 4 + +// SPI1_SCK Pin <0=>PA5 +#define RTE_SPI1_SCK_PORT_ID_DEF 0 +#if (RTE_SPI1_SCK_PORT_ID_DEF == 0) +#define RTE_SPI1_SCK_PORT_DEF GPIOA +#define RTE_SPI1_SCK_BIT_DEF 5 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PA6 +#define RTE_SPI1_MISO_PORT_ID_DEF 0 +#if (RTE_SPI1_MISO_PORT_ID_DEF == 0) +#define RTE_SPI1_MISO_DEF 0 +#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1) +#define RTE_SPI1_MISO_DEF 1 +#define RTE_SPI1_MISO_PORT_DEF GPIOA +#define RTE_SPI1_MISO_BIT_DEF 6 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>Not Used <1=>PA7 +#define RTE_SPI1_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI1_MOSI_DEF 0 +#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI1_MOSI_DEF 1 +#define RTE_SPI1_MOSI_PORT_DEF GPIOA +#define RTE_SPI1_MOSI_BIT_DEF 7 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1 Pin Remap +// Enable SPI1 Pin Remapping. +#define RTE_SPI1_REMAP 0 + +// SPI1_SCK Pin <0=>PB3 +#define RTE_SPI1_SCK_PORT_ID_FULL 0 +#if (RTE_SPI1_SCK_PORT_ID_FULL == 0) +#define RTE_SPI1_SCK_PORT_FULL GPIOB +#define RTE_SPI1_SCK_BIT_FULL 3 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI1_MISO_PORT_ID_FULL 0 +#if (RTE_SPI1_MISO_PORT_ID_FULL == 0) +#define RTE_SPI1_MISO_FULL 0 +#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1) +#define RTE_SPI1_MISO_FULL 1 +#define RTE_SPI1_MISO_PORT_FULL GPIOB +#define RTE_SPI1_MISO_BIT_FULL 4 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif +// SPI1_MOSI Pin <0=>Not Used <1=>PB5 +#define RTE_SPI1_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI1_MOSI_FULL 0 +#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI1_MOSI_FULL 1 +#define RTE_SPI1_MOSI_PORT_FULL GPIOB +#define RTE_SPI1_MOSI_BIT_FULL 5 +#else +#error "Invalid SPI1_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI1_REMAP) +#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL +#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL +#else +#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF +#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_RX_DMA 0 +#define RTE_SPI1_RX_DMA_NUMBER 1 +#define RTE_SPI1_RX_DMA_CHANNEL 2 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_TX_DMA 0 +#define RTE_SPI1_TX_DMA_NUMBER 1 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI +#define RTE_SPI2 0 + +// SPI2_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIO_PORT(1) +#define RTE_SPI2_NSS_BIT 12 + +// SPI2_SCK Pin <0=>PB13 +#define RTE_SPI2_SCK_PORT_ID 0 +#if (RTE_SPI2_SCK_PORT_ID == 0) +#define RTE_SPI2_SCK_PORT GPIOB +#define RTE_SPI2_SCK_BIT 13 +#define RTE_SPI2_SCK_REMAP 0 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_MISO Pin <0=>Not Used <1=>PB14 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO 0 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#define RTE_SPI2_MISO_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>Not Used <1=>PB15 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI 0 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#define RTE_SPI2_MOSI_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 0 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_CHANNEL 4 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 0 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_CHANNEL 5 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI +#define RTE_SPI3 0 + +// SPI3_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIO_PORT(0) +#define RTE_SPI3_NSS_BIT 15 + +// SPI3_SCK Pin <0=>PB3 +#define RTE_SPI3_SCK_PORT_ID_DEF 0 +#if (RTE_SPI3_SCK_PORT_ID_DEF == 0) +#define RTE_SPI3_SCK_PORT_DEF GPIOB +#define RTE_SPI3_SCK_BIT_DEF 3 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI3_MISO_PORT_ID_DEF 0 +#if (RTE_SPI3_MISO_PORT_ID_DEF == 0) +#define RTE_SPI3_MISO_DEF 0 +#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1) +#define RTE_SPI3_MISO_DEF 1 +#define RTE_SPI3_MISO_PORT_DEF GPIOB +#define RTE_SPI3_MISO_BIT_DEF 4 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI <0=>Not Used Pin <1=>PB5 +#define RTE_SPI3_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI3_MOSI_DEF 0 +#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI3_MOSI_DEF 1 +#define RTE_SPI3_MOSI_PORT_DEF GPIOB +#define RTE_SPI3_MOSI_BIT_DEF 5 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// SPI3 Pin Remap +// Enable SPI3 Pin Remapping. +// SPI 3 Pin Remapping is available only in connectivity line devices! +#define RTE_SPI3_REMAP 0 + +// SPI3_SCK Pin <0=>PC10 +#define RTE_SPI3_SCK_PORT_ID_FULL 0 +#if (RTE_SPI3_SCK_PORT_ID_FULL == 0) +#define RTE_SPI3_SCK_PORT_FULL GPIOC +#define RTE_SPI3_SCK_BIT_FULL 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PC11 +#define RTE_SPI3_MISO_PORT_ID_FULL 0 +#if (RTE_SPI3_MISO_PORT_ID_FULL == 0) +#define RTE_SPI3_MISO_FULL 0 +#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1) +#define RTE_SPI3_MISO_FULL 1 +#define RTE_SPI3_MISO_PORT_FULL GPIOC +#define RTE_SPI3_MISO_BIT_FULL 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif +// SPI3_MOSI Pin <0=>Not Used <1=>PC12 +#define RTE_SPI3_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI3_MOSI_FULL 0 +#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI3_MOSI_FULL 1 +#define RTE_SPI3_MOSI_PORT_FULL GPIOC +#define RTE_SPI3_MOSI_BIT_FULL 12 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI3_REMAP) +#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL +#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL +#else +#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF +#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 0 +#define RTE_SPI3_RX_DMA_NUMBER 2 +#define RTE_SPI3_RX_DMA_CHANNEL 1 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 0 +#define RTE_SPI3_TX_DMA_NUMBER 2 +#define RTE_SPI3_TX_DMA_CHANNEL 2 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SDIO (Secure Digital Input/Output) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI +#define RTE_SDIO 0 + +// SDIO Peripheral Bus +// SDIO_CK Pin <0=>PC12 +#define RTE_SDIO_CK_PORT_ID 0 +#if (RTE_SDIO_CK_PORT_ID == 0) + #define RTE_SDIO_CK_PORT GPIOC + #define RTE_SDIO_CK_PIN 12 +#else + #error "Invalid SDIO_CLK Pin Configuration!" +#endif +// SDIO_CMD Pin <0=>PD2 +#define RTE_SDIO_CMD_PORT_ID 0 +#if (RTE_SDIO_CMD_PORT_ID == 0) + #define RTE_SDIO_CMD_PORT GPIOD + #define RTE_SDIO_CMD_PIN 2 +#else + #error "Invalid SDIO_CMD Pin Configuration!" +#endif +// SDIO_D0 Pin <0=>PC8 +#define RTE_SDIO_D0_PORT_ID 0 +#if (RTE_SDIO_D0_PORT_ID == 0) + #define RTE_SDIO_D0_PORT GPIOC + #define RTE_SDIO_D0_PIN 8 +#else + #error "Invalid SDIO_DAT0 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +#define RTE_SDIO_BUS_WIDTH_4 1 +// SDIO_D1 Pin <0=>PC9 +#define RTE_SDIO_D1_PORT_ID 0 +#if (RTE_SDIO_D1_PORT_ID == 0) + #define RTE_SDIO_D1_PORT GPIOC + #define RTE_SDIO_D1_PIN 9 +#else + #error "Invalid SDIO_D1 Pin Configuration!" +#endif +// SDIO_D2 Pin <0=>PC10 +#define RTE_SDIO_D2_PORT_ID 0 +#if (RTE_SDIO_D2_PORT_ID == 0) + #define RTE_SDIO_D2_PORT GPIOC + #define RTE_SDIO_D2_PIN 10 +#else + #error "Invalid SDIO_D2 Pin Configuration!" +#endif +// SDIO_D3 Pin <0=>PC11 +#define RTE_SDIO_D3_PORT_ID 0 +#if (RTE_SDIO_D3_PORT_ID == 0) + #define RTE_SDIO_D3_PORT GPIOC + #define RTE_SDIO_D3_PIN 11 +#else + #error "Invalid SDIO_D3 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +// SDIO_D[4 .. 7] +#define RTE_SDIO_BUS_WIDTH_8 0 +// SDIO_D4 Pin <0=>PB8 +#define RTE_SDIO_D4_PORT_ID 0 +#if (RTE_SDIO_D4_PORT_ID == 0) + #define RTE_SDIO_D4_PORT GPIOB + #define RTE_SDIO_D4_PIN 8 +#else + #error "Invalid SDIO_D4 Pin Configuration!" +#endif +// SDIO_D5 Pin <0=>PB9 +#define RTE_SDIO_D5_PORT_ID 0 +#if (RTE_SDIO_D5_PORT_ID == 0) + #define RTE_SDIO_D5_PORT GPIOB + #define RTE_SDIO_D5_PIN 9 +#else + #error "Invalid SDIO_D5 Pin Configuration!" +#endif +// SDIO_D6 Pin <0=>PC6 +#define RTE_SDIO_D6_PORT_ID 0 +#if (RTE_SDIO_D6_PORT_ID == 0) + #define RTE_SDIO_D6_PORT GPIOC + #define RTE_SDIO_D6_PIN 6 +#else + #error "Invalid SDIO_D6 Pin Configuration!" +#endif +// SDIO_D7 Pin <0=>PC7 +#define RTE_SDIO_D7_PORT_ID 0 +#if (RTE_SDIO_D7_PORT_ID == 0) + #define RTE_SDIO_D7_PORT GPIOC + #define RTE_SDIO_D7_PIN 7 +#else + #error "Invalid SDIO_D7 Pin Configuration!" +#endif +// SDIO_D[4 .. 7] +// SDIO Peripheral Bus + +// Card Detect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_CD_EN 1 +#define RTE_SDIO_CD_ACTIVE 0 +#define RTE_SDIO_CD_PORT GPIO_PORT(5) +#define RTE_SDIO_CD_PIN 11 + +// Write Protect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_WP_EN 0 +#define RTE_SDIO_WP_ACTIVE 1 +#define RTE_SDIO_WP_PORT GPIO_PORT(0) +#define RTE_SDIO_WP_PIN 10 + +// DMA +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_DMA_NUMBER 2 +#define RTE_SDIO_DMA_CHANNEL 4 +#define RTE_SDIO_DMA_PRIORITY 0 + +// + + +// CAN1 (Controller Area Network 1) [Driver_CAN1] +// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN +#define RTE_CAN1 0 + +// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 +#define RTE_CAN1_RX_PORT_ID 0 +#if (RTE_CAN1_RX_PORT_ID == 0) +#define RTE_CAN1_RX_PORT GPIOA +#define RTE_CAN1_RX_BIT 11 +#elif (RTE_CAN1_RX_PORT_ID == 1) +#define RTE_CAN1_RX_PORT GPIOB +#define RTE_CAN1_RX_BIT 8 +#elif (RTE_CAN1_RX_PORT_ID == 2) +#define RTE_CAN1_RX_PORT GPIOD +#define RTE_CAN1_RX_BIT 0 +#else +#error "Invalid CAN1_RX Pin Configuration!" +#endif + +// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 +#define RTE_CAN1_TX_PORT_ID 0 +#if (RTE_CAN1_TX_PORT_ID == 0) +#define RTE_CAN1_TX_PORT GPIOA +#define RTE_CAN1_TX_BIT 12 +#elif (RTE_CAN1_TX_PORT_ID == 1) +#define RTE_CAN1_TX_PORT GPIOB +#define RTE_CAN1_TX_BIT 9 +#elif (RTE_CAN1_TX_PORT_ID == 2) +#define RTE_CAN1_TX_PORT GPIOD +#define RTE_CAN1_TX_BIT 1 +#else +#error "Invalid CAN1_TX Pin Configuration!" +#endif + +// + + +// CAN2 (Controller Area Network 2) [Driver_CAN2] +// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN +#define RTE_CAN2 0 + +// CAN2_RX Pin <0=>PB5 <1=>PB12 +#define RTE_CAN2_RX_PORT_ID 0 +#if (RTE_CAN2_RX_PORT_ID == 0) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 5 +#elif (RTE_CAN2_RX_PORT_ID == 1) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 12 +#else +#error "Invalid CAN2_RX Pin Configuration!" +#endif + +// CAN2_TX Pin <0=>PB6 <1=>PB13 +#define RTE_CAN2_TX_PORT_ID 0 +#if (RTE_CAN2_TX_PORT_ID == 0) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 6 +#elif (RTE_CAN2_TX_PORT_ID == 1) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 13 +#else +#error "Invalid CAN2_TX Pin Configuration!" +#endif + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC +#define RTE_ETH 0 + +// MII (Media Independent Interface) +// Enable Media Independent Interface pin configuration +#define RTE_ETH_MII 0 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_DEF 0 + +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_DEF 0 + +// ETH_MII_RXD2 Pin <0=>PB0 +#define RTE_ETH_MII_RXD2_DEF 0 + +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12 +#define RTE_ETH_MII_RXD3_DEF 0 + +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_DEF 0 + +// ETH_MII_RX_ER Pin <0=>PB10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>PA0 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>PA3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_MII_REMAP 0 + +// ETH_MII_RXD0 Pin <1=>PD9 +#define RTE_ETH_MII_RXD0_REMAP 1 + +// ETH_MII_RXD1 Pin <1=>PD10 +#define RTE_ETH_MII_RXD1_REMAP 1 + +// ETH_MII_RXD2 Pin <1=>PD11 +#define RTE_ETH_MII_RXD2_REMAP 1 + +// ETH_MII_RXD3 Pin <1=>PD12 +#define RTE_ETH_MII_RXD3_REMAP 1 + +// ETH_MII_RX_DV Pin <1=>PD8 +#define RTE_ETH_MII_RX_DV_REMAP 1 +// + +// + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0)) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1)) +#define RTE_ETH_MII_RXD0_PORT GPIOD +#define RTE_ETH_MII_RXD0_PIN 9 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0)) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1)) +#define RTE_ETH_MII_RXD1_PORT GPIOD +#define RTE_ETH_MII_RXD1_PIN 10 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0)) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1)) +#define RTE_ETH_MII_RXD2_PORT GPIOD +#define RTE_ETH_MII_RXD2_PIN 11 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0)) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1)) +#define RTE_ETH_MII_RXD3_PORT GPIOD +#define RTE_ETH_MII_RXD3_PIN 12 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0)) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1)) +#define RTE_ETH_MII_RX_DV_PORT GPIOD +#define RTE_ETH_MII_RX_DV_PIN 8 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 0 + +// ETH_RMII_TXD0 Pin <0=>PB12 +#define RTE_ETH_RMII_TXD0_PORT_ID 0 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 +#define RTE_ETH_RMII_TXD1_PORT_ID 0 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 0 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_DEF 0 + +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_DEF 0 + +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_DEF 0 + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_RMII_REMAP 0 +// ETH_RMII_RXD0 Pin <1=>PD9 +#define RTE_ETH_RMII_RXD0_REMAP 1 + +// ETH_RMII_RXD1 Pin <1=>PD10 +#define RTE_ETH_RMII_RXD1_REMAP 1 + +// ETH_RMII_CRS_DV Pin <1=>PD8 +#define RTE_ETH_RMII_CRS_DV_REMAP 1 +// + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0)) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1)) +#define RTE_ETH_RMII_RXD0_PORT GPIOD +#define RTE_ETH_RMII_RXD0_PIN 9 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0)) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1)) +#define RTE_ETH_RMII_RXD1_PORT GPIOD +#define RTE_ETH_RMII_RXD1_PIN 10 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOD +#define RTE_ETH_RMII_CRS_DV_PIN 8 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// Management Data Interface +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_MDI_MDC_PORT_ID 0 +#if (RTE_ETH_MDI_MDC_PORT_ID == 0) +#define RTE_ETH_MDI_MDC_PORT GPIOC +#define RTE_ETH_MDI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_MDI_MDIO_PORT_ID 0 +#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) +#define RTE_ETH_MDI_MDIO_PORT GPIOA +#define RTE_ETH_MDI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled +#define RTE_ETH_REF_CLOCK_ID 0 +#if (RTE_ETH_REF_CLOCK_ID == 0) +#define RTE_ETH_REF_CLOCK 0 +#elif (RTE_ETH_REF_CLOCK_ID == 1) +#define RTE_ETH_REF_CLOCK 1 +#else +#error "Invalid MCO Ethernet Reference Clock Configuration!" +#endif +// + + +// USB Device Full-speed +// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device +#define RTE_USB_DEVICE 0 + +// CON On/Off Pin +// Configure Pin for driving D+ pull-up +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_USB_DEVICE_CON_PIN 1 +#define RTE_USB_DEVICE_CON_ACTIVE 0 +#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1) +#define RTE_USB_DEVICE_CON_BIT 14 + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host + +#define RTE_USB_OTG_FS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 1 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2) +#define RTE_OTG_FS_VBUS_BIT 9 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 1 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(4) +#define RTE_OTG_FS_OC_BIT 1 +// + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/RTE/Device/STM32F107VC/startup_stm32f10x_cl.s.update@1.0.1 b/RTE/Device/STM32F107VC/startup_stm32f10x_cl.s.update@1.0.1 new file mode 100644 index 0000000..e40f734 --- /dev/null +++ b/RTE/Device/STM32F107VC/startup_stm32f10x_cl.s.update@1.0.1 @@ -0,0 +1,369 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_cl.s +;* Author : MCD Application Team +;* Version : V3.5.1 +;* Date : 08-September-2021 +;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Copyright (c) 2011 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C1 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/RTE/Device/STM32F107VC/system_stm32f10x.c.update@1.0.1 b/RTE/Device/STM32F107VC/system_stm32f10x.c.update@1.0.1 new file mode 100644 index 0000000..9e31f67 --- /dev/null +++ b/RTE/Device/STM32F107VC/system_stm32f10x.c.update@1.0.1 @@ -0,0 +1,1092 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.5.1 + * @date 08-September-2021 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2011 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depending on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */