diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..adf9980
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,31 @@
+*.obj
+*.o
+*.bin
+*.list
+*.map
+*.mk
+*.makefile
+*.o
+*.su
+*.d
+*.elf
+*.scvd
+*.crf
+*.map
+*.sct
+*.dbgconf
+*.axf
+*.htm
+*.lnp
+*.dep
+*.uvguix.*
+*.lst
+*.iex
+**/Objects/
+**/Listings/
+**/Debug/
+.obsidian
+
+
+
+
diff --git a/DebugConfig/R_el_STM32F107VC_1.0.0.dbgconf b/DebugConfig/R_el_STM32F107VC_1.0.0.dbgconf
deleted file mode 100644
index 90dabd8..0000000
--- a/DebugConfig/R_el_STM32F107VC_1.0.0.dbgconf
+++ /dev/null
@@ -1,97 +0,0 @@
-// <<< Use Configuration Wizard in Context Menu >>>
-// <h> Debug MCU Configuration
-//   <o0.0>    DBG_SLEEP
-// <i> Debug Sleep Mode
-// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
-// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
-//   <o0.1>    DBG_STOP
-// <i> Debug Stop Mode
-// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
-// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
-//   <o0.2>    DBG_STANDBY
-// <i> Debug Standby Mode
-// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
-// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
-//   <o0.8>    DBG_IWDG_STOP
-// <i> Debug independent watchdog stopped when core is halted
-// <i> 0: The watchdog counter clock continues even if the core is halted
-// <i> 1: The watchdog counter clock is stopped when the core is halted
-//   <o0.9>    DBG_WWDG_STOP
-// <i> Debug window watchdog stopped when core is halted
-// <i> 0: The window watchdog counter clock continues even if the core is halted
-// <i> 1: The window watchdog counter clock is stopped when the core is halted
-//   <o0.10>   DBG_TIM1_STOP
-// <i> Timer 1 counter stopped when core is halted
-// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
-// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
-//   <o0.11>   DBG_TIM2_STOP
-// <i> Timer 2 counter stopped when core is halted
-// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
-// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
-//   <o0.12>   DBG_TIM3_STOP
-// <i> Timer 3 counter stopped when core is halted
-// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
-// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
-//   <o0.13>   DBG_TIM4_STOP
-// <i> Timer 4 counter stopped when core is halted
-// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
-// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
-//   <o0.14>   DBG_CAN1_STOP
-// <i> Debug CAN1 stopped when Core is halted
-// <i> 0: Same behavior as in normal mode
-// <i> 1: CAN1 receive registers are frozen
-//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
-// <i> I2C1 SMBUS timeout mode stopped when Core is halted
-// <i> 0: Same behavior as in normal mode
-// <i> 1: The SMBUS timeout is frozen
-//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
-// <i> I2C2 SMBUS timeout mode stopped when Core is halted
-// <i> 0: Same behavior as in normal mode
-// <i> 1: The SMBUS timeout is frozen
-//   <o0.17>   DBG_TIM8_STOP
-// <i> Timer 8 counter stopped when core is halted
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
-//   <o0.18>   DBG_TIM5_STOP
-// <i> Timer 5 counter stopped when core is halted
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
-//   <o0.19>   DBG_TIM6_STOP
-// <i> Timer 6 counter stopped when core is halted
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
-//   <o0.20>   DBG_TIM7_STOP
-// <i> Timer 7 counter stopped when core is halted
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
-//   <o0.21>   DBG_CAN2_STOP
-// <i> Debug CAN2 stopped when Core is halted
-// <i> 0: Same behavior as in normal mode
-// <i> 1: CAN2 receive registers are frozen
-//   <o0.25>   DBG_TIM12_STOP
-// <i> Timer 12 counter stopped when core is halted
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
-//   <o0.26>   DBG_TIM13_STOP
-// <i> Timer 13 counter stopped when core is halted
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
-//   <o0.27>   DBG_TIM14_STOP
-// <i> Timer 14 counter stopped when core is halted
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
-//   <o0.28>   DBG_TIM9_STOP
-// <i> Timer 9 counter stopped when core is halted
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
-//   <o0.29>   DBG_TIM10_STOP
-// <i> Timer 10 counter stopped when core is halted
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
-//   <o0.30>   DBG_TIM11_STOP
-// <i> Timer 11 counter stopped when core is halted
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
-// </h>
-DbgMCU_CR = 0x00000007;
-// <<< end of configuration section >>>
\ No newline at end of file
diff --git a/DebugConfig/Simul__STM32F103RB_1.0.0.dbgconf b/DebugConfig/Simul__STM32F103RB_1.0.0.dbgconf
deleted file mode 100644
index 90dabd8..0000000
--- a/DebugConfig/Simul__STM32F103RB_1.0.0.dbgconf
+++ /dev/null
@@ -1,97 +0,0 @@
-// <<< Use Configuration Wizard in Context Menu >>>
-// <h> Debug MCU Configuration
-//   <o0.0>    DBG_SLEEP
-// <i> Debug Sleep Mode
-// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
-// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
-//   <o0.1>    DBG_STOP
-// <i> Debug Stop Mode
-// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
-// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
-//   <o0.2>    DBG_STANDBY
-// <i> Debug Standby Mode
-// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
-// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
-//   <o0.8>    DBG_IWDG_STOP
-// <i> Debug independent watchdog stopped when core is halted
-// <i> 0: The watchdog counter clock continues even if the core is halted
-// <i> 1: The watchdog counter clock is stopped when the core is halted
-//   <o0.9>    DBG_WWDG_STOP
-// <i> Debug window watchdog stopped when core is halted
-// <i> 0: The window watchdog counter clock continues even if the core is halted
-// <i> 1: The window watchdog counter clock is stopped when the core is halted
-//   <o0.10>   DBG_TIM1_STOP
-// <i> Timer 1 counter stopped when core is halted
-// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
-// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
-//   <o0.11>   DBG_TIM2_STOP
-// <i> Timer 2 counter stopped when core is halted
-// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
-// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
-//   <o0.12>   DBG_TIM3_STOP
-// <i> Timer 3 counter stopped when core is halted
-// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
-// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
-//   <o0.13>   DBG_TIM4_STOP
-// <i> Timer 4 counter stopped when core is halted
-// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
-// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
-//   <o0.14>   DBG_CAN1_STOP
-// <i> Debug CAN1 stopped when Core is halted
-// <i> 0: Same behavior as in normal mode
-// <i> 1: CAN1 receive registers are frozen
-//   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
-// <i> I2C1 SMBUS timeout mode stopped when Core is halted
-// <i> 0: Same behavior as in normal mode
-// <i> 1: The SMBUS timeout is frozen
-//   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
-// <i> I2C2 SMBUS timeout mode stopped when Core is halted
-// <i> 0: Same behavior as in normal mode
-// <i> 1: The SMBUS timeout is frozen
-//   <o0.17>   DBG_TIM8_STOP
-// <i> Timer 8 counter stopped when core is halted
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
-//   <o0.18>   DBG_TIM5_STOP
-// <i> Timer 5 counter stopped when core is halted
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
-//   <o0.19>   DBG_TIM6_STOP
-// <i> Timer 6 counter stopped when core is halted
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
-//   <o0.20>   DBG_TIM7_STOP
-// <i> Timer 7 counter stopped when core is halted
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
-//   <o0.21>   DBG_CAN2_STOP
-// <i> Debug CAN2 stopped when Core is halted
-// <i> 0: Same behavior as in normal mode
-// <i> 1: CAN2 receive registers are frozen
-//   <o0.25>   DBG_TIM12_STOP
-// <i> Timer 12 counter stopped when core is halted
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
-//   <o0.26>   DBG_TIM13_STOP
-// <i> Timer 13 counter stopped when core is halted
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
-//   <o0.27>   DBG_TIM14_STOP
-// <i> Timer 14 counter stopped when core is halted
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
-//   <o0.28>   DBG_TIM9_STOP
-// <i> Timer 9 counter stopped when core is halted
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
-//   <o0.29>   DBG_TIM10_STOP
-// <i> Timer 10 counter stopped when core is halted
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
-//   <o0.30>   DBG_TIM11_STOP
-// <i> Timer 11 counter stopped when core is halted
-// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
-// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
-// </h>
-DbgMCU_CR = 0x00000007;
-// <<< end of configuration section >>>
\ No newline at end of file
diff --git a/Etape_1.uvguix.boujon b/Etape_1.uvguix.boujon
deleted file mode 100644
index b339d3c..0000000
--- a/Etape_1.uvguix.boujon
+++ /dev/null
@@ -1,1896 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<ProjectGui xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_guix.xsd">
-
-  <SchemaVersion>-6.1</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <PrjGuiSettings>
-    <LastAddFilePath></LastAddFilePath>
-  </PrjGuiSettings>
-
-  <ViewPool/>
-
-  <SECTreeCtrl>
-    <View>
-      <WinId>38003</WinId>
-      <ViewName>Registers</ViewName>
-      <TableColWidths>140 90</TableColWidths>
-    </View>
-    <View>
-      <WinId>346</WinId>
-      <ViewName>Code Coverage</ViewName>
-      <TableColWidths>1010 160</TableColWidths>
-    </View>
-    <View>
-      <WinId>204</WinId>
-      <ViewName>Performance Analyzer</ViewName>
-      <TableColWidths>1170</TableColWidths>
-    </View>
-  </SECTreeCtrl>
-
-  <TreeListPane>
-    <View>
-      <WinId>35141</WinId>
-      <ViewName>Event Statistics</ViewName>
-      <UserString></UserString>
-      <TableColWidths>200 50 700</TableColWidths>
-    </View>
-    <View>
-      <WinId>1506</WinId>
-      <ViewName>Symbols</ViewName>
-      <UserString></UserString>
-      <TableColWidths>80 80 80</TableColWidths>
-    </View>
-    <View>
-      <WinId>1936</WinId>
-      <ViewName>Watch 1</ViewName>
-      <UserString></UserString>
-      <TableColWidths>200 133 133</TableColWidths>
-    </View>
-    <View>
-      <WinId>1937</WinId>
-      <ViewName>Watch 2</ViewName>
-      <UserString></UserString>
-      <TableColWidths>200 133 133</TableColWidths>
-    </View>
-    <View>
-      <WinId>1935</WinId>
-      <ViewName>Call Stack + Locals</ViewName>
-      <UserString></UserString>
-      <TableColWidths>200 133 133</TableColWidths>
-    </View>
-    <View>
-      <WinId>2506</WinId>
-      <ViewName>Trace Data</ViewName>
-      <UserString></UserString>
-      <TableColWidths>75 135 130 95 70 230 200 150</TableColWidths>
-    </View>
-    <View>
-      <WinId>466</WinId>
-      <ViewName>Source Browser</ViewName>
-      <UserString>500</UserString>
-      <TableColWidths>300</TableColWidths>
-    </View>
-  </TreeListPane>
-
-  <CompViewPool/>
-
-  <WindowSettings>
-    <LogicAnalizer>
-      <ShowLACursor>1</ShowLACursor>
-      <ShowSignalInfo>1</ShowSignalInfo>
-      <ShowCycles>0</ShowCycles>
-      <LeftSideBarSize>0</LeftSideBarSize>
-      <TimeBaseIndex>-1</TimeBaseIndex>
-    </LogicAnalizer>
-  </WindowSettings>
-
-  <WinLayoutEx>
-    <sActiveDebugView></sActiveDebugView>
-    <WindowPosition>
-      <length>44</length>
-      <flags>2</flags>
-      <showCmd>3</showCmd>
-      <MinPosition>
-        <xPos>-1</xPos>
-        <yPos>-1</yPos>
-      </MinPosition>
-      <MaxPosition>
-        <xPos>-1</xPos>
-        <yPos>-1</yPos>
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-      <NormalPosition>
-        <Top>52</Top>
-        <Left>52</Left>
-        <Right>1492</Right>
-        <Bottom>811</Bottom>
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-    <ViewEx>
-      <ViewType>0</ViewType>
-      <ViewName>Build</ViewName>
-      <Window>
-        <RegID>-1</RegID>
-        <PaneID>-1</PaneID>
-        <IsVisible>0</IsVisible>
-        <IsFloating>0</IsFloating>
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-        <PaneID>1465</PaneID>
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+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>0</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>0</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+      <DebugDescription>
+        <Enable>1</Enable>
+        <EnableFlashSeq>1</EnableFlashSeq>
+        <EnableLog>0</EnableLog>
+        <Protocol>2</Protocol>
+        <DbgClock>10000000</DbgClock>
+      </DebugDescription>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>Réel</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>0</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\Listings\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>0</CpuCode>
+      <DebugOpt>
+        <uSim>1</uSim>
+        <uTrg>0</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>0</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>-1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon></pMon>
+      </DebugOpt>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>Application</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>2</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\Principale.asm</PathWithFileName>
+      <FilenameWithoutPath>Principale.asm</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>2</FileNumber>
+      <FileType>2</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\FonctionEtape.asm</PathWithFileName>
+      <FilenameWithoutPath>FonctionEtape.asm</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>3</FileNumber>
+      <FileType>2</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\FonctionEtape2.asm</PathWithFileName>
+      <FilenameWithoutPath>FonctionEtape2.asm</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Pilote</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>4</FileNumber>
+      <FileType>4</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\Matos.lib</PathWithFileName>
+      <FilenameWithoutPath>Matos.lib</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>::CMSIS</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+  <Group>
+    <GroupName>::Device</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+</ProjectOpt>
diff --git a/Etape_1.uvprojx b/Etape_2.uvprojx
similarity index 97%
rename from Etape_1.uvprojx
rename to Etape_2.uvprojx
index e7b567c..819b966 100644
--- a/Etape_1.uvprojx
+++ b/Etape_2.uvprojx
@@ -10,8 +10,8 @@
       <TargetName>Simulé</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
-      <pCCUsed>5060528::V5.06 update 5 (build 528)::ARMCC</pCCUsed>
-      <uAC6>0</uAC6>
+      <pCCUsed>6160000::V6.16::ARMCLANG</pCCUsed>
+      <uAC6>1</uAC6>
       <TargetOption>
         <TargetCommonOption>
           <Device>STM32F103RB</Device>
@@ -313,7 +313,7 @@
           </ArmAdsMisc>
           <Cads>
             <interw>1</interw>
-            <Optim>1</Optim>
+            <Optim>2</Optim>
             <oTime>0</oTime>
             <SplitLS>0</SplitLS>
             <OneElfS>1</OneElfS>
@@ -322,14 +322,14 @@
             <PlainCh>0</PlainCh>
             <Ropi>0</Ropi>
             <Rwpi>0</Rwpi>
-            <wLevel>2</wLevel>
+            <wLevel>3</wLevel>
             <uThumb>0</uThumb>
             <uSurpInc>0</uSurpInc>
             <uC99>1</uC99>
             <uGnu>0</uGnu>
             <useXO>0</useXO>
-            <v6Lang>1</v6Lang>
-            <v6LangP>1</v6LangP>
+            <v6Lang>3</v6Lang>
+            <v6LangP>5</v6LangP>
             <vShortEn>1</vShortEn>
             <vShortWch>1</vShortWch>
             <v6Lto>0</v6Lto>
@@ -393,6 +393,11 @@
               <FileType>2</FileType>
               <FilePath>.\FonctionEtape.asm</FilePath>
             </File>
+            <File>
+              <FileName>FonctionEtape2.asm</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\FonctionEtape2.asm</FilePath>
+            </File>
           </Files>
         </Group>
         <Group>
@@ -417,7 +422,7 @@
       <TargetName>Réel</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
-      <pCCUsed>5060528::V5.06 update 5 (build 528)::ARMCC</pCCUsed>
+      <pCCUsed>5060960::V5.06 update 7 (build 960)::.\ARMCC</pCCUsed>
       <uAC6>0</uAC6>
       <TargetOption>
         <TargetCommonOption>
@@ -800,6 +805,11 @@
               <FileType>2</FileType>
               <FilePath>.\FonctionEtape.asm</FilePath>
             </File>
+            <File>
+              <FileName>FonctionEtape2.asm</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\FonctionEtape2.asm</FilePath>
+            </File>
           </Files>
         </Group>
         <Group>
@@ -825,15 +835,15 @@
   <RTE>
     <apis/>
     <components>
-      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.1" condition="ARMv6_7_8-M Device">
-        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.1"/>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
         <targetInfos>
           <targetInfo name="Réel"/>
           <targetInfo name="Simulé"/>
         </targetInfos>
       </component>
       <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="STM32F1xx CMSIS">
-        <package name="STM32F1xx_DFP" schemaVersion="1.4.0" url="http://www.keil.com/pack/" vendor="Keil" version="2.2.0"/>
+        <package name="STM32F1xx_DFP" schemaVersion="1.7.2" url="http://www.keil.com/pack/" vendor="Keil" version="2.4.0"/>
         <targetInfos>
           <targetInfo name="Réel"/>
           <targetInfo name="Simulé"/>
diff --git a/Etape_1.uvoptx b/Etape_3.uvoptx
similarity index 72%
rename from Etape_1.uvoptx
rename to Etape_3.uvoptx
index 06d0ccf..766fd34 100644
--- a/Etape_1.uvoptx
+++ b/Etape_3.uvoptx
@@ -75,7 +75,7 @@
       <OPTFL>
         <tvExp>1</tvExp>
         <tvExpOptDlg>0</tvExpOptDlg>
-        <IsCurrentTarget>0</IsCurrentTarget>
+        <IsCurrentTarget>1</IsCurrentTarget>
       </OPTFL>
       <CpuCode>18</CpuCode>
       <DebugOpt>
@@ -125,7 +125,7 @@
         <SetRegEntry>
           <Number>0</Number>
           <Key>DLGDARM</Key>
-          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=15,39,661,712,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=1148,258,1639,750,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
+          <Name>(1010=1003,355,1379,912,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=15,39,661,712,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=1462,180,1883,607,1)(121=1499,392,1920,819,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=1088,133,1682,884,1)(131=255,99,849,850,0)(132=49,93,643,844,0)(133=867,101,1461,852,1)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
         </SetRegEntry>
         <SetRegEntry>
           <Number>0</Number>
@@ -142,89 +142,25 @@
         <Bp>
           <Number>0</Number>
           <Type>0</Type>
-          <LineNumber>47</LineNumber>
+          <LineNumber>106</LineNumber>
           <EnabledFlag>1</EnabledFlag>
-          <Address>0</Address>
+          <Address>134223108</Address>
           <ByteObject>0</ByteObject>
           <HtxType>0</HtxType>
           <ManyObjects>0</ManyObjects>
           <SizeOfObject>0</SizeOfObject>
           <BreakByAccess>0</BreakByAccess>
-          <BreakIfRCount>0</BreakIfRCount>
-          <Filename>.\Principale.asm</Filename>
+          <BreakIfRCount>1</BreakIfRCount>
+          <Filename>.\FonctionEtape3.asm</Filename>
           <ExecCommand></ExecCommand>
-          <Expression></Expression>
-        </Bp>
-        <Bp>
-          <Number>1</Number>
-          <Type>0</Type>
-          <LineNumber>49</LineNumber>
-          <EnabledFlag>1</EnabledFlag>
-          <Address>0</Address>
-          <ByteObject>0</ByteObject>
-          <HtxType>0</HtxType>
-          <ManyObjects>0</ManyObjects>
-          <SizeOfObject>0</SizeOfObject>
-          <BreakByAccess>0</BreakByAccess>
-          <BreakIfRCount>0</BreakIfRCount>
-          <Filename>.\Principale.asm</Filename>
-          <ExecCommand></ExecCommand>
-          <Expression></Expression>
-        </Bp>
-        <Bp>
-          <Number>2</Number>
-          <Type>0</Type>
-          <LineNumber>50</LineNumber>
-          <EnabledFlag>1</EnabledFlag>
-          <Address>0</Address>
-          <ByteObject>0</ByteObject>
-          <HtxType>0</HtxType>
-          <ManyObjects>0</ManyObjects>
-          <SizeOfObject>0</SizeOfObject>
-          <BreakByAccess>0</BreakByAccess>
-          <BreakIfRCount>0</BreakIfRCount>
-          <Filename>.\Principale.asm</Filename>
-          <ExecCommand></ExecCommand>
-          <Expression></Expression>
-        </Bp>
-        <Bp>
-          <Number>3</Number>
-          <Type>0</Type>
-          <LineNumber>51</LineNumber>
-          <EnabledFlag>1</EnabledFlag>
-          <Address>0</Address>
-          <ByteObject>0</ByteObject>
-          <HtxType>0</HtxType>
-          <ManyObjects>0</ManyObjects>
-          <SizeOfObject>0</SizeOfObject>
-          <BreakByAccess>0</BreakByAccess>
-          <BreakIfRCount>0</BreakIfRCount>
-          <Filename>.\Principale.asm</Filename>
-          <ExecCommand></ExecCommand>
-          <Expression></Expression>
-        </Bp>
-        <Bp>
-          <Number>4</Number>
-          <Type>0</Type>
-          <LineNumber>52</LineNumber>
-          <EnabledFlag>1</EnabledFlag>
-          <Address>0</Address>
-          <ByteObject>0</ByteObject>
-          <HtxType>0</HtxType>
-          <ManyObjects>0</ManyObjects>
-          <SizeOfObject>0</SizeOfObject>
-          <BreakByAccess>0</BreakByAccess>
-          <BreakIfRCount>0</BreakIfRCount>
-          <Filename>.\Principale.asm</Filename>
-          <ExecCommand></ExecCommand>
-          <Expression></Expression>
+          <Expression>\\Simu_Etape0\FonctionEtape3.asm\106</Expression>
         </Bp>
       </Breakpoint>
       <MemoryWindow1>
         <Mm>
           <WinNumber>1</WinNumber>
           <SubType>0</SubType>
-          <ItemText>0x20000000</ItemText>
+          <ItemText>0x08001650</ItemText>
           <AccSizeX>0</AccSizeX>
         </Mm>
       </MemoryWindow1>
@@ -245,7 +181,7 @@
       </Tracepoint>
       <DebugFlag>
         <trace>0</trace>
-        <periodic>0</periodic>
+        <periodic>1</periodic>
         <aLwin>1</aLwin>
         <aCover>0</aCover>
         <aSer1>0</aSer1>
@@ -254,7 +190,7 @@
         <viewmode>1</viewmode>
         <vrSel>0</vrSel>
         <aSym>0</aSym>
-        <aTbox>0</aTbox>
+        <aTbox>1</aTbox>
         <AscS1>0</AscS1>
         <AscS2>0</AscS2>
         <AscS3>0</AscS3>
@@ -282,6 +218,18 @@
       <pszMrulep></pszMrulep>
       <pSingCmdsp></pSingCmdsp>
       <pMultCmdsp></pMultCmdsp>
+      <LogicAnalyzers>
+        <Wi>
+          <IntNumber>0</IntNumber>
+          <FirstString>(portA &amp; 0x20 &amp; 0x20) &gt;&gt; 0</FirstString>
+          <SecondString>FF000000000000000000000000000000E0FFEF4001000000000000000000000000000000706F72744120262030783230000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000001984C7ED33DFE33F1500000000000000000000000000000000000000E4120008</SecondString>
+        </Wi>
+        <Wi>
+          <IntNumber>1</IntNumber>
+          <FirstString>(portA &amp; 0x80 &amp; 0x80) &gt;&gt; 0</FirstString>
+          <SecondString>00800000000000000000000000000000E0FFEF4001000000000000000000000000000000706F7274412026203078383000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000002000000CDF770249841D83F150000000000000000000000000000000000000062120008</SecondString>
+        </Wi>
+      </LogicAnalyzers>
       <DebugDescription>
         <Enable>1</Enable>
         <EnableFlashSeq>0</EnableFlashSeq>
@@ -346,7 +294,7 @@
       <OPTFL>
         <tvExp>1</tvExp>
         <tvExpOptDlg>0</tvExpOptDlg>
-        <IsCurrentTarget>1</IsCurrentTarget>
+        <IsCurrentTarget>0</IsCurrentTarget>
       </OPTFL>
       <CpuCode>18</CpuCode>
       <DebugOpt>
@@ -411,46 +359,30 @@
         <SetRegEntry>
           <Number>0</Number>
           <Key>UL2CM3</Key>
-          <Name>-UAny -O206 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_CL.FLM -FS08000000 -FL080000 -FP0($$Device:STM32F107VC$Flash\STM32F10x_CL.FLM)</Name>
+          <Name>-UAny -O206 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_CL.FLM -FS08000000 -FL080000 -FP0($$Device:STM32F107VC$Flash\STM32F10x_CL.FLM)</Name>
         </SetRegEntry>
       </TargetDriverDllRegistry>
       <Breakpoint>
         <Bp>
           <Number>0</Number>
           <Type>0</Type>
-          <LineNumber>51</LineNumber>
+          <LineNumber>106</LineNumber>
           <EnabledFlag>1</EnabledFlag>
-          <Address>134222552</Address>
+          <Address>0</Address>
           <ByteObject>0</ByteObject>
           <HtxType>0</HtxType>
           <ManyObjects>0</ManyObjects>
           <SizeOfObject>0</SizeOfObject>
           <BreakByAccess>0</BreakByAccess>
-          <BreakIfRCount>1</BreakIfRCount>
-          <Filename>.\Principale.asm</Filename>
+          <BreakIfRCount>0</BreakIfRCount>
+          <Filename>.\FonctionEtape3.asm</Filename>
           <ExecCommand></ExecCommand>
-          <Expression>\\Reel_Etape0\Principale.asm\51</Expression>
+          <Expression></Expression>
         </Bp>
         <Bp>
           <Number>1</Number>
           <Type>0</Type>
-          <LineNumber>50</LineNumber>
-          <EnabledFlag>1</EnabledFlag>
-          <Address>134222548</Address>
-          <ByteObject>0</ByteObject>
-          <HtxType>0</HtxType>
-          <ManyObjects>0</ManyObjects>
-          <SizeOfObject>0</SizeOfObject>
-          <BreakByAccess>0</BreakByAccess>
-          <BreakIfRCount>1</BreakIfRCount>
-          <Filename>.\Principale.asm</Filename>
-          <ExecCommand></ExecCommand>
-          <Expression>\\Reel_Etape0\Principale.asm\50</Expression>
-        </Bp>
-        <Bp>
-          <Number>2</Number>
-          <Type>0</Type>
-          <LineNumber>47</LineNumber>
+          <LineNumber>55</LineNumber>
           <EnabledFlag>1</EnabledFlag>
           <Address>0</Address>
           <ByteObject>0</ByteObject>
@@ -459,50 +391,26 @@
           <SizeOfObject>0</SizeOfObject>
           <BreakByAccess>0</BreakByAccess>
           <BreakIfRCount>0</BreakIfRCount>
-          <Filename>.\Principale.asm</Filename>
-          <ExecCommand></ExecCommand>
-          <Expression></Expression>
-        </Bp>
-        <Bp>
-          <Number>3</Number>
-          <Type>0</Type>
-          <LineNumber>49</LineNumber>
-          <EnabledFlag>1</EnabledFlag>
-          <Address>0</Address>
-          <ByteObject>0</ByteObject>
-          <HtxType>0</HtxType>
-          <ManyObjects>0</ManyObjects>
-          <SizeOfObject>0</SizeOfObject>
-          <BreakByAccess>0</BreakByAccess>
-          <BreakIfRCount>0</BreakIfRCount>
-          <Filename>.\Principale.asm</Filename>
-          <ExecCommand></ExecCommand>
-          <Expression></Expression>
-        </Bp>
-        <Bp>
-          <Number>4</Number>
-          <Type>0</Type>
-          <LineNumber>52</LineNumber>
-          <EnabledFlag>1</EnabledFlag>
-          <Address>0</Address>
-          <ByteObject>0</ByteObject>
-          <HtxType>0</HtxType>
-          <ManyObjects>0</ManyObjects>
-          <SizeOfObject>0</SizeOfObject>
-          <BreakByAccess>0</BreakByAccess>
-          <BreakIfRCount>0</BreakIfRCount>
-          <Filename>.\Principale.asm</Filename>
+          <Filename>.\FonctionEtape3.asm</Filename>
           <ExecCommand></ExecCommand>
           <Expression></Expression>
         </Bp>
       </Breakpoint>
+      <MemoryWindow1>
+        <Mm>
+          <WinNumber>1</WinNumber>
+          <SubType>0</SubType>
+          <ItemText>0x2000FFF0</ItemText>
+          <AccSizeX>0</AccSizeX>
+        </Mm>
+      </MemoryWindow1>
       <Tracepoint>
         <THDelay>0</THDelay>
       </Tracepoint>
       <DebugFlag>
         <trace>0</trace>
         <periodic>0</periodic>
-        <aLwin>1</aLwin>
+        <aLwin>0</aLwin>
         <aCover>0</aCover>
         <aSer1>0</aSer1>
         <aSer2>0</aSer2>
@@ -578,6 +486,42 @@
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>3</FileNumber>
+      <FileType>2</FileType>
+      <tvExp>1</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\FonctionEtape2.asm</PathWithFileName>
+      <FilenameWithoutPath>FonctionEtape2.asm</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>4</FileNumber>
+      <FileType>2</FileType>
+      <tvExp>1</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\FonctionEtape3.asm</PathWithFileName>
+      <FilenameWithoutPath>FonctionEtape3.asm</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>5</FileNumber>
+      <FileType>2</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\Mire.asm</PathWithFileName>
+      <FilenameWithoutPath>Mire.asm</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
   </Group>
 
   <Group>
@@ -588,7 +532,7 @@
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>2</GroupNumber>
-      <FileNumber>3</FileNumber>
+      <FileNumber>6</FileNumber>
       <FileType>4</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
diff --git a/Etape_3.uvprojx b/Etape_3.uvprojx
new file mode 100644
index 0000000..4f07e48
--- /dev/null
+++ b/Etape_3.uvprojx
@@ -0,0 +1,937 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>Simulé</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>6160000::V6.16::ARMCLANG</pCCUsed>
+      <uAC6>1</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32F103RB</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <PackID>Keil.STM32F1xx_DFP.2.3.0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x5000) IROM(0x08000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:STM32F103RB$Device\Include\stm32f10x.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:STM32F103RB$SVD\STM32F103xx.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>Simu_Etape0</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments> -REMAP</SimDllArguments>
+          <SimDlgDll>DARMSTM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pSTM32F103RB</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x5000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x20000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x5000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>2</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>3</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>5</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>STM32F10X_MD</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\pilotes\Include</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <ClangAsOpt>4</ClangAsOpt>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>STM32F10X_MD</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Application</GroupName>
+          <Files>
+            <File>
+              <FileName>Principale.asm</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\Principale.asm</FilePath>
+            </File>
+            <File>
+              <FileName>FonctionEtape.asm</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\FonctionEtape.asm</FilePath>
+            </File>
+            <File>
+              <FileName>FonctionEtape2.asm</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\FonctionEtape2.asm</FilePath>
+            </File>
+            <File>
+              <FileName>FonctionEtape3.asm</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\FonctionEtape3.asm</FilePath>
+            </File>
+            <File>
+              <FileName>Mire.asm</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\Mire.asm</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Pilote</GroupName>
+          <Files>
+            <File>
+              <FileName>Matos.lib</FileName>
+              <FileType>4</FileType>
+              <FilePath>.\Matos.lib</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+    <Target>
+      <TargetName>Réel</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060960::V5.06 update 7 (build 960)::.\ARMCC</pCCUsed>
+      <uAC6>0</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32F107VC</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <PackID>Keil.STM32F1xx_DFP.2.3.0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x10000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_CL -FS08000000 -FL080000 -FP0($$Device:STM32F107VC$Flash\STM32F10x_CL.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:STM32F107VC$Device\Include\stm32f10x.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:STM32F107VC$SVD\STM32F107xx.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>Reel_Etape0</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments> -REMAP</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>1</v6Lang>
+            <v6LangP>1</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>STM32F10X_CL</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\pilotes\Include</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <ClangAsOpt>4</ClangAsOpt>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>STM32F10X_CL</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Application</GroupName>
+          <Files>
+            <File>
+              <FileName>Principale.asm</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\Principale.asm</FilePath>
+            </File>
+            <File>
+              <FileName>FonctionEtape.asm</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\FonctionEtape.asm</FilePath>
+            </File>
+            <File>
+              <FileName>FonctionEtape2.asm</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\FonctionEtape2.asm</FilePath>
+            </File>
+            <File>
+              <FileName>FonctionEtape3.asm</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\FonctionEtape3.asm</FilePath>
+            </File>
+            <File>
+              <FileName>Mire.asm</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\Mire.asm</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Pilote</GroupName>
+          <Files>
+            <File>
+              <FileName>Matos.lib</FileName>
+              <FileType>4</FileType>
+              <FilePath>.\Matos.lib</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
+        <targetInfos>
+          <targetInfo name="Réel"/>
+          <targetInfo name="Simulé"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="STM32F1xx CMSIS">
+        <package name="STM32F1xx_DFP" schemaVersion="1.7.2" url="http://www.keil.com/pack/" vendor="Keil" version="2.4.0"/>
+        <targetInfos>
+          <targetInfo name="Réel"/>
+          <targetInfo name="Simulé"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="header" name="RTE_Driver\Config\RTE_Device.h" version="1.1.2">
+        <instance index="0">RTE\Device\STM32F103RB\RTE_Device.h</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="STM32F1xx CMSIS"/>
+        <package name="STM32F1xx_DFP" schemaVersion="1.4.0" url="http://www.keil.com/pack/" vendor="Keil" version="2.3.0"/>
+        <targetInfos>
+          <targetInfo name="Simulé"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" condition="STM32F1xx MD ARMCC" name="Device\Source\ARM\startup_stm32f10x_md.s" version="1.0.0">
+        <instance index="0">RTE\Device\STM32F103RB\startup_stm32f10x_md.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="STM32F1xx CMSIS"/>
+        <package name="STM32F1xx_DFP" schemaVersion="1.4.0" url="http://www.keil.com/pack/" vendor="Keil" version="2.3.0"/>
+        <targetInfos>
+          <targetInfo name="Simulé"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" name="Device\StdPeriph_Driver\templates\stm32f10x_conf.h" version="3.5.0">
+        <instance index="0" removed="1">RTE\Device\STM32F103RB\stm32f10x_conf.h</instance>
+        <component Cclass="Device" Cgroup="StdPeriph Drivers" Csub="Framework" Cvendor="Keil" Cversion="3.5.1" condition="STM32F1xx STDPERIPH"/>
+        <package name="STM32F1xx_DFP" schemaVersion="1.4.0" url="http://www.keil.com/pack/" vendor="Keil" version="2.2.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="source" name="Device\Source\system_stm32f10x.c" version="1.0.0">
+        <instance index="0">RTE\Device\STM32F103RB\system_stm32f10x.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="STM32F1xx CMSIS"/>
+        <package name="STM32F1xx_DFP" schemaVersion="1.4.0" url="http://www.keil.com/pack/" vendor="Keil" version="2.3.0"/>
+        <targetInfos>
+          <targetInfo name="Simulé"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="header" name="RTE_Driver\Config\RTE_Device.h" version="1.1.2">
+        <instance index="0">RTE\Device\STM32F107VC\RTE_Device.h</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="STM32F1xx CMSIS"/>
+        <package name="STM32F1xx_DFP" schemaVersion="1.4.0" url="http://www.keil.com/pack/" vendor="Keil" version="2.3.0"/>
+        <targetInfos>
+          <targetInfo name="Réel"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" condition="STM32F1xx CL ARMCC" name="Device\Source\ARM\startup_stm32f10x_cl.s" version="1.0.0">
+        <instance index="0">RTE\Device\STM32F107VC\startup_stm32f10x_cl.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="STM32F1xx CMSIS"/>
+        <package name="STM32F1xx_DFP" schemaVersion="1.4.0" url="http://www.keil.com/pack/" vendor="Keil" version="2.3.0"/>
+        <targetInfos>
+          <targetInfo name="Réel"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" name="Device\StdPeriph_Driver\templates\stm32f10x_conf.h" version="3.5.0">
+        <instance index="0" removed="1">RTE\Device\STM32F107VC\stm32f10x_conf.h</instance>
+        <component Cclass="Device" Cgroup="StdPeriph Drivers" Csub="Framework" Cvendor="Keil" Cversion="3.5.1" condition="STM32F1xx STDPERIPH"/>
+        <package name="STM32F1xx_DFP" schemaVersion="1.4.0" url="http://www.keil.com/pack/" vendor="Keil" version="2.2.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="source" name="Device\Source\system_stm32f10x.c" version="1.0.0">
+        <instance index="0">RTE\Device\STM32F107VC\system_stm32f10x.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="STM32F1xx CMSIS"/>
+        <package name="STM32F1xx_DFP" schemaVersion="1.4.0" url="http://www.keil.com/pack/" vendor="Keil" version="2.3.0"/>
+        <targetInfos>
+          <targetInfo name="Réel"/>
+        </targetInfos>
+      </file>
+    </files>
+  </RTE>
+
+</Project>
diff --git a/EventRecorderStub.scvd b/EventRecorderStub.scvd
deleted file mode 100644
index 2956b29..0000000
--- a/EventRecorderStub.scvd
+++ /dev/null
@@ -1,9 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>
-
-<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
-
-<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
-  <events>
-  </events>
-
-</component_viewer>
diff --git a/FonctionEtape.asm b/FonctionEtape.asm
index 6097cad..bf8c559 100644
--- a/FonctionEtape.asm
+++ b/FonctionEtape.asm
@@ -11,7 +11,9 @@
 
 ;***************IMPORT/EXPORT**********************************************
 
-
+	EXPORT Eteint_LED
+	EXPORT Allume_LED
+	EXPORT Inverse_LED
 
 ;**************************************************************************
 
@@ -19,7 +21,8 @@
 
 ;***************CONSTANTES*************************************************
 
-	include REG_UTILES.inc 
+	include REG_UTILES.inc
+	include LUMIERES.inc
 
 ;**************************************************************************
 
@@ -53,10 +56,64 @@
 ;------------------------------------------------------------------------
 
 
+;*******************************************************************************
+;	On eteint la LED
+;*******************************************************************************
+Eteint_LED	PROC
 
+		PUSH {R12,R0}				;On stocke R12 dans R0
+		LDR R12,=GPIOBASEB			;On recupère l'adresse de base
+		MOV R5,#(0x01 << 10)		;1 décalé de 10 dans R5
+		STRH R5,[R12,#OffsetReset]	;On stocke la variable R5 à l'adresse 0x0X40010C14 (reset)
+		POP {R12,R0}				;On restitue R12 dans R0
+		BX LR						;Retour
+;LDR R5,[R12,#0x0C]		;Valeur à l'adresse de l'output
+;AND R5, R5,#~(0x01 << 10)	;OU LOGIQUE pour calculer la valeur a mettre dans l'output
+;STRH R5,[R12,#0x0C]			;Etat du port B (R5) stocké dans l'output 	
+		ENDP
+				
+;*******************************************************************************
+;	On allume la LED
+;*******************************************************************************
+Allume_LED   PROC
 
+		PUSH {R12,R0}			;On stocke R12 dans R0
+		LDR R12,=GPIOBASEB		;On recupère l'adresse de base
+		MOV R5,#(0x01 << 10)	;1 décalé de 10 dans R5
+		STRH R5,[R12,#OffsetSet]	;On stocke la variable R5 à l'adresse 0x0X40010C10 (set)
+		POP {R12,R0}			;On restitue R12 dans R0
+		BX LR					;Retour
+;LDR R5,[R12,#0x0C]		;Valeur à l'adresse de l'output
+;ORR R5, R5,#(0x01 << 10)	;OU LOGIQUE pour calculer la valeur a mettre dans l'output
+;STRH R5,[R12,#0x0C]			;Etat du port B (R5) stocké dans l'output 
+			
+		ENDP
+			
+;*******************************************************************************
+;	On inverse la LED (besoin de R0)
+;*******************************************************************************
+Inverse_LED	  PROC
+		PUSH {R12,R5}			;R12 et R5 sont mis dans la pile
+		LDR R12,=GPIOBASEB		;On recupère l'adresse de base
+		LDR R1,=isLedOn			;On recupère l'adresse de isLedOn
+		MOV R5,#(0x01 << 10)	;1 décalé de 10 dans R5
+		CMP R0,#0				;Si R3=0 (default) alors on allume, sinon on eteint
+		BNE Eteint
+Allume
+		STRH R5,[R12,#OffsetSet]	;On stocke la variable R5 à l'adresse 0x0X40010C10 (set)
+		MOV R0,#1;					;On remet la variable à 1
+		B Fin						;Retour	
+Eteint
+		STRH R5,[R12,#OffsetReset]	;On stocke la variable R5 à l'adresse 0x0X40010C14 (reset)
+		MOV R0,#0;					;On remet la variable à 0
+		B Fin
+		
 
-
+Fin 
+		POP {R12,R5}		;On restitue R12
+		BX LR				;Retour
+	
+	ENDP
 
 ;**************************************************************************
 	END
\ No newline at end of file
diff --git a/FonctionEtape2.asm b/FonctionEtape2.asm
new file mode 100644
index 0000000..8d1a714
--- /dev/null
+++ b/FonctionEtape2.asm
@@ -0,0 +1,223 @@
+;***************************************************************************
+	THUMB	
+	REQUIRE8
+	PRESERVE8
+
+;**************************************************************************
+;  Fichier Vierge.asm
+; Auteur : V.MAHOUT
+; Date :  12/11/2013
+;**************************************************************************
+
+;***************IMPORT/EXPORT**********************************************
+
+	IMPORT DataSend
+	EXPORT Set_SCLK
+	EXPORT Reset_SCLK
+	EXPORT DriverGlobal
+	EXPORT Tempo
+	EXPORT DriverReg
+
+;**************************************************************************
+
+
+
+;***************CONSTANTES*************************************************
+
+	include REG_UTILES.inc 
+	include LUMIERES.inc
+
+;**************************************************************************
+
+
+;***************VARIABLES**************************************************
+	 AREA  MesDonnees, data, readwrite
+;**************************************************************************
+
+SCLK 		EQU 5
+SIN1 		EQU 7
+MILSEC		EQU 1304
+	
+PF			DCD (1<<31)
+
+;**************************************************************************
+
+
+
+;***************CODE*******************************************************
+   	AREA  moncode, code, readonly
+;**************************************************************************
+
+Set_SCLK	PROC
+		PUSH {R0-R2}				;On stocke R0 à R2
+		LDR R1,=GPIOBASEA			;R1 -> Adresse de GPIOA
+		LDRH R2,[R1,#OffsetOutput]	;Valeur à l'adresse d'ODR : R2 = GPIOA->ODR
+		ORR R2, R2,#(0x01 << 5)		;similaire à GPIOA->ODR |= (1<<5)
+		STRH R2,[R1,#OffsetOutput]	;Etat du port B (R5) stocké dans ODR
+		BX LR						;Retour
+	
+	ENDP
+		
+Set_X	PROC
+		PUSH {R1,R2}				;On stocke R1 et R2 dans SP
+		MOV R1, #1					;*******
+		LSL R0, R1, R0				;1<<Arg
+		LDR R1,=GPIOBASEA			;R1 -> Adresse de GPIOA
+		LDRH R2,[R1,#OffsetOutput]	;Valeur à l'adresse d'ODR : R2 = GPIOA->ODR
+		ORR R2, R2, R0				;similaire à GPIOA->ODR |= (1<<Arg)
+		STRH R2,[R1,#OffsetOutput]	;Etat du port B (R2) stocké dans ODR
+		POP{R1,R2}					;Déchargement de la pile
+		BX LR						;Retour
+	
+	ENDP
+		
+Reset_X	PROC
+		PUSH {R1,R2}				;On stocke R1 et R2 dans SP
+		MOV R1, #1					;*******
+		LSL R0, R1, R0				;1<<Arg
+		MVN R0, R0					;~(1<<Arg)
+		LDR R1,=GPIOBASEA			;R1 -> Adresse de GPIOA
+		LDRH R2,[R1,#OffsetOutput]	;Valeur à l'adresse d'ODR : R2 = GPIOA->ODR
+		AND R2, R2, R0				;similaire à GPIOA->ODR &= ~(1<<Arg)
+		STRH R2,[R1,#OffsetOutput]	;Etat du port B (R2) stocké dans ODR
+		POP{R1,R2}					;Déchargement de la pile
+		BX LR						;Retour
+	
+	ENDP
+
+Reset_SCLK	PROC
+		PUSH {R0-R2}				;On stocke R0 à R2 dans SP
+		LDR R1,=GPIOBASEA			;R1 -> Adresse de GPIOA
+		LDRH R2,[R1,#OffsetOutput]	;Valeur à l'adresse d'ODR : R2 = GPIOA->ODR
+		AND R2, R2,#~(0x01 << 5)	;similaire à GPIOA->ODR &= ~(1<<5)
+		STRH R2,[R1,#OffsetOutput]	;Etat du port B (R5) stocké dans ODR
+		BX LR						;Retour
+	
+	ENDP
+		
+Tempo PROC
+		MOV R1,#10					;*******
+		MUL R0,R0,R1				;10*Argument
+		MOV R2,#MILSEC				;1304, la constante pour avoir 0.01ms
+		MOV R3,#0					;0
+WHILE_NBMIL							;for(int i=0;i<10*Arg;i++)
+		ADD R3,R3,#1				;i++
+		MOV R1,#0					;j=0
+		CMP R3,R0					;SI i==10*Arg alors on arrête la boucle
+		BXEQ LR
+WHILE_NOPL							;for(int j=0;j<1304;j++)
+		NOP							;Timing
+		ADD R1,R1,#1				;j++
+		CMP R1,R2					;SI j==1304 alors on arrête la sous-boucle
+		BNE WHILE_NOPL				;NON : On retourne dans cette boucle
+		B WHILE_NBMIL				;OUI : On retourne dans la surboucle
+	ENDP
+		
+;****************************************************************************
+;R1 = *ValCourante
+;R2 = NBLed (i)
+;R3 = ValCourante[i]
+;****************************************************************************
+DriverGlobal	PROC
+		MOV R0, #SCLK	;Argument SCLK
+		BL Set_X;		;Set_X(SCLK)
+		LDR R1,=Barette1;On recupère l'adresse de base
+		
+		MOV R2, #0;			;*************************
+WHILE_NBLED					;for(int i=0;i<48;i++)
+		LDRB R3,[R1,R2]		;ValCourante[i]
+		LSL R3,#24			;ValCourante[i]<<24
+		
+		LDR R0,=PF
+		LDR R5,[R0,#0]	;R5 = (1<<31)
+		MOV R4, #0		;*************************
+WHILE_NBBIT				;for(int j=0;j<12;j++)
+		MOV R0, #SCLK		;Argument SCLK
+		BL Reset_X;			;Reset_X(SCLK)
+		MOV R0, #SIN1		;Argument SIN1
+		AND R6,R3,R5		;ValCourante[i] &= (1<<31) (<- PF)
+		CMP R6,R5			;if(PF == 1)
+		BEQ PoidFortOKIF	;{ Set_X(SIN1) }
+		BL Reset_X;			;else { Reset_X(SIN1) }
+PoidFortOKJUMP				;Fin Si
+		LSL R3,#1			;ValeurCourante[i]<<1
+		MOV R0, #SCLK		;Argument SCLK
+		BL Set_X;			;Set_X(SCLK)
+		ADD R4, R4, #1		;On incrémente NBBit
+		CMP R4, #11			;SI NBBIT==11 alors on arrête la boucle
+		BNE WHILE_NBBIT
+		
+		ADD R2, R2, #1		;On incrémente NBLed
+		CMP R2, #48			;SI NBLED==47 alors on arrête la boucle
+		BNE WHILE_NBLED
+		
+		MOV R0, #SCLK	;Argument SCLK
+		BL Reset_X;		;Reset_X(SCLK)
+		LDR R0,=DataSend;Adresse de DataSend
+		MOV R1,#0		; DataSend
+		STRB R1,[R0]	;DataSend=0
+		B .				;while(1)
+		
+PoidFortOKIF
+	BL Set_X			;Set_X(SCLK)
+	B PoidFortOKJUMP	;After Reset8X
+	
+	ENDP
+
+;****************************************************************************
+;R0 Argument : Barette
+;R1 = *ValCourante
+;R2 = NBLed (i)
+;R3 = ValCourante[i]
+;****************************************************************************
+
+DriverReg	PROC
+		PUSH {LR,R6}	;Place LR dans la pile
+		MOV R1,R0		;On recupère l'adresse de base
+		MOV R0, #SCLK	;Argument SCLK
+		BL Set_X;		;Set_X(SCLK)
+		
+		MOV R2, #0;			;*************************
+REG_WHILE_NBLED					;for(int i=0;i<48;i++)
+		LDRB R3,[R1,R2]		;ValCourante[i]
+		LSL R3,#24			;ValCourante[i]<<24
+		
+		LDR R0,=PF
+		LDR R5,[R0,#0]	;R5 = (1<<31)
+		MOV R4, #0		;*************************
+REG_WHILE_NBBIT				;for(int j=0;j<12;j++)
+		MOV R0, #SCLK		;Argument SCLK
+		BL Reset_X;			;Reset_X(SCLK)
+		MOV R0, #SIN1		;Argument SIN1
+		AND R6,R3,R5		;ValCourante[i] &= (1<<31) (<- PF)
+		CMP R6,R5			;if(PF == 1)
+		BEQ REG_PoidFortOKIF;{ Set_X(SIN1) }
+		BL Reset_X;			;else { Reset_X(SIN1) }
+REG_PoidFortOKJUMP			;Fin Si
+		LSL R3,#1			;ValeurCourante[i]<<1
+		MOV R0, #SCLK		;Argument SCLK
+		BL Set_X;			;Set_X(SCLK)
+		ADD R4, R4, #1		;On incrémente NBBit
+		CMP R4, #12			;SI NBBIT==11 alors on arrête la boucle
+		BNE REG_WHILE_NBBIT
+		
+		ADD R2, R2, #1		;On incrémente NBLed
+		CMP R2, #48			;SI NBLED==47 alors on arrête la boucle
+		BNE REG_WHILE_NBLED
+		
+		MOV R0, #SCLK	;Argument SCLK
+		BL Reset_X;		;Reset_X(SCLK)
+		LDR R0,=DataSend;Adresse de DataSend
+		MOV R1,#0		; DataSend
+		STRB R1,[R0,#0]	;DataSend=0
+		POP {LR,R6}		;On remet LR dans les registres
+		BX LR			;On retourne dans le main
+		
+REG_PoidFortOKIF
+	BL Set_X				;Set_X(SCLK)
+	B REG_PoidFortOKJUMP	;After Reset8X
+	
+	ENDP
+
+;**************************************************************************
+	END
diff --git a/FonctionEtape3.asm b/FonctionEtape3.asm
new file mode 100644
index 0000000..25e6283
--- /dev/null
+++ b/FonctionEtape3.asm
@@ -0,0 +1,152 @@
+;***************************************************************************
+	THUMB	
+	REQUIRE8
+	PRESERVE8
+
+;**************************************************************************
+;  Fichier Vierge.asm
+; Auteur : V.MAHOUT
+; Date :  12/11/2013
+;**************************************************************************
+
+;***************IMPORT/EXPORT**********************************************
+
+	IMPORT DataSend
+	EXPORT Init_TVI
+	IMPORT Stop_Timer4
+	IMPORT Run_Timer4
+	IMPORT mire
+	EXPORT Timer1_IRQHandler
+	EXPORT Timer1Up_IRQHandler
+	EXPORT setIRQFunction
+	EXPORT Timer4_IRQHandler
+		
+	IMPORT DriverReg
+	IMPORT Tempo
+
+;**************************************************************************
+
+
+
+;***************CONSTANTES*************************************************
+
+	include REG_UTILES.inc 
+	include LUMIERES.inc
+
+;**************************************************************************
+
+
+;***************VARIABLES**************************************************
+	 AREA  MesDonnees, data, readwrite
+;**************************************************************************
+
+MAX_Interrupt			EQU 256
+TVI_Flash				EQU 0x0
+
+;**************************************************************************
+
+
+
+;***************CODE*******************************************************
+   	AREA  moncode, code, readonly
+;**************************************************************************
+		
+Timer1_IRQHandler PROC
+		PUSH {LR}
+		;On récupère le CNT, on le divise par le nombre de jeu de leds -> on affect le ARR du timer4
+		LDR R0,=TIM1_CNT
+		LDR R0,[R0]
+		MOV R1,#8
+		UDIV R0, R0, R1
+		LDR R1,=TIM4_ARR
+		STR R0,[R1]
+
+		LDR R0,=TIM1_CNT
+		MOV R1,#0
+		STR R1,[R0]
+		
+		LDR R0,=TIM1_SR				;On charge l'adresse du flag
+		LDR R1, [R0]				;On lit le flag dans SR
+		AND R1, #~(1<<1)			;Reset le flag de CC1IF
+		STR R1, [R0]				;On le stock
+		BL Run_Timer4
+		POP {LR}
+		BX LR
+	ENDP
+
+Timer1Up_IRQHandler PROC
+		PUSH {LR}
+		BL Stop_Timer4
+		LDR R0,=TIM1_SR				;On charge l'adresse du flag
+		LDR R1, [R0]				;On lit le flag dans SR
+		AND R1, #~(1<<0)			;Reset le flag de UIF
+		STR R1, [R0]				;On le stock
+		POP {LR}
+		BX LR
+	ENDP
+
+Timer4_IRQHandler PROC
+	;	SwitchState;
+		PUSH {LR}
+		
+		LDR R2,=SwitchState			;On lit l'adresse de switch state
+		LDRB R3,[R2]				;On charge la donnée
+		CMP R3, #8					;if(Switchstate == 8)
+		BEQ ResetSwitchState
+		B SetLED
+ResetSwitchState					;Switchstate = 0
+		MOV R3, #0;
+		B GoToDriverReg
+SetLED
+		LDR R0,=mire				;tempMire
+		MOV R1,#48
+		MLA R0,R1,R3,R0				;tempMire += (48*Switchstate)
+GoToDriverReg
+		ADD R3, R3, #1				;Switchstate++
+		STRB R3,[R2]				;On remet la donnée
+		BL DriverReg				;DriverReg(mire+Switchstate)
+		LDR R0,=TIM4_SR				;On charge l'adresse du flag
+		LDR R1, [R0]				;On lit le flag dans SR
+		AND R1, #~(1<<0)			;Reset le flag de UIF
+		STR R1, [R0]				;On le stock
+		POP {LR}
+		BX LR
+	ENDP
+
+;On copie toute la TVI dans la RAM (0x2....)
+;On modifie les interruptions Up et CC pour pointer sur nos fonctions rien qu'à nous
+;On fait pointer à SCB_VTOR l'adresse de la TVI que nous avons copié
+Init_TVI PROC
+		LDR R0,=TVI_Flash				;On Lit le premier TVI
+		LDR R1,=TVI_Pile				;Nouvelle TVI
+		MOV R2,#0						;i
+for_tvi								;for(int i=0;i<MAX_Interrupt;i++)
+		LDR R3,[R0]						;temp = TVI_Flash[i]
+		STR R3, [R1]					;TVI_Pile[i] = temp
+		ADD R1,R1,#4					;TVI_Pile++
+		ADD R0,R0,#4					;TVI_Flash++
+		ADD R2,R2,#1					;i++
+		CMP R2,#MAX_Interrupt			;is i == MAX_Interrupt?
+		BNE	for_tvi
+scbvector_link
+		LDR R1,=TVI_Pile				;On relit l'adresse de TVIPile
+		LDR R0,=SCB_VTOR				;ON lit l'adresse de SCB_VTOR
+		STR R1,[R0]						;On met l'adresse de TVI_Pile dans le SCB_VTOR
+		BX LR
+	ENDP
+
+;*******************************************************************
+;Arguments :
+;R0 -> Interruption
+;R1 -> Adresse de la fonction
+;*******************************************************************
+setIRQFunction PROC
+		LDR R3,=TVI_Pile
+		ADD R0,R0,R3
+		STR R1, [R0]
+		BX LR
+	ENDP
+	
+
+;**************************************************************************
+	END
diff --git a/LUMIERES.inc b/LUMIERES.inc
new file mode 100644
index 0000000..001a0a3
--- /dev/null
+++ b/LUMIERES.inc
@@ -0,0 +1,50 @@
+;**************************************
+;     Les deux Barettes 	
+;***************************************
+
+;***************VARIABLES**************************************************
+	 AREA  MesDonnees, data, readwrite
+;**************************************************************************
+
+isLedOn		DCB 0x00
+SwitchState	DCB	0x00
+
+Barette1 	DCB 0xff,0x00,0x0
+			DCB 0xff,0x00,0x0
+			DCB 0xff,0x00,0x0
+			DCB 0xff,0x00,0x0
+			DCB 0xff,0x00,0x0
+			DCB 0xff,0x00,0x0
+			DCB 0xff,0x00,0x0
+			DCB 0xff,0x00,0x0
+			DCB 0xff,0x00,0x0
+			DCB 0xff,0x00,0x0
+			DCB 0xff,0x00,0x0
+			DCB 0xff,0x00,0x00
+			DCB 0xff,0x00,0x00
+			DCB 0xff,0x00,0x00
+			DCB 0xff,0x00,0x00
+			DCB 0x00,0x00,0x00
+			
+Barette2 	DCB 0x00,0x00,0x00
+			DCB 0x00,0xff,0xff
+			DCB 0x00,0xff,0xff
+			DCB 0x00,0xff,0xff
+			DCB 0x00,0xff,0xff
+			DCB 0x00,0xff,0xff
+			DCB 0x00,0xff,0xff
+			DCB 0x00,0xff,0xff
+			DCB 0x00,0xff,0xff
+			DCB 0x00,0xff,0xff
+			DCB 0x00,0xff,0xff
+			DCB 0x00,0xff,0xff
+			DCB 0x00,0xff,0xff
+			DCB 0x00,0xff,0xff
+			DCB 0x00,0xff,0xff
+			DCB 0x00,0x00,0x00
+			
+			
+TVI_Pile	EQU	0x20000200		;9 bits de poids faible = 0
+			
+	END
+		
\ No newline at end of file
diff --git a/Listings/Reel_Etape0.map b/Listings/Reel_Etape0.map
deleted file mode 100644
index 4bc6311..0000000
--- a/Listings/Reel_Etape0.map
+++ /dev/null
@@ -1,599 +0,0 @@
-Component: ARM Compiler 5.06 update 5 (build 528) Tool: armlink [4d35e2]
-
-==============================================================================
-
-Section Cross References
-
-    principale.o(moncode) refers to initialisation.o(i.Init_Cible) for Init_Cible
-    startup_stm32f10x_cl.o(RESET) refers to startup_stm32f10x_cl.o(STACK) for __initial_sp
-    startup_stm32f10x_cl.o(RESET) refers to startup_stm32f10x_cl.o(.text) for Reset_Handler
-    startup_stm32f10x_cl.o(RESET) refers to timer_systick_1.o(i.SysTick_Handler) for SysTick_Handler
-    startup_stm32f10x_cl.o(RESET) refers to fonctiontimer.o(i.TIM1_UP_IRQHandler) for TIM1_UP_IRQHandler
-    startup_stm32f10x_cl.o(RESET) refers to fonctiontimer.o(i.TIM1_CC_IRQHandler) for TIM1_CC_IRQHandler
-    startup_stm32f10x_cl.o(RESET) refers to fonctiontimer.o(i.TIM2_IRQHandler) for TIM2_IRQHandler
-    startup_stm32f10x_cl.o(RESET) refers to fonctiontimer.o(i.TIM3_IRQHandler) for TIM3_IRQHandler
-    startup_stm32f10x_cl.o(RESET) refers to fonctiontimer.o(i.TIM4_IRQHandler) for TIM4_IRQHandler
-    startup_stm32f10x_cl.o(.text) refers to system_stm32f10x.o(i.SystemInit) for SystemInit
-    startup_stm32f10x_cl.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main
-    system_stm32f10x.o(i.SetSysClock) refers to system_stm32f10x.o(i.SetSysClockTo72) for SetSysClockTo72
-    system_stm32f10x.o(i.SystemCoreClockUpdate) refers to system_stm32f10x.o(.data) for SystemCoreClock
-    system_stm32f10x.o(i.SystemInit) refers to system_stm32f10x.o(i.SetSysClock) for SetSysClock
-    initialisation.o(i.Init_Cible) refers to initialisation.o(i.Init_Port) for Init_Port
-    initialisation.o(i.Init_Cible) refers to initialisation.o(i.Init_Dot) for Init_Dot
-    initialisation.o(i.Init_Cible) refers to initialisation.o(i.Init_Timer1) for Init_Timer1
-    initialisation.o(i.Init_Cible) refers to initialisation.o(i.Init_Timer2_PWM) for Init_Timer2_PWM
-    initialisation.o(i.Init_Cible) refers to initialisation.o(i.Init_Timer3_Slave) for Init_Timer3_Slave
-    initialisation.o(i.Init_Cible) refers to initialisation.o(i.Init_Timer4) for Init_Timer4
-    initialisation.o(i.Init_Cible) refers to foncasm.o(moncode) for Envoie192Boucle
-    initialisation.o(i.Init_Cible) refers to pilote_io_1.o(i.Port_IO_Set) for Port_IO_Set
-    initialisation.o(i.Init_Cible) refers to pilote_io_1.o(i.Port_IO_Reset) for Port_IO_Reset
-    initialisation.o(i.Init_Cible) refers to timer_systick_1.o(i.Systick_Period) for Systick_Period
-    initialisation.o(i.Init_Cible) refers to timer_systick_1.o(i.Systick_Prio_IT) for Systick_Prio_IT
-    initialisation.o(i.Init_Cible) refers to initialisation.o(.data) for PrtSurImage
-    initialisation.o(i.Init_Cible) refers to warning.o(.data) for warning
-    initialisation.o(i.Init_Cible) refers to fonctiontimer.o(i.Anim) for Anim
-    initialisation.o(i.Init_Dot) refers to pilote_io_1.o(i.Port_IO_Set) for Port_IO_Set
-    initialisation.o(i.Init_Dot) refers to pilote_io_1.o(i.Port_IO_Reset) for Port_IO_Reset
-    initialisation.o(i.Init_Dot) refers to foncasm.o(moncode) for Envoie96Dot
-    initialisation.o(i.Init_Dot) refers to initialisation.o(.data) for CinqDots
-    initialisation.o(i.Init_Port) refers to pilote_io_1.o(i.GPIO_Configure) for GPIO_Configure
-    initialisation.o(i.Init_Port_SPI) refers to pilote_io_1.o(i.GPIO_Configure) for GPIO_Configure
-    initialisation.o(i.Init_Timer1) refers to ffltui.o(.text) for __aeabi_ui2f
-    initialisation.o(i.Init_Timer1) refers to f2d.o(.text) for __aeabi_f2d
-    initialisation.o(i.Init_Timer1) refers to dmul.o(.text) for __aeabi_dmul
-    initialisation.o(i.Init_Timer1) refers to ddiv.o(.text) for __aeabi_ddiv
-    initialisation.o(i.Init_Timer1) refers to d2f.o(.text) for __aeabi_d2f
-    initialisation.o(i.Init_Timer1) refers to fmul.o(.text) for __aeabi_fmul
-    initialisation.o(i.Init_Timer1) refers to cdcmple.o(.text) for __aeabi_cdcmple
-    initialisation.o(i.Init_Timer1) refers to cdrcmple.o(.text) for __aeabi_cdrcmple
-    initialisation.o(i.Init_Timer1) refers to ffixui.o(.text) for __aeabi_f2uiz
-    initialisation.o(i.Init_Timer2_PWM) refers to f2d.o(.text) for __aeabi_f2d
-    initialisation.o(i.Init_Timer2_PWM) refers to ddiv.o(.text) for __aeabi_ddiv
-    initialisation.o(i.Init_Timer2_PWM) refers to d2f.o(.text) for __aeabi_d2f
-    initialisation.o(i.Init_Timer2_PWM) refers to ffltui.o(.text) for __aeabi_ui2f
-    initialisation.o(i.Init_Timer2_PWM) refers to fmul.o(.text) for __aeabi_fmul
-    initialisation.o(i.Init_Timer2_PWM) refers to ffixui.o(.text) for __aeabi_f2uiz
-    initialisation.o(i.Init_Timer2_PWM) refers to fdiv.o(.text) for __aeabi_fdiv
-    fonctiontimer.o(i.Anim) refers to fonctiontimer.o(.data) for ImageEnCours
-    fonctiontimer.o(i.TIM1_CC_IRQHandler) refers to fonctiontimer.o(.data) for SecteurEnCours
-    fonctiontimer.o(i.TIM1_UP_IRQHandler) refers to foncasm.o(moncode) for Envoie192Boucle
-    fonctiontimer.o(i.TIM1_UP_IRQHandler) refers to fonctiontimer.o(.data) for VitesseSuffisante
-    fonctiontimer.o(i.TIM1_UP_IRQHandler) refers to warning.o(.data) for warning
-    fonctiontimer.o(i.TIM1_UP_IRQHandler) refers to initialisation.o(.data) for BarretEnCours
-    fonctiontimer.o(i.TIM3_IRQHandler) refers to pilote_io_1.o(i.Port_IO_Set) for Port_IO_Set
-    fonctiontimer.o(i.TIM3_IRQHandler) refers to pilote_io_1.o(i.Port_IO_Reset) for Port_IO_Reset
-    fonctiontimer.o(i.TIM3_IRQHandler) refers to initialisation.o(.data) for DataSend
-    fonctiontimer.o(i.TIM4_IRQHandler) refers to foncasm.o(moncode) for Envoie192Boucle
-    fonctiontimer.o(i.TIM4_IRQHandler) refers to fonctiontimer.o(.data) for SecteurEnCours
-    fonctiontimer.o(i.TIM4_IRQHandler) refers to initialisation.o(.data) for PrtSurImage
-    foncasm.o(moncode) refers to initialisation.o(.data) for BarretEnCours
-    timer_systick_1.o(i.SysTick_Handler) refers to timer_systick_1.o(.data) for Ptr_Systick
-    timer_systick_1.o(i.Systick_Period) refers to fmul.o(.text) for __aeabi_fmul
-    timer_systick_1.o(i.Systick_Period) refers to f2d.o(.text) for __aeabi_f2d
-    timer_systick_1.o(i.Systick_Period) refers to ddiv.o(.text) for __aeabi_ddiv
-    timer_systick_1.o(i.Systick_Period) refers to d2f.o(.text) for __aeabi_d2f
-    timer_systick_1.o(i.Systick_Period) refers to ffixui.o(.text) for __aeabi_f2uiz
-    timer_systick_1.o(i.Systick_Period) refers to ffltui.o(.text) for __aeabi_ui2f
-    timer_systick_1.o(i.Systick_Period) refers to fdiv.o(.text) for __aeabi_fdiv
-    timer_systick_1.o(i.Systick_Period) refers to dmul.o(.text) for __aeabi_dmul
-    timer_systick_1.o(i.Systick_Period) refers to cdrcmple.o(.text) for __aeabi_cdrcmple
-    timer_systick_1.o(i.Systick_Prio_IT) refers to timer_systick_1.o(.data) for Ptr_Systick
-    entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000D) for __rt_final_cpp
-    entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$0000000F) for __rt_final_exit
-    entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock
-    entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init
-    entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry9a.o(.ARM.Collect$$$$0000000B) for _main_init
-    entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry5.o(.ARM.Collect$$$$00000004) for _main_scatterload
-    entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry2.o(.ARM.Collect$$$$00000001) for _main_stk
-    fmul.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
-    fdiv.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
-    fdiv.o(.text) refers to fepilogue.o(.text) for _float_round
-    dmul.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
-    dmul.o(.text) refers to depilogue.o(.text) for _double_epilogue
-    ddiv.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
-    ddiv.o(.text) refers to depilogue.o(.text) for _double_round
-    ffltui.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
-    ffltui.o(.text) refers to fepilogue.o(.text) for _float_epilogue
-    ffixui.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
-    f2d.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
-    cdcmple.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
-    cdrcmple.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
-    d2f.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
-    d2f.o(.text) refers to fepilogue.o(.text) for _float_round
-    entry2.o(.ARM.Collect$$$$00000001) refers to entry2.o(.ARM.Collect$$$$00002712) for __lit__00000000
-    entry2.o(.ARM.Collect$$$$00002712) refers to startup_stm32f10x_cl.o(STACK) for __initial_sp
-    entry2.o(__vectab_stack_and_reset_area) refers to startup_stm32f10x_cl.o(STACK) for __initial_sp
-    entry2.o(__vectab_stack_and_reset_area) refers to entry.o(.ARM.Collect$$$$00000000) for __main
-    entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload
-    entry9a.o(.ARM.Collect$$$$0000000B) refers to principale.o(moncode) for main
-    entry9b.o(.ARM.Collect$$$$0000000C) refers to principale.o(moncode) for main
-    depilogue.o(.text) refers to llshl.o(.text) for __aeabi_llsl
-    depilogue.o(.text) refers to llushr.o(.text) for __aeabi_llsr
-    init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload
-
-
-==============================================================================
-
-Removing Unused input sections from the image.
-
-    Removing principale.o(mesdonnees), (0 bytes).
-    Removing fonctionetape.o(MesDonnees), (0 bytes).
-    Removing fonctionetape.o(moncode), (0 bytes).
-    Removing startup_stm32f10x_cl.o(HEAP), (512 bytes).
-    Removing system_stm32f10x.o(.rev16_text), (4 bytes).
-    Removing system_stm32f10x.o(.revsh_text), (4 bytes).
-    Removing system_stm32f10x.o(.rrx_text), (6 bytes).
-    Removing system_stm32f10x.o(i.SystemCoreClockUpdate), (256 bytes).
-    Removing system_stm32f10x.o(.data), (20 bytes).
-    Removing initialisation.o(.rev16_text), (4 bytes).
-    Removing initialisation.o(.revsh_text), (4 bytes).
-    Removing initialisation.o(.rrx_text), (6 bytes).
-    Removing initialisation.o(i.Init_Port_SPI), (76 bytes).
-    Removing fonctiontimer.o(.rev16_text), (4 bytes).
-    Removing fonctiontimer.o(.revsh_text), (4 bytes).
-    Removing fonctiontimer.o(.rrx_text), (6 bytes).
-    Removing fonctiontimer.o(i.Run_Timer1), (20 bytes).
-    Removing fonctiontimer.o(i.Run_Timer2), (18 bytes).
-    Removing fonctiontimer.o(i.Run_Timer3), (20 bytes).
-    Removing fonctiontimer.o(i.Run_Timer4), (20 bytes).
-    Removing fonctiontimer.o(i.Stop_Timer1), (20 bytes).
-    Removing fonctiontimer.o(i.Stop_Timer2), (18 bytes).
-    Removing fonctiontimer.o(i.Stop_Timer3), (20 bytes).
-    Removing fonctiontimer.o(i.Stop_Timer4), (20 bytes).
-    Removing foncasm.o(muu), (0 bytes).
-    Removing pilote_io_1.o(.rev16_text), (4 bytes).
-    Removing pilote_io_1.o(.revsh_text), (4 bytes).
-    Removing pilote_io_1.o(.rrx_text), (6 bytes).
-    Removing pilote_io_1.o(i.Port_IO_Blink), (16 bytes).
-    Removing pilote_io_1.o(i.Port_IO_Init_Input), (74 bytes).
-    Removing pilote_io_1.o(i.Port_IO_Init_Input_Analog), (46 bytes).
-    Removing pilote_io_1.o(i.Port_IO_Init_Output), (74 bytes).
-    Removing pilote_io_1.o(i.Port_IO_Read), (12 bytes).
-    Removing timer_systick_1.o(.rev16_text), (4 bytes).
-    Removing timer_systick_1.o(.revsh_text), (4 bytes).
-    Removing timer_systick_1.o(.rrx_text), (6 bytes).
-
-36 unused section(s) (total 1312 bytes) removed from the image.
-
-==============================================================================
-
-Image Symbol Table
-
-    Local Symbols
-
-    Symbol Name                              Value     Ov Type        Size  Object(Section)
-
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry10a.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry9b.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry9a.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry7a.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry8b.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry2.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry11b.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry8a.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry11a.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry5.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry7b.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry10b.o ABSOLUTE
-    ../clib/microlib/longlong.c              0x00000000   Number         0  llushr.o ABSOLUTE
-    ../clib/microlib/longlong.c              0x00000000   Number         0  llshl.o ABSOLUTE
-    ../clib/microlib/stubs.s                 0x00000000   Number         0  iusefp.o ABSOLUTE
-    ../fplib/microlib/d2f.c                  0x00000000   Number         0  d2f.o ABSOLUTE
-    ../fplib/microlib/f2d.c                  0x00000000   Number         0  f2d.o ABSOLUTE
-    ../fplib/microlib/fpdiv.c                0x00000000   Number         0  ddiv.o ABSOLUTE
-    ../fplib/microlib/fpdiv.c                0x00000000   Number         0  fdiv.o ABSOLUTE
-    ../fplib/microlib/fpepilogue.c           0x00000000   Number         0  depilogue.o ABSOLUTE
-    ../fplib/microlib/fpepilogue.c           0x00000000   Number         0  fepilogue.o ABSOLUTE
-    ../fplib/microlib/fpfix.c                0x00000000   Number         0  ffixui.o ABSOLUTE
-    ../fplib/microlib/fpflt.c                0x00000000   Number         0  ffltui.o ABSOLUTE
-    ../fplib/microlib/fpmul.c                0x00000000   Number         0  fmul.o ABSOLUTE
-    ../fplib/microlib/fpmul.c                0x00000000   Number         0  dmul.o ABSOLUTE
-    ..\\pilotes\\Sources\\Timer_Systick.c    0x00000000   Number         0  timer_systick_1.o ABSOLUTE
-    ..\\pilotes\\Sources\\pilote_IO.c        0x00000000   Number         0  pilote_io_1.o ABSOLUTE
-    ..\pilotes\Sources\Timer_Systick.c       0x00000000   Number         0  timer_systick_1.o ABSOLUTE
-    ..\pilotes\Sources\pilote_IO.c           0x00000000   Number         0  pilote_io_1.o ABSOLUTE
-    FoncAsm.asm                              0x00000000   Number         0  foncasm.o ABSOLUTE
-    FonctionEtape.asm                        0x00000000   Number         0  fonctionetape.o ABSOLUTE
-    FonctionTimer.c                          0x00000000   Number         0  fonctiontimer.o ABSOLUTE
-    FonctionTimer.c                          0x00000000   Number         0  fonctiontimer.o ABSOLUTE
-    Initialisation.c                         0x00000000   Number         0  initialisation.o ABSOLUTE
-    Initialisation.c                         0x00000000   Number         0  initialisation.o ABSOLUTE
-    Principale.asm                           0x00000000   Number         0  principale.o ABSOLUTE
-    RTE\Device\STM32F107VC\startup_stm32f10x_cl.s 0x00000000   Number         0  startup_stm32f10x_cl.o ABSOLUTE
-    RTE\Device\STM32F107VC\system_stm32f10x.c 0x00000000   Number         0  system_stm32f10x.o ABSOLUTE
-    RTE\\Device\\STM32F107VC\\system_stm32f10x.c 0x00000000   Number         0  system_stm32f10x.o ABSOLUTE
-    Warning.c                                0x00000000   Number         0  warning.o ABSOLUTE
-    cdcmple.s                                0x00000000   Number         0  cdcmple.o ABSOLUTE
-    cdrcmple.s                               0x00000000   Number         0  cdrcmple.o ABSOLUTE
-    dc.s                                     0x00000000   Number         0  dc.o ABSOLUTE
-    handlers.s                               0x00000000   Number         0  handlers.o ABSOLUTE
-    init.s                                   0x00000000   Number         0  init.o ABSOLUTE
-    RESET                                    0x08000000   Section      336  startup_stm32f10x_cl.o(RESET)
-    .ARM.Collect$$$$00000000                 0x08000150   Section        0  entry.o(.ARM.Collect$$$$00000000)
-    .ARM.Collect$$$$00000001                 0x08000150   Section        4  entry2.o(.ARM.Collect$$$$00000001)
-    .ARM.Collect$$$$00000004                 0x08000154   Section        4  entry5.o(.ARM.Collect$$$$00000004)
-    .ARM.Collect$$$$00000008                 0x08000158   Section        0  entry7b.o(.ARM.Collect$$$$00000008)
-    .ARM.Collect$$$$0000000A                 0x08000158   Section        0  entry8b.o(.ARM.Collect$$$$0000000A)
-    .ARM.Collect$$$$0000000B                 0x08000158   Section        8  entry9a.o(.ARM.Collect$$$$0000000B)
-    .ARM.Collect$$$$0000000D                 0x08000160   Section        0  entry10a.o(.ARM.Collect$$$$0000000D)
-    .ARM.Collect$$$$0000000F                 0x08000160   Section        0  entry11a.o(.ARM.Collect$$$$0000000F)
-    .ARM.Collect$$$$00002712                 0x08000160   Section        4  entry2.o(.ARM.Collect$$$$00002712)
-    __lit__00000000                          0x08000160   Data           4  entry2.o(.ARM.Collect$$$$00002712)
-    .text                                    0x08000164   Section       36  startup_stm32f10x_cl.o(.text)
-    .text                                    0x08000188   Section        0  fmul.o(.text)
-    .text                                    0x080001ec   Section        0  fdiv.o(.text)
-    .text                                    0x08000268   Section        0  dmul.o(.text)
-    .text                                    0x0800034c   Section        0  ddiv.o(.text)
-    .text                                    0x0800042a   Section        0  ffltui.o(.text)
-    .text                                    0x08000434   Section        0  ffixui.o(.text)
-    .text                                    0x0800045c   Section        0  f2d.o(.text)
-    .text                                    0x08000484   Section       48  cdcmple.o(.text)
-    .text                                    0x080004b4   Section       48  cdrcmple.o(.text)
-    .text                                    0x080004e4   Section        0  d2f.o(.text)
-    .text                                    0x0800051c   Section        0  fepilogue.o(.text)
-    .text                                    0x0800051c   Section        0  iusefp.o(.text)
-    .text                                    0x0800058a   Section        0  depilogue.o(.text)
-    .text                                    0x08000644   Section       36  init.o(.text)
-    .text                                    0x08000668   Section        0  llshl.o(.text)
-    .text                                    0x08000686   Section        0  llushr.o(.text)
-    i.Anim                                   0x080006a8   Section        0  fonctiontimer.o(i.Anim)
-    i.GPIO_Configure                         0x080006d0   Section        0  pilote_io_1.o(i.GPIO_Configure)
-    i.Init_Cible                             0x0800081c   Section        0  initialisation.o(i.Init_Cible)
-    i.Init_Dot                               0x08000928   Section        0  initialisation.o(i.Init_Dot)
-    i.Init_Port                              0x080009a0   Section        0  initialisation.o(i.Init_Port)
-    i.Init_Timer1                            0x08000a30   Section        0  initialisation.o(i.Init_Timer1)
-    i.Init_Timer2_PWM                        0x08000ba4   Section        0  initialisation.o(i.Init_Timer2_PWM)
-    i.Init_Timer3_Slave                      0x08000cc0   Section        0  initialisation.o(i.Init_Timer3_Slave)
-    i.Init_Timer4                            0x08000d30   Section        0  initialisation.o(i.Init_Timer4)
-    i.Port_IO_Reset                          0x08000da4   Section        0  pilote_io_1.o(i.Port_IO_Reset)
-    i.Port_IO_Set                            0x08000db4   Section        0  pilote_io_1.o(i.Port_IO_Set)
-    i.SetSysClock                            0x08000dc4   Section        0  system_stm32f10x.o(i.SetSysClock)
-    SetSysClock                              0x08000dc5   Thumb Code     8  system_stm32f10x.o(i.SetSysClock)
-    i.SetSysClockTo72                        0x08000dcc   Section        0  system_stm32f10x.o(i.SetSysClockTo72)
-    SetSysClockTo72                          0x08000dcd   Thumb Code   264  system_stm32f10x.o(i.SetSysClockTo72)
-    i.SysTick_Handler                        0x08000ee4   Section        0  timer_systick_1.o(i.SysTick_Handler)
-    i.SystemInit                             0x08000ef4   Section        0  system_stm32f10x.o(i.SystemInit)
-    i.Systick_Period                         0x08000f60   Section        0  timer_systick_1.o(i.Systick_Period)
-    i.Systick_Prio_IT                        0x08001070   Section        0  timer_systick_1.o(i.Systick_Prio_IT)
-    i.TIM1_CC_IRQHandler                     0x08001094   Section        0  fonctiontimer.o(i.TIM1_CC_IRQHandler)
-    i.TIM1_UP_IRQHandler                     0x08001148   Section        0  fonctiontimer.o(i.TIM1_UP_IRQHandler)
-    i.TIM2_IRQHandler                        0x080011f4   Section        0  fonctiontimer.o(i.TIM2_IRQHandler)
-    i.TIM3_IRQHandler                        0x080011f8   Section        0  fonctiontimer.o(i.TIM3_IRQHandler)
-    i.TIM4_IRQHandler                        0x08001248   Section        0  fonctiontimer.o(i.TIM4_IRQHandler)
-    i.__scatterload_copy                     0x080012b4   Section       14  handlers.o(i.__scatterload_copy)
-    i.__scatterload_null                     0x080012c2   Section        2  handlers.o(i.__scatterload_null)
-    i.__scatterload_zeroinit                 0x080012c4   Section       14  handlers.o(i.__scatterload_zeroinit)
-    moncode                                  0x080012d4   Section       10  principale.o(moncode)
-    moncode                                  0x080012e0   Section      212  foncasm.o(moncode)
-    .data                                    0x20000000   Section       19  initialisation.o(.data)
-    .data                                    0x20000014   Section       24  fonctiontimer.o(.data)
-    incre                                    0x20000024   Data           4  fonctiontimer.o(.data)
-    Compteur                                 0x20000028   Data           4  fonctiontimer.o(.data)
-    .data                                    0x2000002c   Section       96  warning.o(.data)
-    .data                                    0x2000008c   Section        4  timer_systick_1.o(.data)
-    Ptr_Systick                              0x2000008c   Data           4  timer_systick_1.o(.data)
-    STACK                                    0x20000090   Section     1024  startup_stm32f10x_cl.o(STACK)
-
-    Global Symbols
-
-    Symbol Name                              Value     Ov Type        Size  Object(Section)
-
-    BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OTIME$ROPI$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000   Number         0  anon$$obj.o ABSOLUTE
-    __cpp_initialize__aeabi_                  - Undefined Weak Reference
-    __cxa_finalize                            - Undefined Weak Reference
-    __decompress                              - Undefined Weak Reference
-    _clock_init                               - Undefined Weak Reference
-    _microlib_exit                            - Undefined Weak Reference
-    __Vectors_Size                           0x00000150   Number         0  startup_stm32f10x_cl.o ABSOLUTE
-    __Vectors                                0x08000000   Data           4  startup_stm32f10x_cl.o(RESET)
-    __Vectors_End                            0x08000150   Data           0  startup_stm32f10x_cl.o(RESET)
-    __main                                   0x08000151   Thumb Code     0  entry.o(.ARM.Collect$$$$00000000)
-    _main_stk                                0x08000151   Thumb Code     0  entry2.o(.ARM.Collect$$$$00000001)
-    _main_scatterload                        0x08000155   Thumb Code     0  entry5.o(.ARM.Collect$$$$00000004)
-    __main_after_scatterload                 0x08000159   Thumb Code     0  entry5.o(.ARM.Collect$$$$00000004)
-    _main_clock                              0x08000159   Thumb Code     0  entry7b.o(.ARM.Collect$$$$00000008)
-    _main_cpp_init                           0x08000159   Thumb Code     0  entry8b.o(.ARM.Collect$$$$0000000A)
-    _main_init                               0x08000159   Thumb Code     0  entry9a.o(.ARM.Collect$$$$0000000B)
-    __rt_final_cpp                           0x08000161   Thumb Code     0  entry10a.o(.ARM.Collect$$$$0000000D)
-    __rt_final_exit                          0x08000161   Thumb Code     0  entry11a.o(.ARM.Collect$$$$0000000F)
-    Reset_Handler                            0x08000165   Thumb Code     8  startup_stm32f10x_cl.o(.text)
-    NMI_Handler                              0x0800016d   Thumb Code     2  startup_stm32f10x_cl.o(.text)
-    HardFault_Handler                        0x0800016f   Thumb Code     2  startup_stm32f10x_cl.o(.text)
-    MemManage_Handler                        0x08000171   Thumb Code     2  startup_stm32f10x_cl.o(.text)
-    BusFault_Handler                         0x08000173   Thumb Code     2  startup_stm32f10x_cl.o(.text)
-    UsageFault_Handler                       0x08000175   Thumb Code     2  startup_stm32f10x_cl.o(.text)
-    SVC_Handler                              0x08000177   Thumb Code     2  startup_stm32f10x_cl.o(.text)
-    DebugMon_Handler                         0x08000179   Thumb Code     2  startup_stm32f10x_cl.o(.text)
-    PendSV_Handler                           0x0800017b   Thumb Code     2  startup_stm32f10x_cl.o(.text)
-    ADC1_2_IRQHandler                        0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    CAN1_RX0_IRQHandler                      0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    CAN1_RX1_IRQHandler                      0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    CAN1_SCE_IRQHandler                      0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    CAN1_TX_IRQHandler                       0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    CAN2_RX0_IRQHandler                      0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    CAN2_RX1_IRQHandler                      0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    CAN2_SCE_IRQHandler                      0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    CAN2_TX_IRQHandler                       0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    DMA1_Channel1_IRQHandler                 0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    DMA1_Channel2_IRQHandler                 0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    DMA1_Channel3_IRQHandler                 0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    DMA1_Channel4_IRQHandler                 0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    DMA1_Channel5_IRQHandler                 0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    DMA1_Channel6_IRQHandler                 0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    DMA1_Channel7_IRQHandler                 0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    DMA2_Channel1_IRQHandler                 0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    DMA2_Channel2_IRQHandler                 0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    DMA2_Channel3_IRQHandler                 0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    DMA2_Channel4_IRQHandler                 0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    DMA2_Channel5_IRQHandler                 0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    ETH_IRQHandler                           0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    ETH_WKUP_IRQHandler                      0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    EXTI0_IRQHandler                         0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    EXTI15_10_IRQHandler                     0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    EXTI1_IRQHandler                         0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    EXTI2_IRQHandler                         0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    EXTI3_IRQHandler                         0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    EXTI4_IRQHandler                         0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    EXTI9_5_IRQHandler                       0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    FLASH_IRQHandler                         0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    I2C1_ER_IRQHandler                       0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    I2C1_EV_IRQHandler                       0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    I2C2_ER_IRQHandler                       0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    I2C2_EV_IRQHandler                       0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    OTG_FS_IRQHandler                        0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    OTG_FS_WKUP_IRQHandler                   0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    PVD_IRQHandler                           0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    RCC_IRQHandler                           0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    RTCAlarm_IRQHandler                      0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    RTC_IRQHandler                           0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    SPI1_IRQHandler                          0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    SPI2_IRQHandler                          0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    SPI3_IRQHandler                          0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    TAMPER_IRQHandler                        0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    TIM1_BRK_IRQHandler                      0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    TIM1_TRG_COM_IRQHandler                  0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    TIM5_IRQHandler                          0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    TIM6_IRQHandler                          0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    TIM7_IRQHandler                          0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    UART4_IRQHandler                         0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    UART5_IRQHandler                         0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    USART1_IRQHandler                        0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    USART2_IRQHandler                        0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    USART3_IRQHandler                        0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    WWDG_IRQHandler                          0x0800017f   Thumb Code     0  startup_stm32f10x_cl.o(.text)
-    __aeabi_fmul                             0x08000189   Thumb Code   100  fmul.o(.text)
-    __aeabi_fdiv                             0x080001ed   Thumb Code   124  fdiv.o(.text)
-    __aeabi_dmul                             0x08000269   Thumb Code   228  dmul.o(.text)
-    __aeabi_ddiv                             0x0800034d   Thumb Code   222  ddiv.o(.text)
-    __aeabi_ui2f                             0x0800042b   Thumb Code    10  ffltui.o(.text)
-    __aeabi_f2uiz                            0x08000435   Thumb Code    40  ffixui.o(.text)
-    __aeabi_f2d                              0x0800045d   Thumb Code    38  f2d.o(.text)
-    __aeabi_cdcmpeq                          0x08000485   Thumb Code     0  cdcmple.o(.text)
-    __aeabi_cdcmple                          0x08000485   Thumb Code    48  cdcmple.o(.text)
-    __aeabi_cdrcmple                         0x080004b5   Thumb Code    48  cdrcmple.o(.text)
-    __aeabi_d2f                              0x080004e5   Thumb Code    56  d2f.o(.text)
-    __I$use$fp                               0x0800051d   Thumb Code     0  iusefp.o(.text)
-    _float_round                             0x0800051d   Thumb Code    18  fepilogue.o(.text)
-    _float_epilogue                          0x0800052f   Thumb Code    92  fepilogue.o(.text)
-    _double_round                            0x0800058b   Thumb Code    30  depilogue.o(.text)
-    _double_epilogue                         0x080005a9   Thumb Code   156  depilogue.o(.text)
-    __scatterload                            0x08000645   Thumb Code    28  init.o(.text)
-    __scatterload_rt2                        0x08000645   Thumb Code     0  init.o(.text)
-    __aeabi_llsl                             0x08000669   Thumb Code    30  llshl.o(.text)
-    _ll_shift_l                              0x08000669   Thumb Code     0  llshl.o(.text)
-    __aeabi_llsr                             0x08000687   Thumb Code    32  llushr.o(.text)
-    _ll_ushift_r                             0x08000687   Thumb Code     0  llushr.o(.text)
-    Anim                                     0x080006a9   Thumb Code    32  fonctiontimer.o(i.Anim)
-    GPIO_Configure                           0x080006d1   Thumb Code   314  pilote_io_1.o(i.GPIO_Configure)
-    Init_Cible                               0x0800081d   Thumb Code   218  initialisation.o(i.Init_Cible)
-    Init_Dot                                 0x08000929   Thumb Code   112  initialisation.o(i.Init_Dot)
-    Init_Port                                0x080009a1   Thumb Code   134  initialisation.o(i.Init_Port)
-    Init_Timer1                              0x08000a31   Thumb Code   336  initialisation.o(i.Init_Timer1)
-    Init_Timer2_PWM                          0x08000ba5   Thumb Code   262  initialisation.o(i.Init_Timer2_PWM)
-    Init_Timer3_Slave                        0x08000cc1   Thumb Code    94  initialisation.o(i.Init_Timer3_Slave)
-    Init_Timer4                              0x08000d31   Thumb Code   100  initialisation.o(i.Init_Timer4)
-    Port_IO_Reset                            0x08000da5   Thumb Code    16  pilote_io_1.o(i.Port_IO_Reset)
-    Port_IO_Set                              0x08000db5   Thumb Code    16  pilote_io_1.o(i.Port_IO_Set)
-    SysTick_Handler                          0x08000ee5   Thumb Code    10  timer_systick_1.o(i.SysTick_Handler)
-    SystemInit                               0x08000ef5   Thumb Code    92  system_stm32f10x.o(i.SystemInit)
-    Systick_Period                           0x08000f61   Thumb Code   256  timer_systick_1.o(i.Systick_Period)
-    Systick_Prio_IT                          0x08001071   Thumb Code    28  timer_systick_1.o(i.Systick_Prio_IT)
-    TIM1_CC_IRQHandler                       0x08001095   Thumb Code   158  fonctiontimer.o(i.TIM1_CC_IRQHandler)
-    TIM1_UP_IRQHandler                       0x08001149   Thumb Code   134  fonctiontimer.o(i.TIM1_UP_IRQHandler)
-    TIM2_IRQHandler                          0x080011f5   Thumb Code     4  fonctiontimer.o(i.TIM2_IRQHandler)
-    TIM3_IRQHandler                          0x080011f9   Thumb Code    68  fonctiontimer.o(i.TIM3_IRQHandler)
-    TIM4_IRQHandler                          0x08001249   Thumb Code    84  fonctiontimer.o(i.TIM4_IRQHandler)
-    __scatterload_copy                       0x080012b5   Thumb Code    14  handlers.o(i.__scatterload_copy)
-    __scatterload_null                       0x080012c3   Thumb Code     2  handlers.o(i.__scatterload_null)
-    __scatterload_zeroinit                   0x080012c5   Thumb Code    14  handlers.o(i.__scatterload_zeroinit)
-    main                                     0x080012d5   Thumb Code    10  principale.o(moncode)
-    Envoie192Boucle                          0x080012e1   Thumb Code   116  foncasm.o(moncode)
-    Envoie96Dot                              0x08001355   Thumb Code    78  foncasm.o(moncode)
-    Region$$Table$$Base                      0x080013b4   Number         0  anon$$obj.o(Region$$Table)
-    Region$$Table$$Limit                     0x080013d4   Number         0  anon$$obj.o(Region$$Table)
-    PrtSurImage                              0x20000000   Data           4  initialisation.o(.data)
-    BarretEnCours                            0x20000004   Data           4  initialisation.o(.data)
-    DataSend                                 0x20000008   Data           1  initialisation.o(.data)
-    Angle                                    0x2000000c   Data           4  initialisation.o(.data)
-    CinqDots                                 0x20000010   Data           3  initialisation.o(.data)
-    VitesseSuffisante                        0x20000014   Data           4  fonctiontimer.o(.data)
-    SecteurEnCours                           0x20000018   Data           4  fonctiontimer.o(.data)
-    ImageEnCours                             0x2000001c   Data           4  fonctiontimer.o(.data)
-    increment                                0x20000020   Data           4  fonctiontimer.o(.data)
-    warning                                  0x2000002c   Data          96  warning.o(.data)
-    __initial_sp                             0x20000490   Data           0  startup_stm32f10x_cl.o(STACK)
-
-
-
-==============================================================================
-
-Memory Map of the image
-
-  Image Entry point : 0x08000151
-
-  Load Region LR_IROM1 (Base: 0x08000000, Size: 0x00001464, Max: 0x00040000, ABSOLUTE)
-
-    Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x000013d4, Max: 0x00040000, ABSOLUTE)
-
-    Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
-
-    0x08000000   0x08000000   0x00000150   Data   RO           12    RESET               startup_stm32f10x_cl.o
-    0x08000150   0x08000150   0x00000000   Code   RO          424  * .ARM.Collect$$$$00000000  mc_w.l(entry.o)
-    0x08000150   0x08000150   0x00000004   Code   RO          447    .ARM.Collect$$$$00000001  mc_w.l(entry2.o)
-    0x08000154   0x08000154   0x00000004   Code   RO          450    .ARM.Collect$$$$00000004  mc_w.l(entry5.o)
-    0x08000158   0x08000158   0x00000000   Code   RO          452    .ARM.Collect$$$$00000008  mc_w.l(entry7b.o)
-    0x08000158   0x08000158   0x00000000   Code   RO          454    .ARM.Collect$$$$0000000A  mc_w.l(entry8b.o)
-    0x08000158   0x08000158   0x00000008   Code   RO          455    .ARM.Collect$$$$0000000B  mc_w.l(entry9a.o)
-    0x08000160   0x08000160   0x00000000   Code   RO          457    .ARM.Collect$$$$0000000D  mc_w.l(entry10a.o)
-    0x08000160   0x08000160   0x00000000   Code   RO          459    .ARM.Collect$$$$0000000F  mc_w.l(entry11a.o)
-    0x08000160   0x08000160   0x00000004   Code   RO          448    .ARM.Collect$$$$00002712  mc_w.l(entry2.o)
-    0x08000164   0x08000164   0x00000024   Code   RO           13    .text               startup_stm32f10x_cl.o
-    0x08000188   0x08000188   0x00000064   Code   RO          427    .text               mf_w.l(fmul.o)
-    0x080001ec   0x080001ec   0x0000007c   Code   RO          429    .text               mf_w.l(fdiv.o)
-    0x08000268   0x08000268   0x000000e4   Code   RO          431    .text               mf_w.l(dmul.o)
-    0x0800034c   0x0800034c   0x000000de   Code   RO          433    .text               mf_w.l(ddiv.o)
-    0x0800042a   0x0800042a   0x0000000a   Code   RO          435    .text               mf_w.l(ffltui.o)
-    0x08000434   0x08000434   0x00000028   Code   RO          437    .text               mf_w.l(ffixui.o)
-    0x0800045c   0x0800045c   0x00000026   Code   RO          439    .text               mf_w.l(f2d.o)
-    0x08000482   0x08000482   0x00000002   PAD
-    0x08000484   0x08000484   0x00000030   Code   RO          441    .text               mf_w.l(cdcmple.o)
-    0x080004b4   0x080004b4   0x00000030   Code   RO          443    .text               mf_w.l(cdrcmple.o)
-    0x080004e4   0x080004e4   0x00000038   Code   RO          445    .text               mf_w.l(d2f.o)
-    0x0800051c   0x0800051c   0x00000000   Code   RO          461    .text               mc_w.l(iusefp.o)
-    0x0800051c   0x0800051c   0x0000006e   Code   RO          462    .text               mf_w.l(fepilogue.o)
-    0x0800058a   0x0800058a   0x000000ba   Code   RO          464    .text               mf_w.l(depilogue.o)
-    0x08000644   0x08000644   0x00000024   Code   RO          466    .text               mc_w.l(init.o)
-    0x08000668   0x08000668   0x0000001e   Code   RO          468    .text               mc_w.l(llshl.o)
-    0x08000686   0x08000686   0x00000020   Code   RO          470    .text               mc_w.l(llushr.o)
-    0x080006a6   0x080006a6   0x00000002   PAD
-    0x080006a8   0x080006a8   0x00000028   Code   RO          200    i.Anim              Matos.lib(fonctiontimer.o)
-    0x080006d0   0x080006d0   0x0000014c   Code   RO          323    i.GPIO_Configure    Matos.lib(pilote_io_1.o)
-    0x0800081c   0x0800081c   0x0000010c   Code   RO           86    i.Init_Cible        Matos.lib(initialisation.o)
-    0x08000928   0x08000928   0x00000078   Code   RO           87    i.Init_Dot          Matos.lib(initialisation.o)
-    0x080009a0   0x080009a0   0x00000090   Code   RO           88    i.Init_Port         Matos.lib(initialisation.o)
-    0x08000a30   0x08000a30   0x00000174   Code   RO           90    i.Init_Timer1       Matos.lib(initialisation.o)
-    0x08000ba4   0x08000ba4   0x0000011c   Code   RO           91    i.Init_Timer2_PWM   Matos.lib(initialisation.o)
-    0x08000cc0   0x08000cc0   0x00000070   Code   RO           92    i.Init_Timer3_Slave  Matos.lib(initialisation.o)
-    0x08000d30   0x08000d30   0x00000074   Code   RO           93    i.Init_Timer4       Matos.lib(initialisation.o)
-    0x08000da4   0x08000da4   0x00000010   Code   RO          329    i.Port_IO_Reset     Matos.lib(pilote_io_1.o)
-    0x08000db4   0x08000db4   0x00000010   Code   RO          330    i.Port_IO_Set       Matos.lib(pilote_io_1.o)
-    0x08000dc4   0x08000dc4   0x00000008   Code   RO           20    i.SetSysClock       system_stm32f10x.o
-    0x08000dcc   0x08000dcc   0x00000118   Code   RO           21    i.SetSysClockTo72   system_stm32f10x.o
-    0x08000ee4   0x08000ee4   0x00000010   Code   RO          389    i.SysTick_Handler   Matos.lib(timer_systick_1.o)
-    0x08000ef4   0x08000ef4   0x0000006c   Code   RO           23    i.SystemInit        system_stm32f10x.o
-    0x08000f60   0x08000f60   0x00000110   Code   RO          390    i.Systick_Period    Matos.lib(timer_systick_1.o)
-    0x08001070   0x08001070   0x00000024   Code   RO          391    i.Systick_Prio_IT   Matos.lib(timer_systick_1.o)
-    0x08001094   0x08001094   0x000000b4   Code   RO          209    i.TIM1_CC_IRQHandler  Matos.lib(fonctiontimer.o)
-    0x08001148   0x08001148   0x000000ac   Code   RO          210    i.TIM1_UP_IRQHandler  Matos.lib(fonctiontimer.o)
-    0x080011f4   0x080011f4   0x00000004   Code   RO          211    i.TIM2_IRQHandler   Matos.lib(fonctiontimer.o)
-    0x080011f8   0x080011f8   0x00000050   Code   RO          212    i.TIM3_IRQHandler   Matos.lib(fonctiontimer.o)
-    0x08001248   0x08001248   0x0000006c   Code   RO          213    i.TIM4_IRQHandler   Matos.lib(fonctiontimer.o)
-    0x080012b4   0x080012b4   0x0000000e   Code   RO          474    i.__scatterload_copy  mc_w.l(handlers.o)
-    0x080012c2   0x080012c2   0x00000002   Code   RO          475    i.__scatterload_null  mc_w.l(handlers.o)
-    0x080012c4   0x080012c4   0x0000000e   Code   RO          476    i.__scatterload_zeroinit  mc_w.l(handlers.o)
-    0x080012d2   0x080012d2   0x00000002   PAD
-    0x080012d4   0x080012d4   0x0000000a   Code   RO            2    moncode             principale.o
-    0x080012de   0x080012de   0x00000002   PAD
-    0x080012e0   0x080012e0   0x000000d4   Code   RO          316    moncode             Matos.lib(foncasm.o)
-    0x080013b4   0x080013b4   0x00000020   Data   RO          472    Region$$Table       anon$$obj.o
-
-
-    Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x080013d4, Size: 0x00000490, Max: 0x00010000, ABSOLUTE)
-
-    Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
-
-    0x20000000   0x080013d4   0x00000013   Data   RW           94    .data               Matos.lib(initialisation.o)
-    0x20000013   0x080013e7   0x00000001   PAD
-    0x20000014   0x080013e8   0x00000018   Data   RW          214    .data               Matos.lib(fonctiontimer.o)
-    0x2000002c   0x08001400   0x00000060   Data   RW          306    .data               Matos.lib(warning.o)
-    0x2000008c   0x08001460   0x00000004   Data   RW          392    .data               Matos.lib(timer_systick_1.o)
-    0x20000090        -       0x00000400   Zero   RW           10    STACK               startup_stm32f10x_cl.o
-
-
-==============================================================================
-
-Image component sizes
-
-
-      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   Object Name
-
-        10          0          0          0          0        400   principale.o
-        36          8        336          0       1024        868   startup_stm32f10x_cl.o
-       396         32          0          0          0       6745   system_stm32f10x.o
-
-    ----------------------------------------------------------------------
-       444         40        368          0       1024       8013   Object Totals
-         0          0         32          0          0          0   (incl. Generated)
-         2          0          0          0          0          0   (incl. Padding)
-
-    ----------------------------------------------------------------------
-
-      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   Library Member Name
-
-       212         18          0          0          0        464   foncasm.o
-       584        104          0         24          0       3485   fonctiontimer.o
-      1416        160          0         19          0     225320   initialisation.o
-       364         18          0          0          0       2487   pilote_io_1.o
-       324         30          0          4          0       2509   timer_systick_1.o
-         0          0          0         96          0        582   warning.o
-         0          0          0          0          0          0   entry.o
-         0          0          0          0          0          0   entry10a.o
-         0          0          0          0          0          0   entry11a.o
-         8          4          0          0          0          0   entry2.o
-         4          0          0          0          0          0   entry5.o
-         0          0          0          0          0          0   entry7b.o
-         0          0          0          0          0          0   entry8b.o
-         8          4          0          0          0          0   entry9a.o
-        30          0          0          0          0          0   handlers.o
-        36          8          0          0          0         68   init.o
-         0          0          0          0          0          0   iusefp.o
-        30          0          0          0          0         68   llshl.o
-        32          0          0          0          0         68   llushr.o
-        48          0          0          0          0         68   cdcmple.o
-        48          0          0          0          0         68   cdrcmple.o
-        56          0          0          0          0         88   d2f.o
-       222          0          0          0          0        100   ddiv.o
-       186          0          0          0          0        176   depilogue.o
-       228          0          0          0          0         96   dmul.o
-        38          0          0          0          0         68   f2d.o
-       124          0          0          0          0         88   fdiv.o
-       110          0          0          0          0        168   fepilogue.o
-        40          0          0          0          0         68   ffixui.o
-        10          0          0          0          0         68   ffltui.o
-       100          0          0          0          0         76   fmul.o
-
-    ----------------------------------------------------------------------
-      4264        346          0        144          0     236183   Library Totals
-         6          0          0          1          0          0   (incl. Padding)
-
-    ----------------------------------------------------------------------
-
-      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   Library Name
-
-      2900        330          0        143          0     234847   Matos.lib
-       148         16          0          0          0        204   mc_w.l
-      1210          0          0          0          0       1132   mf_w.l
-
-    ----------------------------------------------------------------------
-      4264        346          0        144          0     236183   Library Totals
-
-    ----------------------------------------------------------------------
-
-==============================================================================
-
-
-      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   
-
-      4708        386        368        144       1024     242580   Grand Totals
-      4708        386        368        144       1024     242580   ELF Image Totals
-      4708        386        368        144          0          0   ROM Totals
-
-==============================================================================
-
-    Total RO  Size (Code + RO Data)                 5076 (   4.96kB)
-    Total RW  Size (RW Data + ZI Data)              1168 (   1.14kB)
-    Total ROM Size (Code + RO Data + RW Data)       5220 (   5.10kB)
-
-==============================================================================
-
diff --git a/Listings/Simu_Etape0.map b/Listings/Simu_Etape0.map
deleted file mode 100644
index aa6c28a..0000000
--- a/Listings/Simu_Etape0.map
+++ /dev/null
@@ -1,896 +0,0 @@
-Component: ARM Compiler 5.06 update 5 (build 528) Tool: armlink [4d35e2]
-
-==============================================================================
-
-Section Cross References
-
-    principale.o(moncode) refers to initialisation.o(i.Init_Cible) for Init_Cible
-    stm32f10x_rcc.o(i.RCC_GetClocksFreq) refers to stm32f10x_rcc.o(.data) for APBAHBPrescTable
-    stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp) refers to stm32f10x_rcc.o(i.RCC_GetFlagStatus) for RCC_GetFlagStatus
-    stm32f10x_spi.o(i.I2S_Init) refers to stm32f10x_rcc.o(i.RCC_GetClocksFreq) for RCC_GetClocksFreq
-    stm32f10x_spi.o(i.SPI_I2S_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd
-    stm32f10x_spi.o(i.SPI_I2S_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd
-    stm32f10x_tim.o(i.TIM_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd
-    stm32f10x_tim.o(i.TIM_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd
-    stm32f10x_tim.o(i.TIM_ETRClockMode1Config) refers to stm32f10x_tim.o(i.TIM_ETRConfig) for TIM_ETRConfig
-    stm32f10x_tim.o(i.TIM_ETRClockMode2Config) refers to stm32f10x_tim.o(i.TIM_ETRConfig) for TIM_ETRConfig
-    stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TI1_Config) for TI1_Config
-    stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC1Prescaler) for TIM_SetIC1Prescaler
-    stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TI2_Config) for TI2_Config
-    stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC2Prescaler) for TIM_SetIC2Prescaler
-    stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TI3_Config) for TI3_Config
-    stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC3Prescaler) for TIM_SetIC3Prescaler
-    stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TI4_Config) for TI4_Config
-    stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC4Prescaler) for TIM_SetIC4Prescaler
-    stm32f10x_tim.o(i.TIM_ITRxExternalClockConfig) refers to stm32f10x_tim.o(i.TIM_SelectInputTrigger) for TIM_SelectInputTrigger
-    stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TI1_Config) for TI1_Config
-    stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TIM_SetIC1Prescaler) for TIM_SetIC1Prescaler
-    stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TI2_Config) for TI2_Config
-    stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TIM_SetIC2Prescaler) for TIM_SetIC2Prescaler
-    stm32f10x_tim.o(i.TIM_TIxExternalClockConfig) refers to stm32f10x_tim.o(i.TI2_Config) for TI2_Config
-    stm32f10x_tim.o(i.TIM_TIxExternalClockConfig) refers to stm32f10x_tim.o(i.TI1_Config) for TI1_Config
-    stm32f10x_tim.o(i.TIM_TIxExternalClockConfig) refers to stm32f10x_tim.o(i.TIM_SelectInputTrigger) for TIM_SelectInputTrigger
-    dma_stm32f10x.o(i.DMA1_Channel1_IRQHandler) refers to dma_stm32f10x.o(i.DMA1_Channel1_Event) for DMA1_Channel1_Event
-    dma_stm32f10x.o(i.DMA1_Channel2_IRQHandler) refers to dma_stm32f10x.o(i.DMA1_Channel2_Event) for DMA1_Channel2_Event
-    dma_stm32f10x.o(i.DMA1_Channel3_IRQHandler) refers to dma_stm32f10x.o(i.DMA1_Channel3_Event) for DMA1_Channel3_Event
-    dma_stm32f10x.o(i.DMA1_Channel4_IRQHandler) refers to dma_stm32f10x.o(i.DMA1_Channel4_Event) for DMA1_Channel4_Event
-    dma_stm32f10x.o(i.DMA1_Channel5_IRQHandler) refers to dma_stm32f10x.o(i.DMA1_Channel5_Event) for DMA1_Channel5_Event
-    dma_stm32f10x.o(i.DMA1_Channel6_IRQHandler) refers to dma_stm32f10x.o(i.DMA1_Channel6_Event) for DMA1_Channel6_Event
-    dma_stm32f10x.o(i.DMA1_Channel7_IRQHandler) refers to dma_stm32f10x.o(i.DMA1_Channel7_Event) for DMA1_Channel7_Event
-    dma_stm32f10x.o(i.DMA_ChannelInitialize) refers to dma_stm32f10x.o(i.__NVIC_ClearPendingIRQ) for __NVIC_ClearPendingIRQ
-    dma_stm32f10x.o(i.DMA_ChannelInitialize) refers to dma_stm32f10x.o(i.__NVIC_EnableIRQ) for __NVIC_EnableIRQ
-    dma_stm32f10x.o(i.DMA_ChannelInitialize) refers to dma_stm32f10x.o(.data) for DMA1_Channel
-    dma_stm32f10x.o(i.DMA_ChannelUninitialize) refers to dma_stm32f10x.o(i.__NVIC_DisableIRQ) for __NVIC_DisableIRQ
-    dma_stm32f10x.o(i.DMA_ChannelUninitialize) refers to dma_stm32f10x.o(.data) for DMA1_Channel
-    gpio_stm32f10x.o(i.GPIO_PinConfigure) refers to gpio_stm32f10x.o(i.GPIO_GetPortClockState) for GPIO_GetPortClockState
-    gpio_stm32f10x.o(i.GPIO_PinConfigure) refers to gpio_stm32f10x.o(i.GPIO_PortClock) for GPIO_PortClock
-    startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(STACK) for __initial_sp
-    startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(.text) for Reset_Handler
-    startup_stm32f10x_md.o(RESET) refers to timer_systick_1.o(i.SysTick_Handler) for SysTick_Handler
-    startup_stm32f10x_md.o(RESET) refers to dma_stm32f10x.o(i.DMA1_Channel1_IRQHandler) for DMA1_Channel1_IRQHandler
-    startup_stm32f10x_md.o(RESET) refers to dma_stm32f10x.o(i.DMA1_Channel2_IRQHandler) for DMA1_Channel2_IRQHandler
-    startup_stm32f10x_md.o(RESET) refers to dma_stm32f10x.o(i.DMA1_Channel3_IRQHandler) for DMA1_Channel3_IRQHandler
-    startup_stm32f10x_md.o(RESET) refers to dma_stm32f10x.o(i.DMA1_Channel4_IRQHandler) for DMA1_Channel4_IRQHandler
-    startup_stm32f10x_md.o(RESET) refers to dma_stm32f10x.o(i.DMA1_Channel5_IRQHandler) for DMA1_Channel5_IRQHandler
-    startup_stm32f10x_md.o(RESET) refers to dma_stm32f10x.o(i.DMA1_Channel6_IRQHandler) for DMA1_Channel6_IRQHandler
-    startup_stm32f10x_md.o(RESET) refers to dma_stm32f10x.o(i.DMA1_Channel7_IRQHandler) for DMA1_Channel7_IRQHandler
-    startup_stm32f10x_md.o(RESET) refers to fonctiontimer.o(i.TIM1_UP_IRQHandler) for TIM1_UP_IRQHandler
-    startup_stm32f10x_md.o(RESET) refers to fonctiontimer.o(i.TIM1_CC_IRQHandler) for TIM1_CC_IRQHandler
-    startup_stm32f10x_md.o(RESET) refers to fonctiontimer.o(i.TIM2_IRQHandler) for TIM2_IRQHandler
-    startup_stm32f10x_md.o(RESET) refers to fonctiontimer.o(i.TIM3_IRQHandler) for TIM3_IRQHandler
-    startup_stm32f10x_md.o(RESET) refers to fonctiontimer.o(i.TIM4_IRQHandler) for TIM4_IRQHandler
-    startup_stm32f10x_md.o(.text) refers to system_stm32f10x.o(i.SystemInit) for SystemInit
-    startup_stm32f10x_md.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main
-    system_stm32f10x.o(i.SetSysClock) refers to system_stm32f10x.o(i.SetSysClockTo72) for SetSysClockTo72
-    system_stm32f10x.o(i.SystemCoreClockUpdate) refers to system_stm32f10x.o(.data) for SystemCoreClock
-    system_stm32f10x.o(i.SystemInit) refers to system_stm32f10x.o(i.SetSysClock) for SetSysClock
-    initialisation.o(i.Init_Cible) refers to initialisation.o(i.Init_Port) for Init_Port
-    initialisation.o(i.Init_Cible) refers to initialisation.o(i.Init_Dot) for Init_Dot
-    initialisation.o(i.Init_Cible) refers to initialisation.o(i.Init_Timer1) for Init_Timer1
-    initialisation.o(i.Init_Cible) refers to initialisation.o(i.Init_Timer2_PWM) for Init_Timer2_PWM
-    initialisation.o(i.Init_Cible) refers to initialisation.o(i.Init_Timer3_Slave) for Init_Timer3_Slave
-    initialisation.o(i.Init_Cible) refers to initialisation.o(i.Init_Timer4) for Init_Timer4
-    initialisation.o(i.Init_Cible) refers to spi.o(i.Config_SPI) for Config_SPI
-    initialisation.o(i.Init_Cible) refers to foncasm.o(moncode) for Envoie192Boucle
-    initialisation.o(i.Init_Cible) refers to pilote_io_1.o(i.Port_IO_Set) for Port_IO_Set
-    initialisation.o(i.Init_Cible) refers to pilote_io_1.o(i.Port_IO_Reset) for Port_IO_Reset
-    initialisation.o(i.Init_Cible) refers to timer_systick_1.o(i.Systick_Period) for Systick_Period
-    initialisation.o(i.Init_Cible) refers to timer_systick_1.o(i.Systick_Prio_IT) for Systick_Prio_IT
-    initialisation.o(i.Init_Cible) refers to initialisation.o(.data) for PrtSurImage
-    initialisation.o(i.Init_Cible) refers to warning.o(.data) for warning
-    initialisation.o(i.Init_Cible) refers to fonctiontimer.o(i.Anim) for Anim
-    initialisation.o(i.Init_Dot) refers to pilote_io_1.o(i.Port_IO_Set) for Port_IO_Set
-    initialisation.o(i.Init_Dot) refers to pilote_io_1.o(i.Port_IO_Reset) for Port_IO_Reset
-    initialisation.o(i.Init_Dot) refers to foncasm.o(moncode) for Envoie96Dot
-    initialisation.o(i.Init_Dot) refers to initialisation.o(.data) for CinqDots
-    initialisation.o(i.Init_Port) refers to pilote_io_1.o(i.GPIO_Configure) for GPIO_Configure
-    initialisation.o(i.Init_Port_SPI) refers to pilote_io_1.o(i.GPIO_Configure) for GPIO_Configure
-    initialisation.o(i.Init_Timer1) refers to ffltui.o(.text) for __aeabi_ui2f
-    initialisation.o(i.Init_Timer1) refers to f2d.o(.text) for __aeabi_f2d
-    initialisation.o(i.Init_Timer1) refers to dmul.o(.text) for __aeabi_dmul
-    initialisation.o(i.Init_Timer1) refers to ddiv.o(.text) for __aeabi_ddiv
-    initialisation.o(i.Init_Timer1) refers to d2f.o(.text) for __aeabi_d2f
-    initialisation.o(i.Init_Timer1) refers to fmul.o(.text) for __aeabi_fmul
-    initialisation.o(i.Init_Timer1) refers to cdcmple.o(.text) for __aeabi_cdcmple
-    initialisation.o(i.Init_Timer1) refers to cdrcmple.o(.text) for __aeabi_cdrcmple
-    initialisation.o(i.Init_Timer1) refers to ffixui.o(.text) for __aeabi_f2uiz
-    initialisation.o(i.Init_Timer2_PWM) refers to f2d.o(.text) for __aeabi_f2d
-    initialisation.o(i.Init_Timer2_PWM) refers to ddiv.o(.text) for __aeabi_ddiv
-    initialisation.o(i.Init_Timer2_PWM) refers to d2f.o(.text) for __aeabi_d2f
-    initialisation.o(i.Init_Timer2_PWM) refers to ffltui.o(.text) for __aeabi_ui2f
-    initialisation.o(i.Init_Timer2_PWM) refers to fmul.o(.text) for __aeabi_fmul
-    initialisation.o(i.Init_Timer2_PWM) refers to ffixui.o(.text) for __aeabi_f2uiz
-    initialisation.o(i.Init_Timer2_PWM) refers to fdiv.o(.text) for __aeabi_fdiv
-    fonctiontimer.o(i.Anim) refers to fonctiontimer.o(.data) for ImageEnCours
-    fonctiontimer.o(i.TIM1_CC_IRQHandler) refers to fonctiontimer.o(.data) for SecteurEnCours
-    fonctiontimer.o(i.TIM1_UP_IRQHandler) refers to foncasm.o(moncode) for Envoie192Boucle
-    fonctiontimer.o(i.TIM1_UP_IRQHandler) refers to fonctiontimer.o(.data) for VitesseSuffisante
-    fonctiontimer.o(i.TIM1_UP_IRQHandler) refers to warning.o(.data) for warning
-    fonctiontimer.o(i.TIM1_UP_IRQHandler) refers to initialisation.o(.data) for DataSend
-    fonctiontimer.o(i.TIM3_IRQHandler) refers to pilote_io_1.o(i.Port_IO_Set) for Port_IO_Set
-    fonctiontimer.o(i.TIM3_IRQHandler) refers to pilote_io_1.o(i.Port_IO_Reset) for Port_IO_Reset
-    fonctiontimer.o(i.TIM3_IRQHandler) refers to initialisation.o(.data) for DataSend
-    fonctiontimer.o(i.TIM4_IRQHandler) refers to spi.o(i.SendSPI) for SendSPI
-    fonctiontimer.o(i.TIM4_IRQHandler) refers to fonctiontimer.o(.data) for SecteurEnCours
-    fonctiontimer.o(i.TIM4_IRQHandler) refers to initialisation.o(.data) for PrtSurImage
-    spi.o(i.Config_SPI) refers to stm32f10x_spi.o(i.SPI_Init) for SPI_Init
-    spi.o(i.Config_SPI) refers to stm32f10x_spi.o(i.SPI_Cmd) for SPI_Cmd
-    spi.o(i.Config_SPI) refers to spi.o(.bss) for SPI_InitStructure
-    spi.o(i.SendSPI) refers to stm32f10x_spi.o(i.SPI_I2S_GetFlagStatus) for SPI_I2S_GetFlagStatus
-    spi.o(i.SendSPI) refers to spi.o(i.SPI_I2S_SendData16) for SPI_I2S_SendData16
-    foncasm.o(moncode) refers to initialisation.o(.data) for BarretEnCours
-    timer_systick_1.o(i.SysTick_Handler) refers to timer_systick_1.o(.data) for Ptr_Systick
-    timer_systick_1.o(i.Systick_Period) refers to fmul.o(.text) for __aeabi_fmul
-    timer_systick_1.o(i.Systick_Period) refers to f2d.o(.text) for __aeabi_f2d
-    timer_systick_1.o(i.Systick_Period) refers to ddiv.o(.text) for __aeabi_ddiv
-    timer_systick_1.o(i.Systick_Period) refers to d2f.o(.text) for __aeabi_d2f
-    timer_systick_1.o(i.Systick_Period) refers to ffixui.o(.text) for __aeabi_f2uiz
-    timer_systick_1.o(i.Systick_Period) refers to ffltui.o(.text) for __aeabi_ui2f
-    timer_systick_1.o(i.Systick_Period) refers to fdiv.o(.text) for __aeabi_fdiv
-    timer_systick_1.o(i.Systick_Period) refers to dmul.o(.text) for __aeabi_dmul
-    timer_systick_1.o(i.Systick_Period) refers to cdrcmple.o(.text) for __aeabi_cdrcmple
-    timer_systick_1.o(i.Systick_Prio_IT) refers to timer_systick_1.o(.data) for Ptr_Systick
-    entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000D) for __rt_final_cpp
-    entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$0000000F) for __rt_final_exit
-    entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock
-    entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init
-    entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry9a.o(.ARM.Collect$$$$0000000B) for _main_init
-    entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry5.o(.ARM.Collect$$$$00000004) for _main_scatterload
-    entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry2.o(.ARM.Collect$$$$00000001) for _main_stk
-    fmul.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
-    fdiv.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
-    fdiv.o(.text) refers to fepilogue.o(.text) for _float_round
-    dmul.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
-    dmul.o(.text) refers to depilogue.o(.text) for _double_epilogue
-    ddiv.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
-    ddiv.o(.text) refers to depilogue.o(.text) for _double_round
-    ffltui.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
-    ffltui.o(.text) refers to fepilogue.o(.text) for _float_epilogue
-    ffixui.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
-    f2d.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
-    cdcmple.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
-    cdrcmple.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
-    d2f.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
-    d2f.o(.text) refers to fepilogue.o(.text) for _float_round
-    entry2.o(.ARM.Collect$$$$00000001) refers to entry2.o(.ARM.Collect$$$$00002712) for __lit__00000000
-    entry2.o(.ARM.Collect$$$$00002712) refers to startup_stm32f10x_md.o(STACK) for __initial_sp
-    entry2.o(__vectab_stack_and_reset_area) refers to startup_stm32f10x_md.o(STACK) for __initial_sp
-    entry2.o(__vectab_stack_and_reset_area) refers to entry.o(.ARM.Collect$$$$00000000) for __main
-    entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload
-    entry9a.o(.ARM.Collect$$$$0000000B) refers to principale.o(moncode) for main
-    entry9b.o(.ARM.Collect$$$$0000000C) refers to principale.o(moncode) for main
-    depilogue.o(.text) refers to llshl.o(.text) for __aeabi_llsl
-    depilogue.o(.text) refers to llushr.o(.text) for __aeabi_llsr
-    init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload
-
-
-==============================================================================
-
-Removing Unused input sections from the image.
-
-    Removing principale.o(mesdonnees), (0 bytes).
-    Removing fonctionetape.o(MesDonnees), (0 bytes).
-    Removing fonctionetape.o(moncode), (0 bytes).
-    Removing misc.o(.rev16_text), (4 bytes).
-    Removing misc.o(.revsh_text), (4 bytes).
-    Removing misc.o(.rrx_text), (6 bytes).
-    Removing misc.o(i.NVIC_Init), (112 bytes).
-    Removing misc.o(i.NVIC_PriorityGroupConfig), (20 bytes).
-    Removing misc.o(i.NVIC_SetVectorTable), (20 bytes).
-    Removing misc.o(i.NVIC_SystemLPConfig), (32 bytes).
-    Removing misc.o(i.SysTick_CLKSourceConfig), (40 bytes).
-    Removing stm32f10x_rcc.o(.rev16_text), (4 bytes).
-    Removing stm32f10x_rcc.o(.revsh_text), (4 bytes).
-    Removing stm32f10x_rcc.o(.rrx_text), (6 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_ADCCLKConfig), (24 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_AHBPeriphClockCmd), (32 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd), (32 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd), (32 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd), (32 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd), (32 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_AdjustHSICalibrationValue), (24 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_BackupResetCmd), (12 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_ClearFlag), (20 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_ClearITPendingBit), (12 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_ClockSecuritySystemCmd), (12 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_DeInit), (76 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_GetClocksFreq), (212 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_GetFlagStatus), (60 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_GetITStatus), (24 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_GetSYSCLKSource), (16 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_HCLKConfig), (24 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_HSEConfig), (76 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_HSICmd), (12 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_ITConfig), (32 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_LSEConfig), (52 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_LSICmd), (12 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_MCOConfig), (12 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_PCLK1Config), (24 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_PCLK2Config), (24 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_PLLCmd), (12 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_PLLConfig), (28 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_RTCCLKCmd), (12 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_RTCCLKConfig), (16 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_SYSCLKConfig), (24 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_USBCLKConfig), (12 bytes).
-    Removing stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp), (56 bytes).
-    Removing stm32f10x_rcc.o(.data), (20 bytes).
-    Removing stm32f10x_spi.o(.rev16_text), (4 bytes).
-    Removing stm32f10x_spi.o(.revsh_text), (4 bytes).
-    Removing stm32f10x_spi.o(.rrx_text), (6 bytes).
-    Removing stm32f10x_spi.o(i.I2S_Cmd), (24 bytes).
-    Removing stm32f10x_spi.o(i.I2S_Init), (232 bytes).
-    Removing stm32f10x_spi.o(i.I2S_StructInit), (20 bytes).
-    Removing stm32f10x_spi.o(i.SPI_BiDirectionalLineConfig), (28 bytes).
-    Removing stm32f10x_spi.o(i.SPI_CalculateCRC), (24 bytes).
-    Removing stm32f10x_spi.o(i.SPI_DataSizeConfig), (18 bytes).
-    Removing stm32f10x_spi.o(i.SPI_GetCRC), (16 bytes).
-    Removing stm32f10x_spi.o(i.SPI_GetCRCPolynomial), (6 bytes).
-    Removing stm32f10x_spi.o(i.SPI_I2S_ClearFlag), (6 bytes).
-    Removing stm32f10x_spi.o(i.SPI_I2S_ClearITPendingBit), (20 bytes).
-    Removing stm32f10x_spi.o(i.SPI_I2S_DMACmd), (18 bytes).
-    Removing stm32f10x_spi.o(i.SPI_I2S_DeInit), (88 bytes).
-    Removing stm32f10x_spi.o(i.SPI_I2S_GetITStatus), (52 bytes).
-    Removing stm32f10x_spi.o(i.SPI_I2S_ITConfig), (32 bytes).
-    Removing stm32f10x_spi.o(i.SPI_I2S_ReceiveData), (6 bytes).
-    Removing stm32f10x_spi.o(i.SPI_I2S_SendData), (4 bytes).
-    Removing stm32f10x_spi.o(i.SPI_NSSInternalSoftwareConfig), (30 bytes).
-    Removing stm32f10x_spi.o(i.SPI_SSOutputCmd), (24 bytes).
-    Removing stm32f10x_spi.o(i.SPI_StructInit), (24 bytes).
-    Removing stm32f10x_spi.o(i.SPI_TransmitCRC), (10 bytes).
-    Removing stm32f10x_tim.o(.rev16_text), (4 bytes).
-    Removing stm32f10x_tim.o(.revsh_text), (4 bytes).
-    Removing stm32f10x_tim.o(.rrx_text), (6 bytes).
-    Removing stm32f10x_tim.o(i.TI1_Config), (128 bytes).
-    Removing stm32f10x_tim.o(i.TI2_Config), (152 bytes).
-    Removing stm32f10x_tim.o(i.TI3_Config), (144 bytes).
-    Removing stm32f10x_tim.o(i.TI4_Config), (152 bytes).
-    Removing stm32f10x_tim.o(i.TIM_ARRPreloadConfig), (24 bytes).
-    Removing stm32f10x_tim.o(i.TIM_BDTRConfig), (32 bytes).
-    Removing stm32f10x_tim.o(i.TIM_BDTRStructInit), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_CCPreloadControl), (24 bytes).
-    Removing stm32f10x_tim.o(i.TIM_CCxCmd), (30 bytes).
-    Removing stm32f10x_tim.o(i.TIM_CCxNCmd), (30 bytes).
-    Removing stm32f10x_tim.o(i.TIM_ClearFlag), (6 bytes).
-    Removing stm32f10x_tim.o(i.TIM_ClearITPendingBit), (6 bytes).
-    Removing stm32f10x_tim.o(i.TIM_ClearOC1Ref), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_ClearOC2Ref), (24 bytes).
-    Removing stm32f10x_tim.o(i.TIM_ClearOC3Ref), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_ClearOC4Ref), (24 bytes).
-    Removing stm32f10x_tim.o(i.TIM_Cmd), (24 bytes).
-    Removing stm32f10x_tim.o(i.TIM_CounterModeConfig), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_CtrlPWMOutputs), (30 bytes).
-    Removing stm32f10x_tim.o(i.TIM_DMACmd), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_DMAConfig), (10 bytes).
-    Removing stm32f10x_tim.o(i.TIM_DeInit), (488 bytes).
-    Removing stm32f10x_tim.o(i.TIM_ETRClockMode1Config), (54 bytes).
-    Removing stm32f10x_tim.o(i.TIM_ETRClockMode2Config), (32 bytes).
-    Removing stm32f10x_tim.o(i.TIM_ETRConfig), (28 bytes).
-    Removing stm32f10x_tim.o(i.TIM_EncoderInterfaceConfig), (66 bytes).
-    Removing stm32f10x_tim.o(i.TIM_ForcedOC1Config), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_ForcedOC2Config), (26 bytes).
-    Removing stm32f10x_tim.o(i.TIM_ForcedOC3Config), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_ForcedOC4Config), (26 bytes).
-    Removing stm32f10x_tim.o(i.TIM_GenerateEvent), (4 bytes).
-    Removing stm32f10x_tim.o(i.TIM_GetCapture1), (6 bytes).
-    Removing stm32f10x_tim.o(i.TIM_GetCapture2), (6 bytes).
-    Removing stm32f10x_tim.o(i.TIM_GetCapture3), (6 bytes).
-    Removing stm32f10x_tim.o(i.TIM_GetCapture4), (8 bytes).
-    Removing stm32f10x_tim.o(i.TIM_GetCounter), (6 bytes).
-    Removing stm32f10x_tim.o(i.TIM_GetFlagStatus), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_GetITStatus), (34 bytes).
-    Removing stm32f10x_tim.o(i.TIM_GetPrescaler), (6 bytes).
-    Removing stm32f10x_tim.o(i.TIM_ICInit), (172 bytes).
-    Removing stm32f10x_tim.o(i.TIM_ICStructInit), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_ITConfig), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_ITRxExternalClockConfig), (24 bytes).
-    Removing stm32f10x_tim.o(i.TIM_InternalClockConfig), (12 bytes).
-    Removing stm32f10x_tim.o(i.TIM_OC1FastConfig), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_OC1Init), (152 bytes).
-    Removing stm32f10x_tim.o(i.TIM_OC1NPolarityConfig), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_OC1PolarityConfig), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_OC1PreloadConfig), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_OC2FastConfig), (26 bytes).
-    Removing stm32f10x_tim.o(i.TIM_OC2Init), (164 bytes).
-    Removing stm32f10x_tim.o(i.TIM_OC2NPolarityConfig), (26 bytes).
-    Removing stm32f10x_tim.o(i.TIM_OC2PolarityConfig), (26 bytes).
-    Removing stm32f10x_tim.o(i.TIM_OC2PreloadConfig), (26 bytes).
-    Removing stm32f10x_tim.o(i.TIM_OC3FastConfig), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_OC3Init), (160 bytes).
-    Removing stm32f10x_tim.o(i.TIM_OC3NPolarityConfig), (26 bytes).
-    Removing stm32f10x_tim.o(i.TIM_OC3PolarityConfig), (26 bytes).
-    Removing stm32f10x_tim.o(i.TIM_OC3PreloadConfig), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_OC4FastConfig), (26 bytes).
-    Removing stm32f10x_tim.o(i.TIM_OC4Init), (124 bytes).
-    Removing stm32f10x_tim.o(i.TIM_OC4PolarityConfig), (26 bytes).
-    Removing stm32f10x_tim.o(i.TIM_OC4PreloadConfig), (26 bytes).
-    Removing stm32f10x_tim.o(i.TIM_OCStructInit), (20 bytes).
-    Removing stm32f10x_tim.o(i.TIM_PWMIConfig), (124 bytes).
-    Removing stm32f10x_tim.o(i.TIM_PrescalerConfig), (6 bytes).
-    Removing stm32f10x_tim.o(i.TIM_SelectCCDMA), (24 bytes).
-    Removing stm32f10x_tim.o(i.TIM_SelectCOM), (24 bytes).
-    Removing stm32f10x_tim.o(i.TIM_SelectHallSensor), (24 bytes).
-    Removing stm32f10x_tim.o(i.TIM_SelectInputTrigger), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_SelectMasterSlaveMode), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_SelectOCxM), (82 bytes).
-    Removing stm32f10x_tim.o(i.TIM_SelectOnePulseMode), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_SelectOutputTrigger), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_SelectSlaveMode), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_SetAutoreload), (4 bytes).
-    Removing stm32f10x_tim.o(i.TIM_SetClockDivision), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_SetCompare1), (4 bytes).
-    Removing stm32f10x_tim.o(i.TIM_SetCompare2), (4 bytes).
-    Removing stm32f10x_tim.o(i.TIM_SetCompare3), (4 bytes).
-    Removing stm32f10x_tim.o(i.TIM_SetCompare4), (6 bytes).
-    Removing stm32f10x_tim.o(i.TIM_SetCounter), (4 bytes).
-    Removing stm32f10x_tim.o(i.TIM_SetIC1Prescaler), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_SetIC2Prescaler), (26 bytes).
-    Removing stm32f10x_tim.o(i.TIM_SetIC3Prescaler), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_SetIC4Prescaler), (26 bytes).
-    Removing stm32f10x_tim.o(i.TIM_TIxExternalClockConfig), (62 bytes).
-    Removing stm32f10x_tim.o(i.TIM_TimeBaseInit), (164 bytes).
-    Removing stm32f10x_tim.o(i.TIM_TimeBaseStructInit), (18 bytes).
-    Removing stm32f10x_tim.o(i.TIM_UpdateDisableConfig), (24 bytes).
-    Removing stm32f10x_tim.o(i.TIM_UpdateRequestConfig), (24 bytes).
-    Removing dma_stm32f10x.o(.rev16_text), (4 bytes).
-    Removing dma_stm32f10x.o(.revsh_text), (4 bytes).
-    Removing dma_stm32f10x.o(.rrx_text), (6 bytes).
-    Removing dma_stm32f10x.o(i.DMA_ChannelInitialize), (256 bytes).
-    Removing dma_stm32f10x.o(i.DMA_ChannelUninitialize), (188 bytes).
-    Removing dma_stm32f10x.o(i.__NVIC_ClearPendingIRQ), (28 bytes).
-    Removing dma_stm32f10x.o(i.__NVIC_DisableIRQ), (60 bytes).
-    Removing dma_stm32f10x.o(i.__NVIC_EnableIRQ), (26 bytes).
-    Removing dma_stm32f10x.o(.data), (1 bytes).
-    Removing gpio_stm32f10x.o(.rev16_text), (4 bytes).
-    Removing gpio_stm32f10x.o(.revsh_text), (4 bytes).
-    Removing gpio_stm32f10x.o(.rrx_text), (6 bytes).
-    Removing gpio_stm32f10x.o(i.GPIO_AFConfigure), (156 bytes).
-    Removing gpio_stm32f10x.o(i.GPIO_GetPortClockState), (152 bytes).
-    Removing gpio_stm32f10x.o(i.GPIO_PinConfigure), (120 bytes).
-    Removing gpio_stm32f10x.o(i.GPIO_PortClock), (316 bytes).
-    Removing startup_stm32f10x_md.o(HEAP), (512 bytes).
-    Removing system_stm32f10x.o(.rev16_text), (4 bytes).
-    Removing system_stm32f10x.o(.revsh_text), (4 bytes).
-    Removing system_stm32f10x.o(.rrx_text), (6 bytes).
-    Removing system_stm32f10x.o(i.SystemCoreClockUpdate), (164 bytes).
-    Removing system_stm32f10x.o(.data), (20 bytes).
-    Removing initialisation.o(.rev16_text), (4 bytes).
-    Removing initialisation.o(.revsh_text), (4 bytes).
-    Removing initialisation.o(.rrx_text), (6 bytes).
-    Removing initialisation.o(i.Init_Port_SPI), (76 bytes).
-    Removing fonctiontimer.o(.rev16_text), (4 bytes).
-    Removing fonctiontimer.o(.revsh_text), (4 bytes).
-    Removing fonctiontimer.o(.rrx_text), (6 bytes).
-    Removing fonctiontimer.o(i.Run_Timer1), (20 bytes).
-    Removing fonctiontimer.o(i.Run_Timer2), (18 bytes).
-    Removing fonctiontimer.o(i.Run_Timer3), (20 bytes).
-    Removing fonctiontimer.o(i.Run_Timer4), (20 bytes).
-    Removing fonctiontimer.o(i.Stop_Timer1), (20 bytes).
-    Removing fonctiontimer.o(i.Stop_Timer2), (18 bytes).
-    Removing fonctiontimer.o(i.Stop_Timer3), (20 bytes).
-    Removing fonctiontimer.o(i.Stop_Timer4), (20 bytes).
-    Removing spi.o(.rev16_text), (4 bytes).
-    Removing spi.o(.revsh_text), (4 bytes).
-    Removing spi.o(.rrx_text), (6 bytes).
-    Removing foncasm.o(muu), (0 bytes).
-    Removing pilote_io_1.o(.rev16_text), (4 bytes).
-    Removing pilote_io_1.o(.revsh_text), (4 bytes).
-    Removing pilote_io_1.o(.rrx_text), (6 bytes).
-    Removing pilote_io_1.o(i.Port_IO_Blink), (16 bytes).
-    Removing pilote_io_1.o(i.Port_IO_Init_Input), (74 bytes).
-    Removing pilote_io_1.o(i.Port_IO_Init_Input_Analog), (46 bytes).
-    Removing pilote_io_1.o(i.Port_IO_Init_Output), (74 bytes).
-    Removing pilote_io_1.o(i.Port_IO_Read), (12 bytes).
-    Removing timer_systick_1.o(.rev16_text), (4 bytes).
-    Removing timer_systick_1.o(.revsh_text), (4 bytes).
-    Removing timer_systick_1.o(.rrx_text), (6 bytes).
-
-216 unused section(s) (total 8411 bytes) removed from the image.
-
-==============================================================================
-
-Image Symbol Table
-
-    Local Symbols
-
-    Symbol Name                              Value     Ov Type        Size  Object(Section)
-
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry7a.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry8b.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry9a.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry11b.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry10b.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry10a.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry7b.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry11a.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry9b.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry8a.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry5.o ABSOLUTE
-    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry2.o ABSOLUTE
-    ../clib/microlib/longlong.c              0x00000000   Number         0  llushr.o ABSOLUTE
-    ../clib/microlib/longlong.c              0x00000000   Number         0  llshl.o ABSOLUTE
-    ../clib/microlib/stubs.s                 0x00000000   Number         0  iusefp.o ABSOLUTE
-    ../fplib/microlib/d2f.c                  0x00000000   Number         0  d2f.o ABSOLUTE
-    ../fplib/microlib/f2d.c                  0x00000000   Number         0  f2d.o ABSOLUTE
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-    DMA1_Channel3_Event                      0x080006f1   Thumb Code     2  dma_stm32f10x.o(i.DMA1_Channel3_Event)
-    DMA1_Channel3_IRQHandler                 0x080006f5   Thumb Code    24  dma_stm32f10x.o(i.DMA1_Channel3_IRQHandler)
-    DMA1_Channel4_Event                      0x08000711   Thumb Code     2  dma_stm32f10x.o(i.DMA1_Channel4_Event)
-    DMA1_Channel4_IRQHandler                 0x08000715   Thumb Code    24  dma_stm32f10x.o(i.DMA1_Channel4_IRQHandler)
-    DMA1_Channel5_Event                      0x08000731   Thumb Code     2  dma_stm32f10x.o(i.DMA1_Channel5_Event)
-    DMA1_Channel5_IRQHandler                 0x08000735   Thumb Code    24  dma_stm32f10x.o(i.DMA1_Channel5_IRQHandler)
-    DMA1_Channel6_Event                      0x08000751   Thumb Code     2  dma_stm32f10x.o(i.DMA1_Channel6_Event)
-    DMA1_Channel6_IRQHandler                 0x08000755   Thumb Code    24  dma_stm32f10x.o(i.DMA1_Channel6_IRQHandler)
-    DMA1_Channel7_Event                      0x08000771   Thumb Code     2  dma_stm32f10x.o(i.DMA1_Channel7_Event)
-    DMA1_Channel7_IRQHandler                 0x08000775   Thumb Code    24  dma_stm32f10x.o(i.DMA1_Channel7_IRQHandler)
-    GPIO_Configure                           0x08000791   Thumb Code   314  pilote_io_1.o(i.GPIO_Configure)
-    Init_Cible                               0x080008dd   Thumb Code   218  initialisation.o(i.Init_Cible)
-    Init_Dot                                 0x080009e9   Thumb Code   112  initialisation.o(i.Init_Dot)
-    Init_Port                                0x08000a61   Thumb Code   134  initialisation.o(i.Init_Port)
-    Init_Timer1                              0x08000af1   Thumb Code   336  initialisation.o(i.Init_Timer1)
-    Init_Timer2_PWM                          0x08000c65   Thumb Code   262  initialisation.o(i.Init_Timer2_PWM)
-    Init_Timer3_Slave                        0x08000d81   Thumb Code    94  initialisation.o(i.Init_Timer3_Slave)
-    Init_Timer4                              0x08000df1   Thumb Code   100  initialisation.o(i.Init_Timer4)
-    Port_IO_Reset                            0x08000e65   Thumb Code    16  pilote_io_1.o(i.Port_IO_Reset)
-    Port_IO_Set                              0x08000e75   Thumb Code    16  pilote_io_1.o(i.Port_IO_Set)
-    SPI_Cmd                                  0x08000e85   Thumb Code    24  stm32f10x_spi.o(i.SPI_Cmd)
-    SPI_I2S_GetFlagStatus                    0x08000e9d   Thumb Code    18  stm32f10x_spi.o(i.SPI_I2S_GetFlagStatus)
-    SPI_I2S_SendData16                       0x08000eaf   Thumb Code     4  spi.o(i.SPI_I2S_SendData16)
-    SPI_Init                                 0x08000eb3   Thumb Code    60  stm32f10x_spi.o(i.SPI_Init)
-    SendSPI                                  0x08000ef1   Thumb Code   130  spi.o(i.SendSPI)
-    SysTick_Handler                          0x08001061   Thumb Code    10  timer_systick_1.o(i.SysTick_Handler)
-    SystemInit                               0x08001071   Thumb Code    78  system_stm32f10x.o(i.SystemInit)
-    Systick_Period                           0x080010d1   Thumb Code   256  timer_systick_1.o(i.Systick_Period)
-    Systick_Prio_IT                          0x080011e1   Thumb Code    28  timer_systick_1.o(i.Systick_Prio_IT)
-    TIM1_CC_IRQHandler                       0x08001205   Thumb Code   158  fonctiontimer.o(i.TIM1_CC_IRQHandler)
-    TIM1_UP_IRQHandler                       0x080012b9   Thumb Code   130  fonctiontimer.o(i.TIM1_UP_IRQHandler)
-    TIM2_IRQHandler                          0x0800135d   Thumb Code     4  fonctiontimer.o(i.TIM2_IRQHandler)
-    TIM3_IRQHandler                          0x08001361   Thumb Code    68  fonctiontimer.o(i.TIM3_IRQHandler)
-    TIM4_IRQHandler                          0x080013b1   Thumb Code    90  fonctiontimer.o(i.TIM4_IRQHandler)
-    __scatterload_copy                       0x08001425   Thumb Code    14  handlers.o(i.__scatterload_copy)
-    __scatterload_null                       0x08001433   Thumb Code     2  handlers.o(i.__scatterload_null)
-    __scatterload_zeroinit                   0x08001435   Thumb Code    14  handlers.o(i.__scatterload_zeroinit)
-    main                                     0x08001445   Thumb Code    10  principale.o(moncode)
-    Envoie192Boucle                          0x08001451   Thumb Code   108  foncasm.o(moncode)
-    Envoie96Dot                              0x080014bd   Thumb Code    78  foncasm.o(moncode)
-    Region$$Table$$Base                      0x08001518   Number         0  anon$$obj.o(Region$$Table)
-    Region$$Table$$Limit                     0x08001538   Number         0  anon$$obj.o(Region$$Table)
-    PrtSurImage                              0x20000000   Data           4  initialisation.o(.data)
-    BarretEnCours                            0x20000004   Data           4  initialisation.o(.data)
-    DataSend                                 0x20000008   Data           1  initialisation.o(.data)
-    Angle                                    0x2000000c   Data           4  initialisation.o(.data)
-    CinqDots                                 0x20000010   Data           3  initialisation.o(.data)
-    VitesseSuffisante                        0x20000014   Data           4  fonctiontimer.o(.data)
-    SecteurEnCours                           0x20000018   Data           4  fonctiontimer.o(.data)
-    ImageEnCours                             0x2000001c   Data           4  fonctiontimer.o(.data)
-    increment                                0x20000020   Data           4  fonctiontimer.o(.data)
-    warning                                  0x2000002c   Data          96  warning.o(.data)
-    SPI_InitStructure                        0x20000090   Data          18  spi.o(.bss)
-    __initial_sp                             0x200004a8   Data           0  startup_stm32f10x_md.o(STACK)
-
-
-
-==============================================================================
-
-Memory Map of the image
-
-  Image Entry point : 0x080000ed
-
-  Load Region LR_IROM1 (Base: 0x08000000, Size: 0x000015c8, Max: 0x00020000, ABSOLUTE)
-
-    Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x00001538, Max: 0x00020000, ABSOLUTE)
-
-    Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
-
-    0x08000000   0x08000000   0x000000ec   Data   RO         1219    RESET               startup_stm32f10x_md.o
-    0x080000ec   0x080000ec   0x00000000   Code   RO         1643  * .ARM.Collect$$$$00000000  mc_w.l(entry.o)
-    0x080000ec   0x080000ec   0x00000004   Code   RO         1666    .ARM.Collect$$$$00000001  mc_w.l(entry2.o)
-    0x080000f0   0x080000f0   0x00000004   Code   RO         1669    .ARM.Collect$$$$00000004  mc_w.l(entry5.o)
-    0x080000f4   0x080000f4   0x00000000   Code   RO         1671    .ARM.Collect$$$$00000008  mc_w.l(entry7b.o)
-    0x080000f4   0x080000f4   0x00000000   Code   RO         1673    .ARM.Collect$$$$0000000A  mc_w.l(entry8b.o)
-    0x080000f4   0x080000f4   0x00000008   Code   RO         1674    .ARM.Collect$$$$0000000B  mc_w.l(entry9a.o)
-    0x080000fc   0x080000fc   0x00000000   Code   RO         1676    .ARM.Collect$$$$0000000D  mc_w.l(entry10a.o)
-    0x080000fc   0x080000fc   0x00000000   Code   RO         1678    .ARM.Collect$$$$0000000F  mc_w.l(entry11a.o)
-    0x080000fc   0x080000fc   0x00000004   Code   RO         1667    .ARM.Collect$$$$00002712  mc_w.l(entry2.o)
-    0x08000100   0x08000100   0x00000024   Code   RO         1220    .text               startup_stm32f10x_md.o
-    0x08000124   0x08000124   0x00000064   Code   RO         1646    .text               mf_w.l(fmul.o)
-    0x08000188   0x08000188   0x0000007c   Code   RO         1648    .text               mf_w.l(fdiv.o)
-    0x08000204   0x08000204   0x000000e4   Code   RO         1650    .text               mf_w.l(dmul.o)
-    0x080002e8   0x080002e8   0x000000de   Code   RO         1652    .text               mf_w.l(ddiv.o)
-    0x080003c6   0x080003c6   0x0000000a   Code   RO         1654    .text               mf_w.l(ffltui.o)
-    0x080003d0   0x080003d0   0x00000028   Code   RO         1656    .text               mf_w.l(ffixui.o)
-    0x080003f8   0x080003f8   0x00000026   Code   RO         1658    .text               mf_w.l(f2d.o)
-    0x0800041e   0x0800041e   0x00000002   PAD
-    0x08000420   0x08000420   0x00000030   Code   RO         1660    .text               mf_w.l(cdcmple.o)
-    0x08000450   0x08000450   0x00000030   Code   RO         1662    .text               mf_w.l(cdrcmple.o)
-    0x08000480   0x08000480   0x00000038   Code   RO         1664    .text               mf_w.l(d2f.o)
-    0x080004b8   0x080004b8   0x00000000   Code   RO         1680    .text               mc_w.l(iusefp.o)
-    0x080004b8   0x080004b8   0x0000006e   Code   RO         1681    .text               mf_w.l(fepilogue.o)
-    0x08000526   0x08000526   0x000000ba   Code   RO         1683    .text               mf_w.l(depilogue.o)
-    0x080005e0   0x080005e0   0x00000024   Code   RO         1685    .text               mc_w.l(init.o)
-    0x08000604   0x08000604   0x0000001e   Code   RO         1687    .text               mc_w.l(llshl.o)
-    0x08000622   0x08000622   0x00000020   Code   RO         1689    .text               mc_w.l(llushr.o)
-    0x08000642   0x08000642   0x00000002   PAD
-    0x08000644   0x08000644   0x00000028   Code   RO         1380    i.Anim              Matos.lib(fonctiontimer.o)
-    0x0800066c   0x0800066c   0x00000044   Code   RO         1489    i.Config_SPI        Matos.lib(spi.o)
-    0x080006b0   0x080006b0   0x00000002   Code   RO         1028    i.DMA1_Channel1_Event  dma_stm32f10x.o
-    0x080006b2   0x080006b2   0x00000002   PAD
-    0x080006b4   0x080006b4   0x0000001c   Code   RO         1029    i.DMA1_Channel1_IRQHandler  dma_stm32f10x.o
-    0x080006d0   0x080006d0   0x00000002   Code   RO         1030    i.DMA1_Channel2_Event  dma_stm32f10x.o
-    0x080006d2   0x080006d2   0x00000002   PAD
-    0x080006d4   0x080006d4   0x0000001c   Code   RO         1031    i.DMA1_Channel2_IRQHandler  dma_stm32f10x.o
-    0x080006f0   0x080006f0   0x00000002   Code   RO         1032    i.DMA1_Channel3_Event  dma_stm32f10x.o
-    0x080006f2   0x080006f2   0x00000002   PAD
-    0x080006f4   0x080006f4   0x0000001c   Code   RO         1033    i.DMA1_Channel3_IRQHandler  dma_stm32f10x.o
-    0x08000710   0x08000710   0x00000002   Code   RO         1034    i.DMA1_Channel4_Event  dma_stm32f10x.o
-    0x08000712   0x08000712   0x00000002   PAD
-    0x08000714   0x08000714   0x0000001c   Code   RO         1035    i.DMA1_Channel4_IRQHandler  dma_stm32f10x.o
-    0x08000730   0x08000730   0x00000002   Code   RO         1036    i.DMA1_Channel5_Event  dma_stm32f10x.o
-    0x08000732   0x08000732   0x00000002   PAD
-    0x08000734   0x08000734   0x0000001c   Code   RO         1037    i.DMA1_Channel5_IRQHandler  dma_stm32f10x.o
-    0x08000750   0x08000750   0x00000002   Code   RO         1038    i.DMA1_Channel6_Event  dma_stm32f10x.o
-    0x08000752   0x08000752   0x00000002   PAD
-    0x08000754   0x08000754   0x0000001c   Code   RO         1039    i.DMA1_Channel6_IRQHandler  dma_stm32f10x.o
-    0x08000770   0x08000770   0x00000002   Code   RO         1040    i.DMA1_Channel7_Event  dma_stm32f10x.o
-    0x08000772   0x08000772   0x00000002   PAD
-    0x08000774   0x08000774   0x0000001c   Code   RO         1041    i.DMA1_Channel7_IRQHandler  dma_stm32f10x.o
-    0x08000790   0x08000790   0x0000014c   Code   RO         1542    i.GPIO_Configure    Matos.lib(pilote_io_1.o)
-    0x080008dc   0x080008dc   0x0000010c   Code   RO         1273    i.Init_Cible        Matos.lib(initialisation.o)
-    0x080009e8   0x080009e8   0x00000078   Code   RO         1274    i.Init_Dot          Matos.lib(initialisation.o)
-    0x08000a60   0x08000a60   0x00000090   Code   RO         1275    i.Init_Port         Matos.lib(initialisation.o)
-    0x08000af0   0x08000af0   0x00000174   Code   RO         1277    i.Init_Timer1       Matos.lib(initialisation.o)
-    0x08000c64   0x08000c64   0x0000011c   Code   RO         1278    i.Init_Timer2_PWM   Matos.lib(initialisation.o)
-    0x08000d80   0x08000d80   0x00000070   Code   RO         1279    i.Init_Timer3_Slave  Matos.lib(initialisation.o)
-    0x08000df0   0x08000df0   0x00000074   Code   RO         1280    i.Init_Timer4       Matos.lib(initialisation.o)
-    0x08000e64   0x08000e64   0x00000010   Code   RO         1548    i.Port_IO_Reset     Matos.lib(pilote_io_1.o)
-    0x08000e74   0x08000e74   0x00000010   Code   RO         1549    i.Port_IO_Set       Matos.lib(pilote_io_1.o)
-    0x08000e84   0x08000e84   0x00000018   Code   RO          317    i.SPI_Cmd           stm32f10x_spi.o
-    0x08000e9c   0x08000e9c   0x00000012   Code   RO          325    i.SPI_I2S_GetFlagStatus  stm32f10x_spi.o
-    0x08000eae   0x08000eae   0x00000004   Code   RO         1490    i.SPI_I2S_SendData16  Matos.lib(spi.o)
-    0x08000eb2   0x08000eb2   0x0000003c   Code   RO          330    i.SPI_Init          stm32f10x_spi.o
-    0x08000eee   0x08000eee   0x00000002   PAD
-    0x08000ef0   0x08000ef0   0x00000088   Code   RO         1491    i.SendSPI           Matos.lib(spi.o)
-    0x08000f78   0x08000f78   0x00000008   Code   RO         1227    i.SetSysClock       system_stm32f10x.o
-    0x08000f80   0x08000f80   0x000000e0   Code   RO         1228    i.SetSysClockTo72   system_stm32f10x.o
-    0x08001060   0x08001060   0x00000010   Code   RO         1608    i.SysTick_Handler   Matos.lib(timer_systick_1.o)
-    0x08001070   0x08001070   0x00000060   Code   RO         1230    i.SystemInit        system_stm32f10x.o
-    0x080010d0   0x080010d0   0x00000110   Code   RO         1609    i.Systick_Period    Matos.lib(timer_systick_1.o)
-    0x080011e0   0x080011e0   0x00000024   Code   RO         1610    i.Systick_Prio_IT   Matos.lib(timer_systick_1.o)
-    0x08001204   0x08001204   0x000000b4   Code   RO         1389    i.TIM1_CC_IRQHandler  Matos.lib(fonctiontimer.o)
-    0x080012b8   0x080012b8   0x000000a4   Code   RO         1390    i.TIM1_UP_IRQHandler  Matos.lib(fonctiontimer.o)
-    0x0800135c   0x0800135c   0x00000004   Code   RO         1391    i.TIM2_IRQHandler   Matos.lib(fonctiontimer.o)
-    0x08001360   0x08001360   0x00000050   Code   RO         1392    i.TIM3_IRQHandler   Matos.lib(fonctiontimer.o)
-    0x080013b0   0x080013b0   0x00000074   Code   RO         1393    i.TIM4_IRQHandler   Matos.lib(fonctiontimer.o)
-    0x08001424   0x08001424   0x0000000e   Code   RO         1693    i.__scatterload_copy  mc_w.l(handlers.o)
-    0x08001432   0x08001432   0x00000002   Code   RO         1694    i.__scatterload_null  mc_w.l(handlers.o)
-    0x08001434   0x08001434   0x0000000e   Code   RO         1695    i.__scatterload_zeroinit  mc_w.l(handlers.o)
-    0x08001442   0x08001442   0x00000002   PAD
-    0x08001444   0x08001444   0x0000000a   Code   RO            2    moncode             principale.o
-    0x0800144e   0x0800144e   0x00000002   PAD
-    0x08001450   0x08001450   0x000000c8   Code   RO         1535    moncode             Matos.lib(foncasm.o)
-    0x08001518   0x08001518   0x00000020   Data   RO         1691    Region$$Table       anon$$obj.o
-
-
-    Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x08001538, Size: 0x000004a8, Max: 0x00005000, ABSOLUTE)
-
-    Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
-
-    0x20000000   0x08001538   0x00000013   Data   RW         1281    .data               Matos.lib(initialisation.o)
-    0x20000013   0x0800154b   0x00000001   PAD
-    0x20000014   0x0800154c   0x00000018   Data   RW         1394    .data               Matos.lib(fonctiontimer.o)
-    0x2000002c   0x08001564   0x00000060   Data   RW         1525    .data               Matos.lib(warning.o)
-    0x2000008c   0x080015c4   0x00000004   Data   RW         1611    .data               Matos.lib(timer_systick_1.o)
-    0x20000090        -       0x00000012   Zero   RW         1492    .bss                Matos.lib(spi.o)
-    0x200000a2   0x080015c8   0x00000006   PAD
-    0x200000a8        -       0x00000400   Zero   RW         1217    STACK               startup_stm32f10x_md.o
-
-
-==============================================================================
-
-Image component sizes
-
-
-      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   Object Name
-
-       210         30          0          0          0       7259   dma_stm32f10x.o
-         0          0          0          0          0     213380   misc.o
-        10          0          0          0          0        400   principale.o
-        36          8        236          0       1024        860   startup_stm32f10x_md.o
-       102          0          0          0          0       2941   stm32f10x_spi.o
-       328         28          0          0          0       2205   system_stm32f10x.o
-
-    ----------------------------------------------------------------------
-       704         66        268          0       1024     227045   Object Totals
-         0          0         32          0          0          0   (incl. Generated)
-        18          0          0          0          0          0   (incl. Padding)
-
-    ----------------------------------------------------------------------
-
-      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   Library Member Name
-
-       200         14          0          0          0        460   foncasm.o
-       584        102          0         24          0       3477   fonctiontimer.o
-      1416        160          0         19          0     225316   initialisation.o
-       364         18          0          0          0       2487   pilote_io_1.o
-       208         16          0          0         18       2436   spi.o
-       324         30          0          4          0       2509   timer_systick_1.o
-         0          0          0         96          0        582   warning.o
-         0          0          0          0          0          0   entry.o
-         0          0          0          0          0          0   entry10a.o
-         0          0          0          0          0          0   entry11a.o
-         8          4          0          0          0          0   entry2.o
-         4          0          0          0          0          0   entry5.o
-         0          0          0          0          0          0   entry7b.o
-         0          0          0          0          0          0   entry8b.o
-         8          4          0          0          0          0   entry9a.o
-        30          0          0          0          0          0   handlers.o
-        36          8          0          0          0         68   init.o
-         0          0          0          0          0          0   iusefp.o
-        30          0          0          0          0         68   llshl.o
-        32          0          0          0          0         68   llushr.o
-        48          0          0          0          0         68   cdcmple.o
-        48          0          0          0          0         68   cdrcmple.o
-        56          0          0          0          0         88   d2f.o
-       222          0          0          0          0        100   ddiv.o
-       186          0          0          0          0        176   depilogue.o
-       228          0          0          0          0         96   dmul.o
-        38          0          0          0          0         68   f2d.o
-       124          0          0          0          0         88   fdiv.o
-       110          0          0          0          0        168   fepilogue.o
-        40          0          0          0          0         68   ffixui.o
-        10          0          0          0          0         68   ffltui.o
-       100          0          0          0          0         76   fmul.o
-
-    ----------------------------------------------------------------------
-      4460        356          0        144         24     238603   Library Totals
-         6          0          0          1          6          0   (incl. Padding)
-
-    ----------------------------------------------------------------------
-
-      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   Library Name
-
-      3096        340          0        143         18     237267   Matos.lib
-       148         16          0          0          0        204   mc_w.l
-      1210          0          0          0          0       1132   mf_w.l
-
-    ----------------------------------------------------------------------
-      4460        356          0        144         24     238603   Library Totals
-
-    ----------------------------------------------------------------------
-
-==============================================================================
-
-
-      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   
-
-      5164        422        268        144       1048     462992   Grand Totals
-      5164        422        268        144       1048     462992   ELF Image Totals
-      5164        422        268        144          0          0   ROM Totals
-
-==============================================================================
-
-    Total RO  Size (Code + RO Data)                 5432 (   5.30kB)
-    Total RW  Size (RW Data + ZI Data)              1192 (   1.16kB)
-    Total ROM Size (Code + RO Data + RW Data)       5576 (   5.45kB)
-
-==============================================================================
-
diff --git a/Listings/fonctionetape.lst b/Listings/fonctionetape.lst
deleted file mode 100644
index 941afd1..0000000
--- a/Listings/fonctionetape.lst
+++ /dev/null
@@ -1,394 +0,0 @@
-
-
-
-ARM Macro Assembler    Page 1 
-
-
-    1 00000000         ;*******************************************************
-                       ********************
-    2 00000000                 THUMB
-    3 00000000                 REQUIRE8
-    4 00000000                 PRESERVE8
-    5 00000000         
-    6 00000000         ;*******************************************************
-                       *******************
-    7 00000000         ;  Fichier Vierge.asm
-    8 00000000         ; Auteur : V.MAHOUT
-    9 00000000         ; Date :  12/11/2013
-   10 00000000         ;*******************************************************
-                       *******************
-   11 00000000         
-   12 00000000         ;***************IMPORT/EXPORT***************************
-                       *******************
-   13 00000000         
-   14 00000000         
-   15 00000000         
-   16 00000000         ;*******************************************************
-                       *******************
-   17 00000000         
-   18 00000000         
-   19 00000000         
-   20 00000000         ;***************CONSTANTES******************************
-                       *******************
-   21 00000000         
-   22 00000000                 include          REG_UTILES.inc
-    1 00000000         
-    2 00000000         ;**************************************
-    3 00000000         ;     Les adresess utiles  
-    4 00000000         ;***************************************
-    5 00000000         
-    6 00000000         
-    7 00000000         ;**************************************
-    8 00000000         ;     Affectation des bits GPIO  
-    9 00000000         ;***************************************
-   10 00000000         ; GSLCK..... PA0 
-   11 00000000         ; DSPRG..... PA1 
-   12 00000000         ; BLANK..... PA2 
-   13 00000000         ; XLAT...... PA3
-   14 00000000         ; VPRG...... PA4
-   15 00000000         ; SCLK...... PA5
-   16 00000000         ; SIN1...... PA7
-   17 00000000         ;Capteur.....PA8
-   18 00000000         
-   19 00000000         ;LED.........PB10
-   20 00000000         ;****************************************/
-   21 00000000         
-   22 00000000         
-   23 00000000         
-   24 00000000 40010800 
-                       GPIOBASEA
-                               EQU              0X40010800
-   25 00000000 40010C00 
-                       GPIOBASEB
-                               EQU              0X40010C00
-   26 00000000         
-   27 00000000 00000008 
-
-
-
-ARM Macro Assembler    Page 2 
-
-
-                       OffsetInput
-                               EQU              0x08
-   28 00000000 0000000C 
-                       OffsetOutput
-                               EQU              0x0C
-   29 00000000 00000010 
-                       OffsetSet
-                               EQU              0x10
-   30 00000000 00000014 
-                       OffsetReset
-                               EQU              0x14
-   31 00000000         
-   32 00000000         
-   33 00000000 00000080 
-                       MaskSerial_In1
-                               equ              0x80
-   34 00000000 00000080 
-                       MaskSerial_Dots
-                               equ              0x80
-   35 00000000 00000010 
-                       MaskVprg
-                               equ              0x10
-   36 00000000 00000008 
-                       MaskXlat
-                               equ              0x08
-   37 00000000 00000004 
-                       MaskBlank
-                               equ              0x04
-   38 00000000 00000020 
-                       MaskSclk
-                               equ              0x20
-   39 00000000 00000002 
-                       MaskDsprg
-                               equ              0x02
-   40 00000000 00000001 
-                       MaskGsclk
-                               equ              0x01
-   41 00000000         
-   42 00000000         
-   43 00000000 E000ED08 
-                       SCB_VTOR
-                               EQU              0xE000ED08
-   44 00000000 40012C10 
-                       TIM1_SR EQU              0x40012c10
-   45 00000000 40012C24 
-                       TIM1_CNT
-                               EQU              0x40012c24
-   46 00000000 4000082C 
-                       TIM4_ARR
-                               EQU              0x4000082C
-   47 00000000 40000810 
-                       TIM4_SR EQU              0x40000810
-   48 00000000         
-   49 00000000         
-   50 00000000         
-   51 00000000         
-   52 00000000         
-   53 00000000                 END
-   23 00000000         
-
-
-
-ARM Macro Assembler    Page 3 
-
-
-   24 00000000         ;*******************************************************
-                       *******************
-   25 00000000         
-   26 00000000         
-   27 00000000         ;***************VARIABLES*******************************
-                       *******************
-   28 00000000                 AREA             MesDonnees, data, readwrite
-   29 00000000         ;*******************************************************
-                       *******************
-   30 00000000         
-   31 00000000         
-   32 00000000         
-   33 00000000         ;*******************************************************
-                       *******************
-   34 00000000         
-   35 00000000         
-   36 00000000         
-   37 00000000         ;***************CODE************************************
-                       *******************
-   38 00000000                 AREA             moncode, code, readonly
-   39 00000000         ;*******************************************************
-                       *******************
-   40 00000000         
-   41 00000000         
-   42 00000000         
-   43 00000000         
-   44 00000000         
-   45 00000000         ;#######################################################
-                       #################
-   46 00000000         ; Procédure ????
-   47 00000000         ;#######################################################
-                       #################
-   48 00000000         ;
-   49 00000000         ; Paramètre entrant  : ???
-   50 00000000         ; Paramètre sortant  : ???
-   51 00000000         ; Variables globales : ???
-   52 00000000         ; Registres modifiés : ???
-   53 00000000         ;-------------------------------------------------------
-                       -----------------
-   54 00000000         
-   55 00000000         
-   56 00000000         
-   57 00000000         
-   58 00000000         
-   59 00000000         
-   60 00000000         
-   61 00000000         ;*******************************************************
-                       *******************
-   62 00000000                 END
-Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw
-ork --depend=.\objects\fonctionetape.d -o.\objects\fonctionetape.o -I.\RTE\Devi
-ce\STM32F107VC -I.\RTE\_R_el -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Includ
-e -IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include --predefine="__
-EVAL SETA 1" --predefine="__MICROLIB SETA 1" --predefine="__UVISION_VERSION SET
-A 524" --predefine="_RTE_ SETA 1" --predefine="STM32F10X_CL SETA 1" --predefine
-="STM32F10X_CL SETA 1" --list=.\listings\fonctionetape.lst FonctionEtape.asm
-
-
-
-ARM Macro Assembler    Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-MesDonnees 00000000
-
-Symbol: MesDonnees
-   Definitions
-      At line 28 in file FonctionEtape.asm
-   Uses
-      None
-Comment: MesDonnees unused
-1 symbol
-
-
-
-ARM Macro Assembler    Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-moncode 00000000
-
-Symbol: moncode
-   Definitions
-      At line 38 in file FonctionEtape.asm
-   Uses
-      None
-Comment: moncode unused
-1 symbol
-
-
-
-ARM Macro Assembler    Page 1 Alphabetic symbol ordering
-Absolute symbols
-
-GPIOBASEA 40010800
-
-Symbol: GPIOBASEA
-   Definitions
-      At line 24 in file REG_UTILES.inc
-   Uses
-      None
-Comment: GPIOBASEA unused
-GPIOBASEB 40010C00
-
-Symbol: GPIOBASEB
-   Definitions
-      At line 25 in file REG_UTILES.inc
-   Uses
-      None
-Comment: GPIOBASEB unused
-MaskBlank 00000004
-
-Symbol: MaskBlank
-   Definitions
-      At line 37 in file REG_UTILES.inc
-   Uses
-      None
-Comment: MaskBlank unused
-MaskDsprg 00000002
-
-Symbol: MaskDsprg
-   Definitions
-      At line 39 in file REG_UTILES.inc
-   Uses
-      None
-Comment: MaskDsprg unused
-MaskGsclk 00000001
-
-Symbol: MaskGsclk
-   Definitions
-      At line 40 in file REG_UTILES.inc
-   Uses
-      None
-Comment: MaskGsclk unused
-MaskSclk 00000020
-
-Symbol: MaskSclk
-   Definitions
-      At line 38 in file REG_UTILES.inc
-   Uses
-      None
-Comment: MaskSclk unused
-MaskSerial_Dots 00000080
-
-Symbol: MaskSerial_Dots
-   Definitions
-      At line 34 in file REG_UTILES.inc
-   Uses
-      None
-Comment: MaskSerial_Dots unused
-MaskSerial_In1 00000080
-
-Symbol: MaskSerial_In1
-
-
-
-ARM Macro Assembler    Page 2 Alphabetic symbol ordering
-Absolute symbols
-
-   Definitions
-      At line 33 in file REG_UTILES.inc
-   Uses
-      None
-Comment: MaskSerial_In1 unused
-MaskVprg 00000010
-
-Symbol: MaskVprg
-   Definitions
-      At line 35 in file REG_UTILES.inc
-   Uses
-      None
-Comment: MaskVprg unused
-MaskXlat 00000008
-
-Symbol: MaskXlat
-   Definitions
-      At line 36 in file REG_UTILES.inc
-   Uses
-      None
-Comment: MaskXlat unused
-OffsetInput 00000008
-
-Symbol: OffsetInput
-   Definitions
-      At line 27 in file REG_UTILES.inc
-   Uses
-      None
-Comment: OffsetInput unused
-OffsetOutput 0000000C
-
-Symbol: OffsetOutput
-   Definitions
-      At line 28 in file REG_UTILES.inc
-   Uses
-      None
-Comment: OffsetOutput unused
-OffsetReset 00000014
-
-Symbol: OffsetReset
-   Definitions
-      At line 30 in file REG_UTILES.inc
-   Uses
-      None
-Comment: OffsetReset unused
-OffsetSet 00000010
-
-Symbol: OffsetSet
-   Definitions
-      At line 29 in file REG_UTILES.inc
-   Uses
-      None
-Comment: OffsetSet unused
-SCB_VTOR E000ED08
-
-Symbol: SCB_VTOR
-   Definitions
-      At line 43 in file REG_UTILES.inc
-   Uses
-
-
-
-ARM Macro Assembler    Page 3 Alphabetic symbol ordering
-Absolute symbols
-
-      None
-Comment: SCB_VTOR unused
-TIM1_CNT 40012C24
-
-Symbol: TIM1_CNT
-   Definitions
-      At line 45 in file REG_UTILES.inc
-   Uses
-      None
-Comment: TIM1_CNT unused
-TIM1_SR 40012C10
-
-Symbol: TIM1_SR
-   Definitions
-      At line 44 in file REG_UTILES.inc
-   Uses
-      None
-Comment: TIM1_SR unused
-TIM4_ARR 4000082C
-
-Symbol: TIM4_ARR
-   Definitions
-      At line 46 in file REG_UTILES.inc
-   Uses
-      None
-Comment: TIM4_ARR unused
-TIM4_SR 40000810
-
-Symbol: TIM4_SR
-   Definitions
-      At line 47 in file REG_UTILES.inc
-   Uses
-      None
-Comment: TIM4_SR unused
-19 symbols
-356 symbols in table
diff --git a/Listings/principale.lst b/Listings/principale.lst
deleted file mode 100644
index 74612e7..0000000
--- a/Listings/principale.lst
+++ /dev/null
@@ -1,419 +0,0 @@
-
-
-
-ARM Macro Assembler    Page 1 
-
-
-    1 00000000         
-    2 00000000         
-    3 00000000         ;*******************************************************
-                       *****************
-    4 00000000                 THUMB
-    5 00000000                 REQUIRE8
-    6 00000000                 PRESERVE8
-    7 00000000         ;*******************************************************
-                       *****************
-    8 00000000         
-    9 00000000                 include          REG_UTILES.inc
-    1 00000000         
-    2 00000000         ;**************************************
-    3 00000000         ;     Les adresess utiles  
-    4 00000000         ;***************************************
-    5 00000000         
-    6 00000000         
-    7 00000000         ;**************************************
-    8 00000000         ;     Affectation des bits GPIO  
-    9 00000000         ;***************************************
-   10 00000000         ; GSLCK..... PA0 
-   11 00000000         ; DSPRG..... PA1 
-   12 00000000         ; BLANK..... PA2 
-   13 00000000         ; XLAT...... PA3
-   14 00000000         ; VPRG...... PA4
-   15 00000000         ; SCLK...... PA5
-   16 00000000         ; SIN1...... PA7
-   17 00000000         ;Capteur.....PA8
-   18 00000000         
-   19 00000000         ;LED.........PB10
-   20 00000000         ;****************************************/
-   21 00000000         
-   22 00000000         
-   23 00000000         
-   24 00000000 40010800 
-                       GPIOBASEA
-                               EQU              0X40010800
-   25 00000000 40010C00 
-                       GPIOBASEB
-                               EQU              0X40010C00
-   26 00000000         
-   27 00000000 00000008 
-                       OffsetInput
-                               EQU              0x08
-   28 00000000 0000000C 
-                       OffsetOutput
-                               EQU              0x0C
-   29 00000000 00000010 
-                       OffsetSet
-                               EQU              0x10
-   30 00000000 00000014 
-                       OffsetReset
-                               EQU              0x14
-   31 00000000         
-   32 00000000         
-   33 00000000 00000080 
-                       MaskSerial_In1
-                               equ              0x80
-   34 00000000 00000080 
-
-
-
-ARM Macro Assembler    Page 2 
-
-
-                       MaskSerial_Dots
-                               equ              0x80
-   35 00000000 00000010 
-                       MaskVprg
-                               equ              0x10
-   36 00000000 00000008 
-                       MaskXlat
-                               equ              0x08
-   37 00000000 00000004 
-                       MaskBlank
-                               equ              0x04
-   38 00000000 00000020 
-                       MaskSclk
-                               equ              0x20
-   39 00000000 00000002 
-                       MaskDsprg
-                               equ              0x02
-   40 00000000 00000001 
-                       MaskGsclk
-                               equ              0x01
-   41 00000000         
-   42 00000000         
-   43 00000000 E000ED08 
-                       SCB_VTOR
-                               EQU              0xE000ED08
-   44 00000000 40012C10 
-                       TIM1_SR EQU              0x40012c10
-   45 00000000 40012C24 
-                       TIM1_CNT
-                               EQU              0x40012c24
-   46 00000000 4000082C 
-                       TIM4_ARR
-                               EQU              0x4000082C
-   47 00000000 40000810 
-                       TIM4_SR EQU              0x40000810
-   48 00000000         
-   49 00000000         
-   50 00000000         
-   51 00000000         
-   52 00000000         
-   53 00000000                 END
-   10 00000000         
-   11 00000000         
-   12 00000000         ;*******************************************************
-                       *****************
-   13 00000000         ;      IMPORT/EXPORT Système
-   14 00000000         ;*******************************************************
-                       *****************
-   15 00000000         
-   16 00000000                 IMPORT           ||Lib$$Request$$armlib|| [CODE,
-WEAK]
-   17 00000000         
-   18 00000000         
-   19 00000000         
-   20 00000000         
-   21 00000000         ; IMPORT/EXPORT de procédure           
-   22 00000000         
-   23 00000000                 IMPORT           Init_Cible
-   24 00000000         
-
-
-
-ARM Macro Assembler    Page 3 
-
-
-   25 00000000         
-   26 00000000                 EXPORT           main
-   27 00000000         
-   28 00000000         ;*******************************************************
-                       ************************
-   29 00000000         
-   30 00000000         
-   31 00000000         ;*******************************************************
-                       ************************
-   32 00000000                 AREA             mesdonnees, data, readwrite
-   33 00000000         
-   34 00000000         
-   35 00000000         
-   36 00000000         
-   37 00000000         ;*******************************************************
-                       ************************
-   38 00000000         
-   39 00000000                 AREA             moncode, code, readonly
-   40 00000000         
-   41 00000000         
-   42 00000000         
-   43 00000000         ;*******************************************************
-                       ************************
-   44 00000000         ; Procédure principale et point d'entrée du projet
-   45 00000000         ;*******************************************************
-                       ************************
-   46 00000000         main    PROC
-   47 00000000         ;*******************************************************
-                       ************************
-   48 00000000         
-   49 00000000         
-   50 00000000 F04F 0000       MOV              R0,#0
-   51 00000004 F7FF FFFE       BL               Init_Cible  ;
-   52 00000008         
-   53 00000008 E7FE            B                .           ; boucle inifinie t
-                                                            erminale...
-   54 0000000A         
-   55 0000000A         
-   56 0000000A         
-   57 0000000A         
-   58 0000000A                 ENDP
-   59 0000000A         
-   60 0000000A                 END
-Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw
-ork --depend=.\objects\principale.d -o.\objects\principale.o -I.\RTE\Device\STM
-32F107VC -I.\RTE\_R_el -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include -IC:
-\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include --predefine="__EVAL S
-ETA 1" --predefine="__MICROLIB SETA 1" --predefine="__UVISION_VERSION SETA 524"
- --predefine="_RTE_ SETA 1" --predefine="STM32F10X_CL SETA 1" --predefine="STM3
-2F10X_CL SETA 1" --list=.\listings\principale.lst Principale.asm
-
-
-
-ARM Macro Assembler    Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-mesdonnees 00000000
-
-Symbol: mesdonnees
-   Definitions
-      At line 32 in file Principale.asm
-   Uses
-      None
-Comment: mesdonnees unused
-1 symbol
-
-
-
-ARM Macro Assembler    Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-main 00000000
-
-Symbol: main
-   Definitions
-      At line 46 in file Principale.asm
-   Uses
-      At line 26 in file Principale.asm
-Comment: main used once
-moncode 00000000
-
-Symbol: moncode
-   Definitions
-      At line 39 in file Principale.asm
-   Uses
-      None
-Comment: moncode unused
-2 symbols
-
-
-
-ARM Macro Assembler    Page 1 Alphabetic symbol ordering
-Absolute symbols
-
-GPIOBASEA 40010800
-
-Symbol: GPIOBASEA
-   Definitions
-      At line 24 in file REG_UTILES.inc
-   Uses
-      None
-Comment: GPIOBASEA unused
-GPIOBASEB 40010C00
-
-Symbol: GPIOBASEB
-   Definitions
-      At line 25 in file REG_UTILES.inc
-   Uses
-      None
-Comment: GPIOBASEB unused
-MaskBlank 00000004
-
-Symbol: MaskBlank
-   Definitions
-      At line 37 in file REG_UTILES.inc
-   Uses
-      None
-Comment: MaskBlank unused
-MaskDsprg 00000002
-
-Symbol: MaskDsprg
-   Definitions
-      At line 39 in file REG_UTILES.inc
-   Uses
-      None
-Comment: MaskDsprg unused
-MaskGsclk 00000001
-
-Symbol: MaskGsclk
-   Definitions
-      At line 40 in file REG_UTILES.inc
-   Uses
-      None
-Comment: MaskGsclk unused
-MaskSclk 00000020
-
-Symbol: MaskSclk
-   Definitions
-      At line 38 in file REG_UTILES.inc
-   Uses
-      None
-Comment: MaskSclk unused
-MaskSerial_Dots 00000080
-
-Symbol: MaskSerial_Dots
-   Definitions
-      At line 34 in file REG_UTILES.inc
-   Uses
-      None
-Comment: MaskSerial_Dots unused
-MaskSerial_In1 00000080
-
-Symbol: MaskSerial_In1
-
-
-
-ARM Macro Assembler    Page 2 Alphabetic symbol ordering
-Absolute symbols
-
-   Definitions
-      At line 33 in file REG_UTILES.inc
-   Uses
-      None
-Comment: MaskSerial_In1 unused
-MaskVprg 00000010
-
-Symbol: MaskVprg
-   Definitions
-      At line 35 in file REG_UTILES.inc
-   Uses
-      None
-Comment: MaskVprg unused
-MaskXlat 00000008
-
-Symbol: MaskXlat
-   Definitions
-      At line 36 in file REG_UTILES.inc
-   Uses
-      None
-Comment: MaskXlat unused
-OffsetInput 00000008
-
-Symbol: OffsetInput
-   Definitions
-      At line 27 in file REG_UTILES.inc
-   Uses
-      None
-Comment: OffsetInput unused
-OffsetOutput 0000000C
-
-Symbol: OffsetOutput
-   Definitions
-      At line 28 in file REG_UTILES.inc
-   Uses
-      None
-Comment: OffsetOutput unused
-OffsetReset 00000014
-
-Symbol: OffsetReset
-   Definitions
-      At line 30 in file REG_UTILES.inc
-   Uses
-      None
-Comment: OffsetReset unused
-OffsetSet 00000010
-
-Symbol: OffsetSet
-   Definitions
-      At line 29 in file REG_UTILES.inc
-   Uses
-      None
-Comment: OffsetSet unused
-SCB_VTOR E000ED08
-
-Symbol: SCB_VTOR
-   Definitions
-      At line 43 in file REG_UTILES.inc
-   Uses
-
-
-
-ARM Macro Assembler    Page 3 Alphabetic symbol ordering
-Absolute symbols
-
-      None
-Comment: SCB_VTOR unused
-TIM1_CNT 40012C24
-
-Symbol: TIM1_CNT
-   Definitions
-      At line 45 in file REG_UTILES.inc
-   Uses
-      None
-Comment: TIM1_CNT unused
-TIM1_SR 40012C10
-
-Symbol: TIM1_SR
-   Definitions
-      At line 44 in file REG_UTILES.inc
-   Uses
-      None
-Comment: TIM1_SR unused
-TIM4_ARR 4000082C
-
-Symbol: TIM4_ARR
-   Definitions
-      At line 46 in file REG_UTILES.inc
-   Uses
-      None
-Comment: TIM4_ARR unused
-TIM4_SR 40000810
-
-Symbol: TIM4_SR
-   Definitions
-      At line 47 in file REG_UTILES.inc
-   Uses
-      None
-Comment: TIM4_SR unused
-19 symbols
-
-
-
-ARM Macro Assembler    Page 1 Alphabetic symbol ordering
-External symbols
-
-Init_Cible 00000000
-
-Symbol: Init_Cible
-   Definitions
-      At line 23 in file Principale.asm
-   Uses
-      At line 51 in file Principale.asm
-Comment: Init_Cible used once
-|Lib$$Request$$armlib| 00000000
-
-Symbol: |Lib$$Request$$armlib|
-   Definitions
-      At line 16 in file Principale.asm
-   Uses
-      None
-Comment: |Lib$$Request$$armlib| unused
-2 symbols
-359 symbols in table
diff --git a/Listings/startup_stm32f10x_cl.lst b/Listings/startup_stm32f10x_cl.lst
deleted file mode 100644
index 5fb5f8d..0000000
--- a/Listings/startup_stm32f10x_cl.lst
+++ /dev/null
@@ -1,1450 +0,0 @@
-
-
-
-ARM Macro Assembler    Page 1 
-
-
-    1 00000000         ;******************** (C) COPYRIGHT 2011 STMicroelectron
-                       ics ********************
-    2 00000000         ;* File Name          : startup_stm32f10x_cl.s
-    3 00000000         ;* Author             : MCD Application Team
-    4 00000000         ;* Version            : V3.5.0
-    5 00000000         ;* Date               : 11-March-2011
-    6 00000000         ;* Description        : STM32F10x Connectivity line devi
-                       ces vector table for MDK-ARM 
-    7 00000000         ;*                      toolchain. 
-    8 00000000         ;*                      This module performs:
-    9 00000000         ;*                      - Set the initial SP
-   10 00000000         ;*                      - Set the initial PC == Reset_Ha
-                       ndler
-   11 00000000         ;*                      - Set the vector table entries w
-                       ith the exceptions ISR address
-   12 00000000         ;*                      - Configure the clock system
-   13 00000000         ;*                      - Branches to __main in the C li
-                       brary (which eventually
-   14 00000000         ;*                        calls main()).
-   15 00000000         ;*                      After Reset the CortexM3 process
-                       or is in Thread mode,
-   16 00000000         ;*                      priority is Privileged, and the 
-                       Stack is set to Main.
-   17 00000000         ;* <<< Use Configuration Wizard in Context Menu >>>   
-   18 00000000         ;*******************************************************
-                       ************************
-   19 00000000         ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS A
-                       T PROVIDING CUSTOMERS
-   20 00000000         ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN OR
-                       DER FOR THEM TO SAVE TIME.
-   21 00000000         ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIAB
-                       LE FOR ANY DIRECT,
-   22 00000000         ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY 
-                       CLAIMS ARISING FROM THE
-   23 00000000         ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOM
-                       ERS OF THE CODING
-   24 00000000         ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR 
-                       PRODUCTS.
-   25 00000000         ;*******************************************************
-                       ************************
-   26 00000000         
-   27 00000000         ; Amount of memory (in bytes) allocated for Stack
-   28 00000000         ; Tailor this value to your application needs
-   29 00000000         ; <h> Stack Configuration
-   30 00000000         ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-   31 00000000         ; </h>
-   32 00000000         
-   33 00000000 00000400 
-                       Stack_Size
-                               EQU              0x00000400
-   34 00000000         
-   35 00000000                 AREA             STACK, NOINIT, READWRITE, ALIGN
-=3
-   36 00000000         Stack_Mem
-                               SPACE            Stack_Size
-   37 00000400         __initial_sp
-   38 00000400         
-   39 00000400         
-   40 00000400         ; <h> Heap Configuration
-
-
-
-ARM Macro Assembler    Page 2 
-
-
-   41 00000400         ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-   42 00000400         ; </h>
-   43 00000400         
-   44 00000400 00000200 
-                       Heap_Size
-                               EQU              0x00000200
-   45 00000400         
-   46 00000400                 AREA             HEAP, NOINIT, READWRITE, ALIGN=
-3
-   47 00000000         __heap_base
-   48 00000000         Heap_Mem
-                               SPACE            Heap_Size
-   49 00000200         __heap_limit
-   50 00000200         
-   51 00000200                 PRESERVE8
-   52 00000200                 THUMB
-   53 00000200         
-   54 00000200         
-   55 00000200         ; Vector Table Mapped to Address 0 at Reset
-   56 00000200                 AREA             RESET, DATA, READONLY
-   57 00000000                 EXPORT           __Vectors
-   58 00000000                 EXPORT           __Vectors_End
-   59 00000000                 EXPORT           __Vectors_Size
-   60 00000000         
-   61 00000000 00000000 
-                       __Vectors
-                               DCD              __initial_sp ; Top of Stack
-   62 00000004 00000000        DCD              Reset_Handler ; Reset Handler
-   63 00000008 00000000        DCD              NMI_Handler ; NMI Handler
-   64 0000000C 00000000        DCD              HardFault_Handler ; Hard Fault 
-                                                            Handler
-   65 00000010 00000000        DCD              MemManage_Handler 
-                                                            ; MPU Fault Handler
-                                                            
-   66 00000014 00000000        DCD              BusFault_Handler 
-                                                            ; Bus Fault Handler
-                                                            
-   67 00000018 00000000        DCD              UsageFault_Handler ; Usage Faul
-                                                            t Handler
-   68 0000001C 00000000        DCD              0           ; Reserved
-   69 00000020 00000000        DCD              0           ; Reserved
-   70 00000024 00000000        DCD              0           ; Reserved
-   71 00000028 00000000        DCD              0           ; Reserved
-   72 0000002C 00000000        DCD              SVC_Handler ; SVCall Handler
-   73 00000030 00000000        DCD              DebugMon_Handler ; Debug Monito
-                                                            r Handler
-   74 00000034 00000000        DCD              0           ; Reserved
-   75 00000038 00000000        DCD              PendSV_Handler ; PendSV Handler
-                                                            
-   76 0000003C 00000000        DCD              SysTick_Handler 
-                                                            ; SysTick Handler
-   77 00000040         
-   78 00000040         ; External Interrupts
-   79 00000040 00000000        DCD              WWDG_IRQHandler 
-                                                            ; Window Watchdog
-   80 00000044 00000000        DCD              PVD_IRQHandler ; PVD through EX
-                                                            TI Line detect
-   81 00000048 00000000        DCD              TAMPER_IRQHandler ; Tamper
-   82 0000004C 00000000        DCD              RTC_IRQHandler ; RTC
-
-
-
-ARM Macro Assembler    Page 3 
-
-
-   83 00000050 00000000        DCD              FLASH_IRQHandler ; Flash
-   84 00000054 00000000        DCD              RCC_IRQHandler ; RCC
-   85 00000058 00000000        DCD              EXTI0_IRQHandler ; EXTI Line 0
-   86 0000005C 00000000        DCD              EXTI1_IRQHandler ; EXTI Line 1
-   87 00000060 00000000        DCD              EXTI2_IRQHandler ; EXTI Line 2
-   88 00000064 00000000        DCD              EXTI3_IRQHandler ; EXTI Line 3
-   89 00000068 00000000        DCD              EXTI4_IRQHandler ; EXTI Line 4
-   90 0000006C 00000000        DCD              DMA1_Channel1_IRQHandler 
-                                                            ; DMA1 Channel 1
-   91 00000070 00000000        DCD              DMA1_Channel2_IRQHandler 
-                                                            ; DMA1 Channel 2
-   92 00000074 00000000        DCD              DMA1_Channel3_IRQHandler 
-                                                            ; DMA1 Channel 3
-   93 00000078 00000000        DCD              DMA1_Channel4_IRQHandler 
-                                                            ; DMA1 Channel 4
-   94 0000007C 00000000        DCD              DMA1_Channel5_IRQHandler 
-                                                            ; DMA1 Channel 5
-   95 00000080 00000000        DCD              DMA1_Channel6_IRQHandler 
-                                                            ; DMA1 Channel 6
-   96 00000084 00000000        DCD              DMA1_Channel7_IRQHandler 
-                                                            ; DMA1 Channel 7
-   97 00000088 00000000        DCD              ADC1_2_IRQHandler 
-                                                            ; ADC1 and ADC2
-   98 0000008C 00000000        DCD              CAN1_TX_IRQHandler ; CAN1 TX
-   99 00000090 00000000        DCD              CAN1_RX0_IRQHandler ; CAN1 RX0
-  100 00000094 00000000        DCD              CAN1_RX1_IRQHandler ; CAN1 RX1
-  101 00000098 00000000        DCD              CAN1_SCE_IRQHandler ; CAN1 SCE
-  102 0000009C 00000000        DCD              EXTI9_5_IRQHandler 
-                                                            ; EXTI Line 9..5
-  103 000000A0 00000000        DCD              TIM1_BRK_IRQHandler 
-                                                            ; TIM1 Break
-  104 000000A4 00000000        DCD              TIM1_UP_IRQHandler 
-                                                            ; TIM1 Update
-  105 000000A8 00000000        DCD              TIM1_TRG_COM_IRQHandler ; TIM1 
-                                                            Trigger and Commuta
-                                                            tion
-  106 000000AC 00000000        DCD              TIM1_CC_IRQHandler ; TIM1 Captu
-                                                            re Compare
-  107 000000B0 00000000        DCD              TIM2_IRQHandler ; TIM2
-  108 000000B4 00000000        DCD              TIM3_IRQHandler ; TIM3
-  109 000000B8 00000000        DCD              TIM4_IRQHandler ; TIM4
-  110 000000BC 00000000        DCD              I2C1_EV_IRQHandler ; I2C1 Event
-                                                            
-  111 000000C0 00000000        DCD              I2C1_ER_IRQHandler ; I2C1 Error
-                                                            
-  112 000000C4 00000000        DCD              I2C2_EV_IRQHandler ; I2C2 Event
-                                                            
-  113 000000C8 00000000        DCD              I2C2_ER_IRQHandler ; I2C1 Error
-                                                            
-  114 000000CC 00000000        DCD              SPI1_IRQHandler ; SPI1
-  115 000000D0 00000000        DCD              SPI2_IRQHandler ; SPI2
-  116 000000D4 00000000        DCD              USART1_IRQHandler ; USART1
-  117 000000D8 00000000        DCD              USART2_IRQHandler ; USART2
-  118 000000DC 00000000        DCD              USART3_IRQHandler ; USART3
-  119 000000E0 00000000        DCD              EXTI15_10_IRQHandler 
-                                                            ; EXTI Line 15..10
-  120 000000E4 00000000        DCD              RTCAlarm_IRQHandler ; RTC alarm
-                                                             through EXTI line
-  121 000000E8 00000000        DCD              OTG_FS_WKUP_IRQHandler ; USB OT
-
-
-
-ARM Macro Assembler    Page 4 
-
-
-                                                            G FS Wakeup through
-                                                             EXTI line
-  122 000000EC 00000000        DCD              0           ; Reserved
-  123 000000F0 00000000        DCD              0           ; Reserved
-  124 000000F4 00000000        DCD              0           ; Reserved
-  125 000000F8 00000000        DCD              0           ; Reserved
-  126 000000FC 00000000        DCD              0           ; Reserved
-  127 00000100 00000000        DCD              0           ; Reserved
-  128 00000104 00000000        DCD              0           ; Reserved
-  129 00000108 00000000        DCD              TIM5_IRQHandler ; TIM5
-  130 0000010C 00000000        DCD              SPI3_IRQHandler ; SPI3
-  131 00000110 00000000        DCD              UART4_IRQHandler ; UART4
-  132 00000114 00000000        DCD              UART5_IRQHandler ; UART5
-  133 00000118 00000000        DCD              TIM6_IRQHandler ; TIM6
-  134 0000011C 00000000        DCD              TIM7_IRQHandler ; TIM7
-  135 00000120 00000000        DCD              DMA2_Channel1_IRQHandler 
-                                                            ; DMA2 Channel1
-  136 00000124 00000000        DCD              DMA2_Channel2_IRQHandler 
-                                                            ; DMA2 Channel2
-  137 00000128 00000000        DCD              DMA2_Channel3_IRQHandler 
-                                                            ; DMA2 Channel3
-  138 0000012C 00000000        DCD              DMA2_Channel4_IRQHandler 
-                                                            ; DMA2 Channel4
-  139 00000130 00000000        DCD              DMA2_Channel5_IRQHandler 
-                                                            ; DMA2 Channel5
-  140 00000134 00000000        DCD              ETH_IRQHandler ; Ethernet
-  141 00000138 00000000        DCD              ETH_WKUP_IRQHandler ; Ethernet 
-                                                            Wakeup through EXTI
-                                                             line
-  142 0000013C 00000000        DCD              CAN2_TX_IRQHandler ; CAN2 TX
-  143 00000140 00000000        DCD              CAN2_RX0_IRQHandler ; CAN2 RX0
-  144 00000144 00000000        DCD              CAN2_RX1_IRQHandler ; CAN2 RX1
-  145 00000148 00000000        DCD              CAN2_SCE_IRQHandler ; CAN2 SCE
-  146 0000014C 00000000        DCD              OTG_FS_IRQHandler ; USB OTG FS
-  147 00000150         __Vectors_End
-  148 00000150         
-  149 00000150 00000150 
-                       __Vectors_Size
-                               EQU              __Vectors_End - __Vectors
-  150 00000150         
-  151 00000150                 AREA             |.text|, CODE, READONLY
-  152 00000000         
-  153 00000000         ; Reset handler
-  154 00000000         Reset_Handler
-                               PROC
-  155 00000000                 EXPORT           Reset_Handler             [WEAK
-]
-  156 00000000                 IMPORT           SystemInit
-  157 00000000                 IMPORT           __main
-  158 00000000 4806            LDR              R0, =SystemInit
-  159 00000002 4780            BLX              R0
-  160 00000004 4806            LDR              R0, =__main
-  161 00000006 4700            BX               R0
-  162 00000008                 ENDP
-  163 00000008         
-  164 00000008         ; Dummy Exception Handlers (infinite loops which can be 
-                       modified)
-  165 00000008         
-  166 00000008         NMI_Handler
-
-
-
-ARM Macro Assembler    Page 5 
-
-
-                               PROC
-  167 00000008                 EXPORT           NMI_Handler                [WEA
-K]
-  168 00000008 E7FE            B                .
-  169 0000000A                 ENDP
-  171 0000000A         HardFault_Handler
-                               PROC
-  172 0000000A                 EXPORT           HardFault_Handler          [WEA
-K]
-  173 0000000A E7FE            B                .
-  174 0000000C                 ENDP
-  176 0000000C         MemManage_Handler
-                               PROC
-  177 0000000C                 EXPORT           MemManage_Handler          [WEA
-K]
-  178 0000000C E7FE            B                .
-  179 0000000E                 ENDP
-  181 0000000E         BusFault_Handler
-                               PROC
-  182 0000000E                 EXPORT           BusFault_Handler           [WEA
-K]
-  183 0000000E E7FE            B                .
-  184 00000010                 ENDP
-  186 00000010         UsageFault_Handler
-                               PROC
-  187 00000010                 EXPORT           UsageFault_Handler         [WEA
-K]
-  188 00000010 E7FE            B                .
-  189 00000012                 ENDP
-  190 00000012         SVC_Handler
-                               PROC
-  191 00000012                 EXPORT           SVC_Handler                [WEA
-K]
-  192 00000012 E7FE            B                .
-  193 00000014                 ENDP
-  195 00000014         DebugMon_Handler
-                               PROC
-  196 00000014                 EXPORT           DebugMon_Handler           [WEA
-K]
-  197 00000014 E7FE            B                .
-  198 00000016                 ENDP
-  199 00000016         PendSV_Handler
-                               PROC
-  200 00000016                 EXPORT           PendSV_Handler             [WEA
-K]
-  201 00000016 E7FE            B                .
-  202 00000018                 ENDP
-  203 00000018         SysTick_Handler
-                               PROC
-  204 00000018                 EXPORT           SysTick_Handler            [WEA
-K]
-  205 00000018 E7FE            B                .
-  206 0000001A                 ENDP
-  207 0000001A         
-  208 0000001A         Default_Handler
-                               PROC
-  209 0000001A         
-  210 0000001A                 EXPORT           WWDG_IRQHandler            [WEA
-K]
-
-
-
-ARM Macro Assembler    Page 6 
-
-
-  211 0000001A                 EXPORT           PVD_IRQHandler             [WEA
-K]
-  212 0000001A                 EXPORT           TAMPER_IRQHandler          [WEA
-K]
-  213 0000001A                 EXPORT           RTC_IRQHandler             [WEA
-K]
-  214 0000001A                 EXPORT           FLASH_IRQHandler           [WEA
-K]
-  215 0000001A                 EXPORT           RCC_IRQHandler             [WEA
-K]
-  216 0000001A                 EXPORT           EXTI0_IRQHandler           [WEA
-K]
-  217 0000001A                 EXPORT           EXTI1_IRQHandler           [WEA
-K]
-  218 0000001A                 EXPORT           EXTI2_IRQHandler           [WEA
-K]
-  219 0000001A                 EXPORT           EXTI3_IRQHandler           [WEA
-K]
-  220 0000001A                 EXPORT           EXTI4_IRQHandler           [WEA
-K]
-  221 0000001A                 EXPORT           DMA1_Channel1_IRQHandler   [WEA
-K]
-  222 0000001A                 EXPORT           DMA1_Channel2_IRQHandler   [WEA
-K]
-  223 0000001A                 EXPORT           DMA1_Channel3_IRQHandler   [WEA
-K]
-  224 0000001A                 EXPORT           DMA1_Channel4_IRQHandler   [WEA
-K]
-  225 0000001A                 EXPORT           DMA1_Channel5_IRQHandler   [WEA
-K]
-  226 0000001A                 EXPORT           DMA1_Channel6_IRQHandler   [WEA
-K]
-  227 0000001A                 EXPORT           DMA1_Channel7_IRQHandler   [WEA
-K]
-  228 0000001A                 EXPORT           ADC1_2_IRQHandler          [WEA
-K]
-  229 0000001A                 EXPORT           CAN1_TX_IRQHandler         [WEA
-K]
-  230 0000001A                 EXPORT           CAN1_RX0_IRQHandler        [WEA
-K]
-  231 0000001A                 EXPORT           CAN1_RX1_IRQHandler        [WEA
-K]
-  232 0000001A                 EXPORT           CAN1_SCE_IRQHandler        [WEA
-K]
-  233 0000001A                 EXPORT           EXTI9_5_IRQHandler         [WEA
-K]
-  234 0000001A                 EXPORT           TIM1_BRK_IRQHandler        [WEA
-K]
-  235 0000001A                 EXPORT           TIM1_UP_IRQHandler         [WEA
-K]
-  236 0000001A                 EXPORT           TIM1_TRG_COM_IRQHandler    [WEA
-K]
-  237 0000001A                 EXPORT           TIM1_CC_IRQHandler         [WEA
-K]
-  238 0000001A                 EXPORT           TIM2_IRQHandler            [WEA
-K]
-  239 0000001A                 EXPORT           TIM3_IRQHandler            [WEA
-K]
-  240 0000001A                 EXPORT           TIM4_IRQHandler            [WEA
-
-
-
-ARM Macro Assembler    Page 7 
-
-
-K]
-  241 0000001A                 EXPORT           I2C1_EV_IRQHandler         [WEA
-K]
-  242 0000001A                 EXPORT           I2C1_ER_IRQHandler         [WEA
-K]
-  243 0000001A                 EXPORT           I2C2_EV_IRQHandler         [WEA
-K]
-  244 0000001A                 EXPORT           I2C2_ER_IRQHandler         [WEA
-K]
-  245 0000001A                 EXPORT           SPI1_IRQHandler            [WEA
-K]
-  246 0000001A                 EXPORT           SPI2_IRQHandler            [WEA
-K]
-  247 0000001A                 EXPORT           USART1_IRQHandler          [WEA
-K]
-  248 0000001A                 EXPORT           USART2_IRQHandler          [WEA
-K]
-  249 0000001A                 EXPORT           USART3_IRQHandler          [WEA
-K]
-  250 0000001A                 EXPORT           EXTI15_10_IRQHandler       [WEA
-K]
-  251 0000001A                 EXPORT           RTCAlarm_IRQHandler        [WEA
-K]
-  252 0000001A                 EXPORT           OTG_FS_WKUP_IRQHandler     [WEA
-K]
-  253 0000001A                 EXPORT           TIM5_IRQHandler            [WEA
-K]
-  254 0000001A                 EXPORT           SPI3_IRQHandler            [WEA
-K]
-  255 0000001A                 EXPORT           UART4_IRQHandler           [WEA
-K]
-  256 0000001A                 EXPORT           UART5_IRQHandler           [WEA
-K]
-  257 0000001A                 EXPORT           TIM6_IRQHandler            [WEA
-K]
-  258 0000001A                 EXPORT           TIM7_IRQHandler            [WEA
-K]
-  259 0000001A                 EXPORT           DMA2_Channel1_IRQHandler   [WEA
-K]
-  260 0000001A                 EXPORT           DMA2_Channel2_IRQHandler   [WEA
-K]
-  261 0000001A                 EXPORT           DMA2_Channel3_IRQHandler   [WEA
-K]
-  262 0000001A                 EXPORT           DMA2_Channel4_IRQHandler   [WEA
-K]
-  263 0000001A                 EXPORT           DMA2_Channel5_IRQHandler   [WEA
-K]
-  264 0000001A                 EXPORT           ETH_IRQHandler             [WEA
-K]
-  265 0000001A                 EXPORT           ETH_WKUP_IRQHandler        [WEA
-K]
-  266 0000001A                 EXPORT           CAN2_TX_IRQHandler         [WEA
-K]
-  267 0000001A                 EXPORT           CAN2_RX0_IRQHandler        [WEA
-K]
-  268 0000001A                 EXPORT           CAN2_RX1_IRQHandler        [WEA
-K]
-  269 0000001A                 EXPORT           CAN2_SCE_IRQHandler        [WEA
-K]
-
-
-
-ARM Macro Assembler    Page 8 
-
-
-  270 0000001A                 EXPORT           OTG_FS_IRQHandler          [WEA
-K]
-  271 0000001A         
-  272 0000001A         WWDG_IRQHandler
-  273 0000001A         PVD_IRQHandler
-  274 0000001A         TAMPER_IRQHandler
-  275 0000001A         RTC_IRQHandler
-  276 0000001A         FLASH_IRQHandler
-  277 0000001A         RCC_IRQHandler
-  278 0000001A         EXTI0_IRQHandler
-  279 0000001A         EXTI1_IRQHandler
-  280 0000001A         EXTI2_IRQHandler
-  281 0000001A         EXTI3_IRQHandler
-  282 0000001A         EXTI4_IRQHandler
-  283 0000001A         DMA1_Channel1_IRQHandler
-  284 0000001A         DMA1_Channel2_IRQHandler
-  285 0000001A         DMA1_Channel3_IRQHandler
-  286 0000001A         DMA1_Channel4_IRQHandler
-  287 0000001A         DMA1_Channel5_IRQHandler
-  288 0000001A         DMA1_Channel6_IRQHandler
-  289 0000001A         DMA1_Channel7_IRQHandler
-  290 0000001A         ADC1_2_IRQHandler
-  291 0000001A         CAN1_TX_IRQHandler
-  292 0000001A         CAN1_RX0_IRQHandler
-  293 0000001A         CAN1_RX1_IRQHandler
-  294 0000001A         CAN1_SCE_IRQHandler
-  295 0000001A         EXTI9_5_IRQHandler
-  296 0000001A         TIM1_BRK_IRQHandler
-  297 0000001A         TIM1_UP_IRQHandler
-  298 0000001A         TIM1_TRG_COM_IRQHandler
-  299 0000001A         TIM1_CC_IRQHandler
-  300 0000001A         TIM2_IRQHandler
-  301 0000001A         TIM3_IRQHandler
-  302 0000001A         TIM4_IRQHandler
-  303 0000001A         I2C1_EV_IRQHandler
-  304 0000001A         I2C1_ER_IRQHandler
-  305 0000001A         I2C2_EV_IRQHandler
-  306 0000001A         I2C2_ER_IRQHandler
-  307 0000001A         SPI1_IRQHandler
-  308 0000001A         SPI2_IRQHandler
-  309 0000001A         USART1_IRQHandler
-  310 0000001A         USART2_IRQHandler
-  311 0000001A         USART3_IRQHandler
-  312 0000001A         EXTI15_10_IRQHandler
-  313 0000001A         RTCAlarm_IRQHandler
-  314 0000001A         OTG_FS_WKUP_IRQHandler
-  315 0000001A         TIM5_IRQHandler
-  316 0000001A         SPI3_IRQHandler
-  317 0000001A         UART4_IRQHandler
-  318 0000001A         UART5_IRQHandler
-  319 0000001A         TIM6_IRQHandler
-  320 0000001A         TIM7_IRQHandler
-  321 0000001A         DMA2_Channel1_IRQHandler
-  322 0000001A         DMA2_Channel2_IRQHandler
-  323 0000001A         DMA2_Channel3_IRQHandler
-  324 0000001A         DMA2_Channel4_IRQHandler
-  325 0000001A         DMA2_Channel5_IRQHandler
-  326 0000001A         ETH_IRQHandler
-  327 0000001A         ETH_WKUP_IRQHandler
-
-
-
-ARM Macro Assembler    Page 9 
-
-
-  328 0000001A         CAN2_TX_IRQHandler
-  329 0000001A         CAN2_RX0_IRQHandler
-  330 0000001A         CAN2_RX1_IRQHandler
-  331 0000001A         CAN2_SCE_IRQHandler
-  332 0000001A         OTG_FS_IRQHandler
-  333 0000001A         
-  334 0000001A E7FE            B                .
-  335 0000001C         
-  336 0000001C                 ENDP
-  337 0000001C         
-  338 0000001C                 ALIGN
-  339 0000001C         
-  340 0000001C         ;*******************************************************
-                       ************************
-  341 0000001C         ; User Stack and Heap initialization
-  342 0000001C         ;*******************************************************
-                       ************************
-  343 0000001C                 IF               :DEF:__MICROLIB
-  344 0000001C         
-  345 0000001C                 EXPORT           __initial_sp
-  346 0000001C                 EXPORT           __heap_base
-  347 0000001C                 EXPORT           __heap_limit
-  348 0000001C         
-  349 0000001C                 ELSE
-  364                          ENDIF
-  365 0000001C         
-  366 0000001C                 END
-              00000000 
-              00000000 
-Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw
-ork --depend=.\objects\startup_stm32f10x_cl.d -o.\objects\startup_stm32f10x_cl.
-o -I.\RTE\Device\STM32F107VC -I.\RTE\_R_el -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.
-1\CMSIS\Include -IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include -
--predefine="__EVAL SETA 1" --predefine="__MICROLIB SETA 1" --predefine="__UVISI
-ON_VERSION SETA 524" --predefine="_RTE_ SETA 1" --predefine="STM32F10X_CL SETA 
-1" --predefine="STM32F10X_CL SETA 1" --list=.\listings\startup_stm32f10x_cl.lst
- RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-
-
-ARM Macro Assembler    Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-STACK 00000000
-
-Symbol: STACK
-   Definitions
-      At line 35 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      None
-Comment: STACK unused
-Stack_Mem 00000000
-
-Symbol: Stack_Mem
-   Definitions
-      At line 36 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      None
-Comment: Stack_Mem unused
-__initial_sp 00000400
-
-Symbol: __initial_sp
-   Definitions
-      At line 37 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 61 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 345 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-3 symbols
-
-
-
-ARM Macro Assembler    Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-HEAP 00000000
-
-Symbol: HEAP
-   Definitions
-      At line 46 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      None
-Comment: HEAP unused
-Heap_Mem 00000000
-
-Symbol: Heap_Mem
-   Definitions
-      At line 48 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      None
-Comment: Heap_Mem unused
-__heap_base 00000000
-
-Symbol: __heap_base
-   Definitions
-      At line 47 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 346 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-Comment: __heap_base used once
-__heap_limit 00000200
-
-Symbol: __heap_limit
-   Definitions
-      At line 49 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 347 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-Comment: __heap_limit used once
-4 symbols
-
-
-
-ARM Macro Assembler    Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-RESET 00000000
-
-Symbol: RESET
-   Definitions
-      At line 56 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      None
-Comment: RESET unused
-__Vectors 00000000
-
-Symbol: __Vectors
-   Definitions
-      At line 61 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 57 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 149 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-__Vectors_End 00000150
-
-Symbol: __Vectors_End
-   Definitions
-      At line 147 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 58 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 149 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-3 symbols
-
-
-
-ARM Macro Assembler    Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-.text 00000000
-
-Symbol: .text
-   Definitions
-      At line 151 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      None
-Comment: .text unused
-ADC1_2_IRQHandler 0000001A
-
-Symbol: ADC1_2_IRQHandler
-   Definitions
-      At line 290 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 97 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 228 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-BusFault_Handler 0000000E
-
-Symbol: BusFault_Handler
-   Definitions
-      At line 181 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 66 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 182 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-CAN1_RX0_IRQHandler 0000001A
-
-Symbol: CAN1_RX0_IRQHandler
-   Definitions
-      At line 292 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 99 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 230 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-CAN1_RX1_IRQHandler 0000001A
-
-Symbol: CAN1_RX1_IRQHandler
-   Definitions
-      At line 293 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 100 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 231 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-CAN1_SCE_IRQHandler 0000001A
-
-Symbol: CAN1_SCE_IRQHandler
-   Definitions
-      At line 294 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 101 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 232 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-CAN1_TX_IRQHandler 0000001A
-
-Symbol: CAN1_TX_IRQHandler
-   Definitions
-      At line 291 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-
-
-
-ARM Macro Assembler    Page 2 Alphabetic symbol ordering
-Relocatable symbols
-
-      At line 98 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 229 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-CAN2_RX0_IRQHandler 0000001A
-
-Symbol: CAN2_RX0_IRQHandler
-   Definitions
-      At line 329 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 143 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 267 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-CAN2_RX1_IRQHandler 0000001A
-
-Symbol: CAN2_RX1_IRQHandler
-   Definitions
-      At line 330 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 144 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 268 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-CAN2_SCE_IRQHandler 0000001A
-
-Symbol: CAN2_SCE_IRQHandler
-   Definitions
-      At line 331 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 145 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 269 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-CAN2_TX_IRQHandler 0000001A
-
-Symbol: CAN2_TX_IRQHandler
-   Definitions
-      At line 328 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 142 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 266 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-DMA1_Channel1_IRQHandler 0000001A
-
-Symbol: DMA1_Channel1_IRQHandler
-   Definitions
-      At line 283 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 90 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 221 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-DMA1_Channel2_IRQHandler 0000001A
-
-Symbol: DMA1_Channel2_IRQHandler
-   Definitions
-      At line 284 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 91 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 222 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-DMA1_Channel3_IRQHandler 0000001A
-
-
-
-
-ARM Macro Assembler    Page 3 Alphabetic symbol ordering
-Relocatable symbols
-
-Symbol: DMA1_Channel3_IRQHandler
-   Definitions
-      At line 285 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 92 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 223 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-DMA1_Channel4_IRQHandler 0000001A
-
-Symbol: DMA1_Channel4_IRQHandler
-   Definitions
-      At line 286 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 93 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 224 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-DMA1_Channel5_IRQHandler 0000001A
-
-Symbol: DMA1_Channel5_IRQHandler
-   Definitions
-      At line 287 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 94 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 225 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-DMA1_Channel6_IRQHandler 0000001A
-
-Symbol: DMA1_Channel6_IRQHandler
-   Definitions
-      At line 288 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 95 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 226 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-DMA1_Channel7_IRQHandler 0000001A
-
-Symbol: DMA1_Channel7_IRQHandler
-   Definitions
-      At line 289 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 96 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 227 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-DMA2_Channel1_IRQHandler 0000001A
-
-Symbol: DMA2_Channel1_IRQHandler
-   Definitions
-      At line 321 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 135 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 259 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-DMA2_Channel2_IRQHandler 0000001A
-
-Symbol: DMA2_Channel2_IRQHandler
-   Definitions
-      At line 322 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 136 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-
-
-ARM Macro Assembler    Page 4 Alphabetic symbol ordering
-Relocatable symbols
-
-      At line 260 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-DMA2_Channel3_IRQHandler 0000001A
-
-Symbol: DMA2_Channel3_IRQHandler
-   Definitions
-      At line 323 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 137 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 261 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-DMA2_Channel4_IRQHandler 0000001A
-
-Symbol: DMA2_Channel4_IRQHandler
-   Definitions
-      At line 324 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 138 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 262 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-DMA2_Channel5_IRQHandler 0000001A
-
-Symbol: DMA2_Channel5_IRQHandler
-   Definitions
-      At line 325 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 139 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 263 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-DebugMon_Handler 00000014
-
-Symbol: DebugMon_Handler
-   Definitions
-      At line 195 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 73 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 196 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-Default_Handler 0000001A
-
-Symbol: Default_Handler
-   Definitions
-      At line 208 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      None
-Comment: Default_Handler unused
-ETH_IRQHandler 0000001A
-
-Symbol: ETH_IRQHandler
-   Definitions
-      At line 326 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 140 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 264 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-ETH_WKUP_IRQHandler 0000001A
-
-Symbol: ETH_WKUP_IRQHandler
-   Definitions
-
-
-
-ARM Macro Assembler    Page 5 Alphabetic symbol ordering
-Relocatable symbols
-
-      At line 327 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 141 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 265 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-EXTI0_IRQHandler 0000001A
-
-Symbol: EXTI0_IRQHandler
-   Definitions
-      At line 278 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 85 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 216 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-EXTI15_10_IRQHandler 0000001A
-
-Symbol: EXTI15_10_IRQHandler
-   Definitions
-      At line 312 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 119 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 250 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-EXTI1_IRQHandler 0000001A
-
-Symbol: EXTI1_IRQHandler
-   Definitions
-      At line 279 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 86 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 217 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-EXTI2_IRQHandler 0000001A
-
-Symbol: EXTI2_IRQHandler
-   Definitions
-      At line 280 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 87 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 218 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-EXTI3_IRQHandler 0000001A
-
-Symbol: EXTI3_IRQHandler
-   Definitions
-      At line 281 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 88 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 219 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-EXTI4_IRQHandler 0000001A
-
-Symbol: EXTI4_IRQHandler
-   Definitions
-      At line 282 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 89 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 220 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-
-
-
-ARM Macro Assembler    Page 6 Alphabetic symbol ordering
-Relocatable symbols
-
-EXTI9_5_IRQHandler 0000001A
-
-Symbol: EXTI9_5_IRQHandler
-   Definitions
-      At line 295 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 102 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 233 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-FLASH_IRQHandler 0000001A
-
-Symbol: FLASH_IRQHandler
-   Definitions
-      At line 276 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 83 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 214 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-HardFault_Handler 0000000A
-
-Symbol: HardFault_Handler
-   Definitions
-      At line 171 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 64 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 172 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-I2C1_ER_IRQHandler 0000001A
-
-Symbol: I2C1_ER_IRQHandler
-   Definitions
-      At line 304 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 111 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 242 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-I2C1_EV_IRQHandler 0000001A
-
-Symbol: I2C1_EV_IRQHandler
-   Definitions
-      At line 303 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 110 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 241 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-I2C2_ER_IRQHandler 0000001A
-
-Symbol: I2C2_ER_IRQHandler
-   Definitions
-      At line 306 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 113 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 244 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-I2C2_EV_IRQHandler 0000001A
-
-Symbol: I2C2_EV_IRQHandler
-   Definitions
-      At line 305 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-
-
-ARM Macro Assembler    Page 7 Alphabetic symbol ordering
-Relocatable symbols
-
-   Uses
-      At line 112 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 243 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-MemManage_Handler 0000000C
-
-Symbol: MemManage_Handler
-   Definitions
-      At line 176 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 65 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 177 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-NMI_Handler 00000008
-
-Symbol: NMI_Handler
-   Definitions
-      At line 166 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 63 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 167 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-OTG_FS_IRQHandler 0000001A
-
-Symbol: OTG_FS_IRQHandler
-   Definitions
-      At line 332 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 146 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 270 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-OTG_FS_WKUP_IRQHandler 0000001A
-
-Symbol: OTG_FS_WKUP_IRQHandler
-   Definitions
-      At line 314 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 121 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 252 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-PVD_IRQHandler 0000001A
-
-Symbol: PVD_IRQHandler
-   Definitions
-      At line 273 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 80 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 211 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-PendSV_Handler 00000016
-
-Symbol: PendSV_Handler
-   Definitions
-      At line 199 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 75 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 200 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-RCC_IRQHandler 0000001A
-
-
-
-ARM Macro Assembler    Page 8 Alphabetic symbol ordering
-Relocatable symbols
-
-
-Symbol: RCC_IRQHandler
-   Definitions
-      At line 277 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 84 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 215 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-RTCAlarm_IRQHandler 0000001A
-
-Symbol: RTCAlarm_IRQHandler
-   Definitions
-      At line 313 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 120 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 251 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-RTC_IRQHandler 0000001A
-
-Symbol: RTC_IRQHandler
-   Definitions
-      At line 275 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 82 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 213 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-Reset_Handler 00000000
-
-Symbol: Reset_Handler
-   Definitions
-      At line 154 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 62 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 155 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-SPI1_IRQHandler 0000001A
-
-Symbol: SPI1_IRQHandler
-   Definitions
-      At line 307 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 114 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 245 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-SPI2_IRQHandler 0000001A
-
-Symbol: SPI2_IRQHandler
-   Definitions
-      At line 308 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 115 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 246 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-SPI3_IRQHandler 0000001A
-
-Symbol: SPI3_IRQHandler
-   Definitions
-      At line 316 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-
-
-
-ARM Macro Assembler    Page 9 Alphabetic symbol ordering
-Relocatable symbols
-
-      At line 130 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 254 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-SVC_Handler 00000012
-
-Symbol: SVC_Handler
-   Definitions
-      At line 190 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 72 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 191 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-SysTick_Handler 00000018
-
-Symbol: SysTick_Handler
-   Definitions
-      At line 203 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 76 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 204 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-TAMPER_IRQHandler 0000001A
-
-Symbol: TAMPER_IRQHandler
-   Definitions
-      At line 274 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 81 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 212 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-TIM1_BRK_IRQHandler 0000001A
-
-Symbol: TIM1_BRK_IRQHandler
-   Definitions
-      At line 296 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 103 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 234 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-TIM1_CC_IRQHandler 0000001A
-
-Symbol: TIM1_CC_IRQHandler
-   Definitions
-      At line 299 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 106 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 237 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-TIM1_TRG_COM_IRQHandler 0000001A
-
-Symbol: TIM1_TRG_COM_IRQHandler
-   Definitions
-      At line 298 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 105 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 236 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-TIM1_UP_IRQHandler 0000001A
-
-
-
-
-ARM Macro Assembler    Page 10 Alphabetic symbol ordering
-Relocatable symbols
-
-Symbol: TIM1_UP_IRQHandler
-   Definitions
-      At line 297 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 104 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 235 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-TIM2_IRQHandler 0000001A
-
-Symbol: TIM2_IRQHandler
-   Definitions
-      At line 300 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 107 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 238 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-TIM3_IRQHandler 0000001A
-
-Symbol: TIM3_IRQHandler
-   Definitions
-      At line 301 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 108 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 239 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-TIM4_IRQHandler 0000001A
-
-Symbol: TIM4_IRQHandler
-   Definitions
-      At line 302 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 109 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 240 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-TIM5_IRQHandler 0000001A
-
-Symbol: TIM5_IRQHandler
-   Definitions
-      At line 315 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 129 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 253 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-TIM6_IRQHandler 0000001A
-
-Symbol: TIM6_IRQHandler
-   Definitions
-      At line 319 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 133 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 257 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-TIM7_IRQHandler 0000001A
-
-Symbol: TIM7_IRQHandler
-   Definitions
-      At line 320 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 134 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-
-
-ARM Macro Assembler    Page 11 Alphabetic symbol ordering
-Relocatable symbols
-
-      At line 258 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-UART4_IRQHandler 0000001A
-
-Symbol: UART4_IRQHandler
-   Definitions
-      At line 317 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 131 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 255 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-UART5_IRQHandler 0000001A
-
-Symbol: UART5_IRQHandler
-   Definitions
-      At line 318 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 132 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 256 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-USART1_IRQHandler 0000001A
-
-Symbol: USART1_IRQHandler
-   Definitions
-      At line 309 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 116 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 247 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-USART2_IRQHandler 0000001A
-
-Symbol: USART2_IRQHandler
-   Definitions
-      At line 310 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 117 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 248 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-USART3_IRQHandler 0000001A
-
-Symbol: USART3_IRQHandler
-   Definitions
-      At line 311 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 118 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 249 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-UsageFault_Handler 00000010
-
-Symbol: UsageFault_Handler
-   Definitions
-      At line 186 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 67 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 187 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-WWDG_IRQHandler 0000001A
-
-Symbol: WWDG_IRQHandler
-
-
-
-ARM Macro Assembler    Page 12 Alphabetic symbol ordering
-Relocatable symbols
-
-   Definitions
-      At line 272 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 79 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-      At line 210 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-
-73 symbols
-
-
-
-ARM Macro Assembler    Page 1 Alphabetic symbol ordering
-Absolute symbols
-
-Heap_Size 00000200
-
-Symbol: Heap_Size
-   Definitions
-      At line 44 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 48 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-Comment: Heap_Size used once
-Stack_Size 00000400
-
-Symbol: Stack_Size
-   Definitions
-      At line 33 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 36 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-Comment: Stack_Size used once
-__Vectors_Size 00000150
-
-Symbol: __Vectors_Size
-   Definitions
-      At line 149 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 59 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-Comment: __Vectors_Size used once
-3 symbols
-
-
-
-ARM Macro Assembler    Page 1 Alphabetic symbol ordering
-External symbols
-
-SystemInit 00000000
-
-Symbol: SystemInit
-   Definitions
-      At line 156 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 158 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-Comment: SystemInit used once
-__main 00000000
-
-Symbol: __main
-   Definitions
-      At line 157 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-   Uses
-      At line 160 in file RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
-Comment: __main used once
-2 symbols
-425 symbols in table
diff --git a/Listings/startup_stm32f10x_md.lst b/Listings/startup_stm32f10x_md.lst
deleted file mode 100644
index 4459f0f..0000000
--- a/Listings/startup_stm32f10x_md.lst
+++ /dev/null
@@ -1,1182 +0,0 @@
-
-
-
-ARM Macro Assembler    Page 1 
-
-
-    1 00000000         ;******************** (C) COPYRIGHT 2011 STMicroelectron
-                       ics ********************
-    2 00000000         ;* File Name          : startup_stm32f10x_md.s
-    3 00000000         ;* Author             : MCD Application Team
-    4 00000000         ;* Version            : V3.5.0
-    5 00000000         ;* Date               : 11-March-2011
-    6 00000000         ;* Description        : STM32F10x Medium Density Devices
-                        vector table for MDK-ARM 
-    7 00000000         ;*                      toolchain.  
-    8 00000000         ;*                      This module performs:
-    9 00000000         ;*                      - Set the initial SP
-   10 00000000         ;*                      - Set the initial PC == Reset_Ha
-                       ndler
-   11 00000000         ;*                      - Set the vector table entries w
-                       ith the exceptions ISR address
-   12 00000000         ;*                      - Configure the clock system
-   13 00000000         ;*                      - Branches to __main in the C li
-                       brary (which eventually
-   14 00000000         ;*                        calls main()).
-   15 00000000         ;*                      After Reset the CortexM3 process
-                       or is in Thread mode,
-   16 00000000         ;*                      priority is Privileged, and the 
-                       Stack is set to Main.
-   17 00000000         ;* <<< Use Configuration Wizard in Context Menu >>>   
-   18 00000000         ;*******************************************************
-                       ************************
-   19 00000000         ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS A
-                       T PROVIDING CUSTOMERS
-   20 00000000         ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN OR
-                       DER FOR THEM TO SAVE TIME.
-   21 00000000         ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIAB
-                       LE FOR ANY DIRECT,
-   22 00000000         ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY 
-                       CLAIMS ARISING FROM THE
-   23 00000000         ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOM
-                       ERS OF THE CODING
-   24 00000000         ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR 
-                       PRODUCTS.
-   25 00000000         ;*******************************************************
-                       ************************
-   26 00000000         
-   27 00000000         ; Amount of memory (in bytes) allocated for Stack
-   28 00000000         ; Tailor this value to your application needs
-   29 00000000         ; <h> Stack Configuration
-   30 00000000         ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-   31 00000000         ; </h>
-   32 00000000         
-   33 00000000 00000400 
-                       Stack_Size
-                               EQU              0x00000400
-   34 00000000         
-   35 00000000                 AREA             STACK, NOINIT, READWRITE, ALIGN
-=3
-   36 00000000         Stack_Mem
-                               SPACE            Stack_Size
-   37 00000400         __initial_sp
-   38 00000400         
-   39 00000400         
-   40 00000400         ; <h> Heap Configuration
-
-
-
-ARM Macro Assembler    Page 2 
-
-
-   41 00000400         ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-   42 00000400         ; </h>
-   43 00000400         
-   44 00000400 00000200 
-                       Heap_Size
-                               EQU              0x00000200
-   45 00000400         
-   46 00000400                 AREA             HEAP, NOINIT, READWRITE, ALIGN=
-3
-   47 00000000         __heap_base
-   48 00000000         Heap_Mem
-                               SPACE            Heap_Size
-   49 00000200         __heap_limit
-   50 00000200         
-   51 00000200                 PRESERVE8
-   52 00000200                 THUMB
-   53 00000200         
-   54 00000200         
-   55 00000200         ; Vector Table Mapped to Address 0 at Reset
-   56 00000200                 AREA             RESET, DATA, READONLY
-   57 00000000                 EXPORT           __Vectors
-   58 00000000                 EXPORT           __Vectors_End
-   59 00000000                 EXPORT           __Vectors_Size
-   60 00000000         
-   61 00000000 00000000 
-                       __Vectors
-                               DCD              __initial_sp ; Top of Stack
-   62 00000004 00000000        DCD              Reset_Handler ; Reset Handler
-   63 00000008 00000000        DCD              NMI_Handler ; NMI Handler
-   64 0000000C 00000000        DCD              HardFault_Handler ; Hard Fault 
-                                                            Handler
-   65 00000010 00000000        DCD              MemManage_Handler 
-                                                            ; MPU Fault Handler
-                                                            
-   66 00000014 00000000        DCD              BusFault_Handler 
-                                                            ; Bus Fault Handler
-                                                            
-   67 00000018 00000000        DCD              UsageFault_Handler ; Usage Faul
-                                                            t Handler
-   68 0000001C 00000000        DCD              0           ; Reserved
-   69 00000020 00000000        DCD              0           ; Reserved
-   70 00000024 00000000        DCD              0           ; Reserved
-   71 00000028 00000000        DCD              0           ; Reserved
-   72 0000002C 00000000        DCD              SVC_Handler ; SVCall Handler
-   73 00000030 00000000        DCD              DebugMon_Handler ; Debug Monito
-                                                            r Handler
-   74 00000034 00000000        DCD              0           ; Reserved
-   75 00000038 00000000        DCD              PendSV_Handler ; PendSV Handler
-                                                            
-   76 0000003C 00000000        DCD              SysTick_Handler 
-                                                            ; SysTick Handler
-   77 00000040         
-   78 00000040         ; External Interrupts
-   79 00000040 00000000        DCD              WWDG_IRQHandler 
-                                                            ; Window Watchdog
-   80 00000044 00000000        DCD              PVD_IRQHandler ; PVD through EX
-                                                            TI Line detect
-   81 00000048 00000000        DCD              TAMPER_IRQHandler ; Tamper
-   82 0000004C 00000000        DCD              RTC_IRQHandler ; RTC
-
-
-
-ARM Macro Assembler    Page 3 
-
-
-   83 00000050 00000000        DCD              FLASH_IRQHandler ; Flash
-   84 00000054 00000000        DCD              RCC_IRQHandler ; RCC
-   85 00000058 00000000        DCD              EXTI0_IRQHandler ; EXTI Line 0
-   86 0000005C 00000000        DCD              EXTI1_IRQHandler ; EXTI Line 1
-   87 00000060 00000000        DCD              EXTI2_IRQHandler ; EXTI Line 2
-   88 00000064 00000000        DCD              EXTI3_IRQHandler ; EXTI Line 3
-   89 00000068 00000000        DCD              EXTI4_IRQHandler ; EXTI Line 4
-   90 0000006C 00000000        DCD              DMA1_Channel1_IRQHandler 
-                                                            ; DMA1 Channel 1
-   91 00000070 00000000        DCD              DMA1_Channel2_IRQHandler 
-                                                            ; DMA1 Channel 2
-   92 00000074 00000000        DCD              DMA1_Channel3_IRQHandler 
-                                                            ; DMA1 Channel 3
-   93 00000078 00000000        DCD              DMA1_Channel4_IRQHandler 
-                                                            ; DMA1 Channel 4
-   94 0000007C 00000000        DCD              DMA1_Channel5_IRQHandler 
-                                                            ; DMA1 Channel 5
-   95 00000080 00000000        DCD              DMA1_Channel6_IRQHandler 
-                                                            ; DMA1 Channel 6
-   96 00000084 00000000        DCD              DMA1_Channel7_IRQHandler 
-                                                            ; DMA1 Channel 7
-   97 00000088 00000000        DCD              ADC1_2_IRQHandler ; ADC1_2
-   98 0000008C 00000000        DCD              USB_HP_CAN1_TX_IRQHandler ; USB
-                                                             High Priority or C
-                                                            AN1 TX
-   99 00000090 00000000        DCD              USB_LP_CAN1_RX0_IRQHandler ; US
-                                                            B Low  Priority or 
-                                                            CAN1 RX0
-  100 00000094 00000000        DCD              CAN1_RX1_IRQHandler ; CAN1 RX1
-  101 00000098 00000000        DCD              CAN1_SCE_IRQHandler ; CAN1 SCE
-  102 0000009C 00000000        DCD              EXTI9_5_IRQHandler 
-                                                            ; EXTI Line 9..5
-  103 000000A0 00000000        DCD              TIM1_BRK_IRQHandler 
-                                                            ; TIM1 Break
-  104 000000A4 00000000        DCD              TIM1_UP_IRQHandler 
-                                                            ; TIM1 Update
-  105 000000A8 00000000        DCD              TIM1_TRG_COM_IRQHandler ; TIM1 
-                                                            Trigger and Commuta
-                                                            tion
-  106 000000AC 00000000        DCD              TIM1_CC_IRQHandler ; TIM1 Captu
-                                                            re Compare
-  107 000000B0 00000000        DCD              TIM2_IRQHandler ; TIM2
-  108 000000B4 00000000        DCD              TIM3_IRQHandler ; TIM3
-  109 000000B8 00000000        DCD              TIM4_IRQHandler ; TIM4
-  110 000000BC 00000000        DCD              I2C1_EV_IRQHandler ; I2C1 Event
-                                                            
-  111 000000C0 00000000        DCD              I2C1_ER_IRQHandler ; I2C1 Error
-                                                            
-  112 000000C4 00000000        DCD              I2C2_EV_IRQHandler ; I2C2 Event
-                                                            
-  113 000000C8 00000000        DCD              I2C2_ER_IRQHandler ; I2C2 Error
-                                                            
-  114 000000CC 00000000        DCD              SPI1_IRQHandler ; SPI1
-  115 000000D0 00000000        DCD              SPI2_IRQHandler ; SPI2
-  116 000000D4 00000000        DCD              USART1_IRQHandler ; USART1
-  117 000000D8 00000000        DCD              USART2_IRQHandler ; USART2
-  118 000000DC 00000000        DCD              USART3_IRQHandler ; USART3
-  119 000000E0 00000000        DCD              EXTI15_10_IRQHandler 
-                                                            ; EXTI Line 15..10
-
-
-
-ARM Macro Assembler    Page 4 
-
-
-  120 000000E4 00000000        DCD              RTCAlarm_IRQHandler ; RTC Alarm
-                                                             through EXTI Line
-  121 000000E8 00000000        DCD              USBWakeUp_IRQHandler ; USB Wake
-                                                            up from suspend
-  122 000000EC         __Vectors_End
-  123 000000EC         
-  124 000000EC 000000EC 
-                       __Vectors_Size
-                               EQU              __Vectors_End - __Vectors
-  125 000000EC         
-  126 000000EC                 AREA             |.text|, CODE, READONLY
-  127 00000000         
-  128 00000000         ; Reset handler
-  129 00000000         Reset_Handler
-                               PROC
-  130 00000000                 EXPORT           Reset_Handler             [WEAK
-]
-  131 00000000                 IMPORT           __main
-  132 00000000                 IMPORT           SystemInit
-  133 00000000 4806            LDR              R0, =SystemInit
-  134 00000002 4780            BLX              R0
-  135 00000004 4806            LDR              R0, =__main
-  136 00000006 4700            BX               R0
-  137 00000008                 ENDP
-  138 00000008         
-  139 00000008         ; Dummy Exception Handlers (infinite loops which can be 
-                       modified)
-  140 00000008         
-  141 00000008         NMI_Handler
-                               PROC
-  142 00000008                 EXPORT           NMI_Handler                [WEA
-K]
-  143 00000008 E7FE            B                .
-  144 0000000A                 ENDP
-  146 0000000A         HardFault_Handler
-                               PROC
-  147 0000000A                 EXPORT           HardFault_Handler          [WEA
-K]
-  148 0000000A E7FE            B                .
-  149 0000000C                 ENDP
-  151 0000000C         MemManage_Handler
-                               PROC
-  152 0000000C                 EXPORT           MemManage_Handler          [WEA
-K]
-  153 0000000C E7FE            B                .
-  154 0000000E                 ENDP
-  156 0000000E         BusFault_Handler
-                               PROC
-  157 0000000E                 EXPORT           BusFault_Handler           [WEA
-K]
-  158 0000000E E7FE            B                .
-  159 00000010                 ENDP
-  161 00000010         UsageFault_Handler
-                               PROC
-  162 00000010                 EXPORT           UsageFault_Handler         [WEA
-K]
-  163 00000010 E7FE            B                .
-  164 00000012                 ENDP
-  165 00000012         SVC_Handler
-
-
-
-ARM Macro Assembler    Page 5 
-
-
-                               PROC
-  166 00000012                 EXPORT           SVC_Handler                [WEA
-K]
-  167 00000012 E7FE            B                .
-  168 00000014                 ENDP
-  170 00000014         DebugMon_Handler
-                               PROC
-  171 00000014                 EXPORT           DebugMon_Handler           [WEA
-K]
-  172 00000014 E7FE            B                .
-  173 00000016                 ENDP
-  174 00000016         PendSV_Handler
-                               PROC
-  175 00000016                 EXPORT           PendSV_Handler             [WEA
-K]
-  176 00000016 E7FE            B                .
-  177 00000018                 ENDP
-  178 00000018         SysTick_Handler
-                               PROC
-  179 00000018                 EXPORT           SysTick_Handler            [WEA
-K]
-  180 00000018 E7FE            B                .
-  181 0000001A                 ENDP
-  182 0000001A         
-  183 0000001A         Default_Handler
-                               PROC
-  184 0000001A         
-  185 0000001A                 EXPORT           WWDG_IRQHandler            [WEA
-K]
-  186 0000001A                 EXPORT           PVD_IRQHandler             [WEA
-K]
-  187 0000001A                 EXPORT           TAMPER_IRQHandler          [WEA
-K]
-  188 0000001A                 EXPORT           RTC_IRQHandler             [WEA
-K]
-  189 0000001A                 EXPORT           FLASH_IRQHandler           [WEA
-K]
-  190 0000001A                 EXPORT           RCC_IRQHandler             [WEA
-K]
-  191 0000001A                 EXPORT           EXTI0_IRQHandler           [WEA
-K]
-  192 0000001A                 EXPORT           EXTI1_IRQHandler           [WEA
-K]
-  193 0000001A                 EXPORT           EXTI2_IRQHandler           [WEA
-K]
-  194 0000001A                 EXPORT           EXTI3_IRQHandler           [WEA
-K]
-  195 0000001A                 EXPORT           EXTI4_IRQHandler           [WEA
-K]
-  196 0000001A                 EXPORT           DMA1_Channel1_IRQHandler   [WEA
-K]
-  197 0000001A                 EXPORT           DMA1_Channel2_IRQHandler   [WEA
-K]
-  198 0000001A                 EXPORT           DMA1_Channel3_IRQHandler   [WEA
-K]
-  199 0000001A                 EXPORT           DMA1_Channel4_IRQHandler   [WEA
-K]
-  200 0000001A                 EXPORT           DMA1_Channel5_IRQHandler   [WEA
-K]
-
-
-
-ARM Macro Assembler    Page 6 
-
-
-  201 0000001A                 EXPORT           DMA1_Channel6_IRQHandler   [WEA
-K]
-  202 0000001A                 EXPORT           DMA1_Channel7_IRQHandler   [WEA
-K]
-  203 0000001A                 EXPORT           ADC1_2_IRQHandler          [WEA
-K]
-  204 0000001A                 EXPORT           USB_HP_CAN1_TX_IRQHandler  [WEA
-K]
-  205 0000001A                 EXPORT           USB_LP_CAN1_RX0_IRQHandler [WEA
-K]
-  206 0000001A                 EXPORT           CAN1_RX1_IRQHandler        [WEA
-K]
-  207 0000001A                 EXPORT           CAN1_SCE_IRQHandler        [WEA
-K]
-  208 0000001A                 EXPORT           EXTI9_5_IRQHandler         [WEA
-K]
-  209 0000001A                 EXPORT           TIM1_BRK_IRQHandler        [WEA
-K]
-  210 0000001A                 EXPORT           TIM1_UP_IRQHandler         [WEA
-K]
-  211 0000001A                 EXPORT           TIM1_TRG_COM_IRQHandler    [WEA
-K]
-  212 0000001A                 EXPORT           TIM1_CC_IRQHandler         [WEA
-K]
-  213 0000001A                 EXPORT           TIM2_IRQHandler            [WEA
-K]
-  214 0000001A                 EXPORT           TIM3_IRQHandler            [WEA
-K]
-  215 0000001A                 EXPORT           TIM4_IRQHandler            [WEA
-K]
-  216 0000001A                 EXPORT           I2C1_EV_IRQHandler         [WEA
-K]
-  217 0000001A                 EXPORT           I2C1_ER_IRQHandler         [WEA
-K]
-  218 0000001A                 EXPORT           I2C2_EV_IRQHandler         [WEA
-K]
-  219 0000001A                 EXPORT           I2C2_ER_IRQHandler         [WEA
-K]
-  220 0000001A                 EXPORT           SPI1_IRQHandler            [WEA
-K]
-  221 0000001A                 EXPORT           SPI2_IRQHandler            [WEA
-K]
-  222 0000001A                 EXPORT           USART1_IRQHandler          [WEA
-K]
-  223 0000001A                 EXPORT           USART2_IRQHandler          [WEA
-K]
-  224 0000001A                 EXPORT           USART3_IRQHandler          [WEA
-K]
-  225 0000001A                 EXPORT           EXTI15_10_IRQHandler       [WEA
-K]
-  226 0000001A                 EXPORT           RTCAlarm_IRQHandler        [WEA
-K]
-  227 0000001A                 EXPORT           USBWakeUp_IRQHandler       [WEA
-K]
-  228 0000001A         
-  229 0000001A         WWDG_IRQHandler
-  230 0000001A         PVD_IRQHandler
-  231 0000001A         TAMPER_IRQHandler
-  232 0000001A         RTC_IRQHandler
-
-
-
-ARM Macro Assembler    Page 7 
-
-
-  233 0000001A         FLASH_IRQHandler
-  234 0000001A         RCC_IRQHandler
-  235 0000001A         EXTI0_IRQHandler
-  236 0000001A         EXTI1_IRQHandler
-  237 0000001A         EXTI2_IRQHandler
-  238 0000001A         EXTI3_IRQHandler
-  239 0000001A         EXTI4_IRQHandler
-  240 0000001A         DMA1_Channel1_IRQHandler
-  241 0000001A         DMA1_Channel2_IRQHandler
-  242 0000001A         DMA1_Channel3_IRQHandler
-  243 0000001A         DMA1_Channel4_IRQHandler
-  244 0000001A         DMA1_Channel5_IRQHandler
-  245 0000001A         DMA1_Channel6_IRQHandler
-  246 0000001A         DMA1_Channel7_IRQHandler
-  247 0000001A         ADC1_2_IRQHandler
-  248 0000001A         USB_HP_CAN1_TX_IRQHandler
-  249 0000001A         USB_LP_CAN1_RX0_IRQHandler
-  250 0000001A         CAN1_RX1_IRQHandler
-  251 0000001A         CAN1_SCE_IRQHandler
-  252 0000001A         EXTI9_5_IRQHandler
-  253 0000001A         TIM1_BRK_IRQHandler
-  254 0000001A         TIM1_UP_IRQHandler
-  255 0000001A         TIM1_TRG_COM_IRQHandler
-  256 0000001A         TIM1_CC_IRQHandler
-  257 0000001A         TIM2_IRQHandler
-  258 0000001A         TIM3_IRQHandler
-  259 0000001A         TIM4_IRQHandler
-  260 0000001A         I2C1_EV_IRQHandler
-  261 0000001A         I2C1_ER_IRQHandler
-  262 0000001A         I2C2_EV_IRQHandler
-  263 0000001A         I2C2_ER_IRQHandler
-  264 0000001A         SPI1_IRQHandler
-  265 0000001A         SPI2_IRQHandler
-  266 0000001A         USART1_IRQHandler
-  267 0000001A         USART2_IRQHandler
-  268 0000001A         USART3_IRQHandler
-  269 0000001A         EXTI15_10_IRQHandler
-  270 0000001A         RTCAlarm_IRQHandler
-  271 0000001A         USBWakeUp_IRQHandler
-  272 0000001A         
-  273 0000001A E7FE            B                .
-  274 0000001C         
-  275 0000001C                 ENDP
-  276 0000001C         
-  277 0000001C                 ALIGN
-  278 0000001C         
-  279 0000001C         ;*******************************************************
-                       ************************
-  280 0000001C         ; User Stack and Heap initialization
-  281 0000001C         ;*******************************************************
-                       ************************
-  282 0000001C                 IF               :DEF:__MICROLIB
-  283 0000001C         
-  284 0000001C                 EXPORT           __initial_sp
-  285 0000001C                 EXPORT           __heap_base
-  286 0000001C                 EXPORT           __heap_limit
-  287 0000001C         
-  288 0000001C                 ELSE
-  303                          ENDIF
-
-
-
-ARM Macro Assembler    Page 8 
-
-
-  304 0000001C         
-  305 0000001C                 END
-              00000000 
-              00000000 
-Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw
-ork --depend=.\objects\startup_stm32f10x_md.d -o.\objects\startup_stm32f10x_md.
-o -I.\RTE\Device\STM32F103RB -I.\RTE\_Simul_ -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.
-0.1\CMSIS\Include -IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include
- -IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc -IC
-:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\RTE_Driver --predefine="__EVAL SETA
- 1" --predefine="__MICROLIB SETA 1" --predefine="__UVISION_VERSION SETA 524" --
-predefine="_RTE_ SETA 1" --predefine="STM32F10X_MD SETA 1" --predefine="STM32F1
-0X_MD SETA 1" --list=.\listings\startup_stm32f10x_md.lst RTE\Device\STM32F103RB
-\startup_stm32f10x_md.s
-
-
-
-ARM Macro Assembler    Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-STACK 00000000
-
-Symbol: STACK
-   Definitions
-      At line 35 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      None
-Comment: STACK unused
-Stack_Mem 00000000
-
-Symbol: Stack_Mem
-   Definitions
-      At line 36 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      None
-Comment: Stack_Mem unused
-__initial_sp 00000400
-
-Symbol: __initial_sp
-   Definitions
-      At line 37 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 61 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 284 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-3 symbols
-
-
-
-ARM Macro Assembler    Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-HEAP 00000000
-
-Symbol: HEAP
-   Definitions
-      At line 46 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      None
-Comment: HEAP unused
-Heap_Mem 00000000
-
-Symbol: Heap_Mem
-   Definitions
-      At line 48 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      None
-Comment: Heap_Mem unused
-__heap_base 00000000
-
-Symbol: __heap_base
-   Definitions
-      At line 47 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 285 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: __heap_base used once
-__heap_limit 00000200
-
-Symbol: __heap_limit
-   Definitions
-      At line 49 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 286 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: __heap_limit used once
-4 symbols
-
-
-
-ARM Macro Assembler    Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-RESET 00000000
-
-Symbol: RESET
-   Definitions
-      At line 56 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      None
-Comment: RESET unused
-__Vectors 00000000
-
-Symbol: __Vectors
-   Definitions
-      At line 61 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 57 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-__Vectors_End 000000EC
-
-Symbol: __Vectors_End
-   Definitions
-      At line 122 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 58 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-3 symbols
-
-
-
-ARM Macro Assembler    Page 1 Alphabetic symbol ordering
-Relocatable symbols
-
-.text 00000000
-
-Symbol: .text
-   Definitions
-      At line 126 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      None
-Comment: .text unused
-ADC1_2_IRQHandler 0000001A
-
-Symbol: ADC1_2_IRQHandler
-   Definitions
-      At line 247 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 97 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 203 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-BusFault_Handler 0000000E
-
-Symbol: BusFault_Handler
-   Definitions
-      At line 156 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 66 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 157 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-CAN1_RX1_IRQHandler 0000001A
-
-Symbol: CAN1_RX1_IRQHandler
-   Definitions
-      At line 250 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 100 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 206 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-CAN1_SCE_IRQHandler 0000001A
-
-Symbol: CAN1_SCE_IRQHandler
-   Definitions
-      At line 251 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 101 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 207 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel1_IRQHandler 0000001A
-
-Symbol: DMA1_Channel1_IRQHandler
-   Definitions
-      At line 240 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 90 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 196 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel2_IRQHandler 0000001A
-
-Symbol: DMA1_Channel2_IRQHandler
-   Definitions
-      At line 241 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-
-
-
-ARM Macro Assembler    Page 2 Alphabetic symbol ordering
-Relocatable symbols
-
-      At line 91 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 197 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel3_IRQHandler 0000001A
-
-Symbol: DMA1_Channel3_IRQHandler
-   Definitions
-      At line 242 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 92 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 198 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel4_IRQHandler 0000001A
-
-Symbol: DMA1_Channel4_IRQHandler
-   Definitions
-      At line 243 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 93 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 199 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel5_IRQHandler 0000001A
-
-Symbol: DMA1_Channel5_IRQHandler
-   Definitions
-      At line 244 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 94 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 200 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel6_IRQHandler 0000001A
-
-Symbol: DMA1_Channel6_IRQHandler
-   Definitions
-      At line 245 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 95 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 201 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DMA1_Channel7_IRQHandler 0000001A
-
-Symbol: DMA1_Channel7_IRQHandler
-   Definitions
-      At line 246 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 96 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 202 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-DebugMon_Handler 00000014
-
-Symbol: DebugMon_Handler
-   Definitions
-      At line 170 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 73 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 171 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-Default_Handler 0000001A
-
-
-
-
-ARM Macro Assembler    Page 3 Alphabetic symbol ordering
-Relocatable symbols
-
-Symbol: Default_Handler
-   Definitions
-      At line 183 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      None
-Comment: Default_Handler unused
-EXTI0_IRQHandler 0000001A
-
-Symbol: EXTI0_IRQHandler
-   Definitions
-      At line 235 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 85 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 191 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-EXTI15_10_IRQHandler 0000001A
-
-Symbol: EXTI15_10_IRQHandler
-   Definitions
-      At line 269 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 119 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 225 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-EXTI1_IRQHandler 0000001A
-
-Symbol: EXTI1_IRQHandler
-   Definitions
-      At line 236 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 86 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 192 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-EXTI2_IRQHandler 0000001A
-
-Symbol: EXTI2_IRQHandler
-   Definitions
-      At line 237 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 87 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 193 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-EXTI3_IRQHandler 0000001A
-
-Symbol: EXTI3_IRQHandler
-   Definitions
-      At line 238 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 88 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 194 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-EXTI4_IRQHandler 0000001A
-
-Symbol: EXTI4_IRQHandler
-   Definitions
-      At line 239 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 89 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 195 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-
-
-ARM Macro Assembler    Page 4 Alphabetic symbol ordering
-Relocatable symbols
-
-
-EXTI9_5_IRQHandler 0000001A
-
-Symbol: EXTI9_5_IRQHandler
-   Definitions
-      At line 252 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 102 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 208 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-FLASH_IRQHandler 0000001A
-
-Symbol: FLASH_IRQHandler
-   Definitions
-      At line 233 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 83 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 189 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-HardFault_Handler 0000000A
-
-Symbol: HardFault_Handler
-   Definitions
-      At line 146 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 64 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 147 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-I2C1_ER_IRQHandler 0000001A
-
-Symbol: I2C1_ER_IRQHandler
-   Definitions
-      At line 261 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 111 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 217 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-I2C1_EV_IRQHandler 0000001A
-
-Symbol: I2C1_EV_IRQHandler
-   Definitions
-      At line 260 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 110 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 216 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-I2C2_ER_IRQHandler 0000001A
-
-Symbol: I2C2_ER_IRQHandler
-   Definitions
-      At line 263 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 113 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 219 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-I2C2_EV_IRQHandler 0000001A
-
-Symbol: I2C2_EV_IRQHandler
-   Definitions
-
-
-
-ARM Macro Assembler    Page 5 Alphabetic symbol ordering
-Relocatable symbols
-
-      At line 262 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 112 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 218 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-MemManage_Handler 0000000C
-
-Symbol: MemManage_Handler
-   Definitions
-      At line 151 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 65 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 152 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-NMI_Handler 00000008
-
-Symbol: NMI_Handler
-   Definitions
-      At line 141 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 63 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 142 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-PVD_IRQHandler 0000001A
-
-Symbol: PVD_IRQHandler
-   Definitions
-      At line 230 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 80 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 186 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-PendSV_Handler 00000016
-
-Symbol: PendSV_Handler
-   Definitions
-      At line 174 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 75 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 175 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-RCC_IRQHandler 0000001A
-
-Symbol: RCC_IRQHandler
-   Definitions
-      At line 234 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 84 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 190 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-RTCAlarm_IRQHandler 0000001A
-
-Symbol: RTCAlarm_IRQHandler
-   Definitions
-      At line 270 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 120 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 226 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-
-
-
-ARM Macro Assembler    Page 6 Alphabetic symbol ordering
-Relocatable symbols
-
-RTC_IRQHandler 0000001A
-
-Symbol: RTC_IRQHandler
-   Definitions
-      At line 232 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 82 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 188 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-Reset_Handler 00000000
-
-Symbol: Reset_Handler
-   Definitions
-      At line 129 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 62 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 130 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-SPI1_IRQHandler 0000001A
-
-Symbol: SPI1_IRQHandler
-   Definitions
-      At line 264 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 114 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 220 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-SPI2_IRQHandler 0000001A
-
-Symbol: SPI2_IRQHandler
-   Definitions
-      At line 265 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 115 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 221 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-SVC_Handler 00000012
-
-Symbol: SVC_Handler
-   Definitions
-      At line 165 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 72 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 166 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-SysTick_Handler 00000018
-
-Symbol: SysTick_Handler
-   Definitions
-      At line 178 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 76 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 179 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TAMPER_IRQHandler 0000001A
-
-Symbol: TAMPER_IRQHandler
-   Definitions
-      At line 231 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-
-
-ARM Macro Assembler    Page 7 Alphabetic symbol ordering
-Relocatable symbols
-
-   Uses
-      At line 81 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 187 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM1_BRK_IRQHandler 0000001A
-
-Symbol: TIM1_BRK_IRQHandler
-   Definitions
-      At line 253 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 103 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 209 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM1_CC_IRQHandler 0000001A
-
-Symbol: TIM1_CC_IRQHandler
-   Definitions
-      At line 256 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 106 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 212 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM1_TRG_COM_IRQHandler 0000001A
-
-Symbol: TIM1_TRG_COM_IRQHandler
-   Definitions
-      At line 255 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 105 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 211 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM1_UP_IRQHandler 0000001A
-
-Symbol: TIM1_UP_IRQHandler
-   Definitions
-      At line 254 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 104 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 210 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM2_IRQHandler 0000001A
-
-Symbol: TIM2_IRQHandler
-   Definitions
-      At line 257 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 107 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 213 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM3_IRQHandler 0000001A
-
-Symbol: TIM3_IRQHandler
-   Definitions
-      At line 258 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 108 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 214 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-TIM4_IRQHandler 0000001A
-
-
-
-ARM Macro Assembler    Page 8 Alphabetic symbol ordering
-Relocatable symbols
-
-
-Symbol: TIM4_IRQHandler
-   Definitions
-      At line 259 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 109 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 215 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USART1_IRQHandler 0000001A
-
-Symbol: USART1_IRQHandler
-   Definitions
-      At line 266 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 116 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 222 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USART2_IRQHandler 0000001A
-
-Symbol: USART2_IRQHandler
-   Definitions
-      At line 267 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 117 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 223 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USART3_IRQHandler 0000001A
-
-Symbol: USART3_IRQHandler
-   Definitions
-      At line 268 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 118 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 224 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USBWakeUp_IRQHandler 0000001A
-
-Symbol: USBWakeUp_IRQHandler
-   Definitions
-      At line 271 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 121 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 227 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USB_HP_CAN1_TX_IRQHandler 0000001A
-
-Symbol: USB_HP_CAN1_TX_IRQHandler
-   Definitions
-      At line 248 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 98 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 204 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-USB_LP_CAN1_RX0_IRQHandler 0000001A
-
-Symbol: USB_LP_CAN1_RX0_IRQHandler
-   Definitions
-      At line 249 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-
-
-
-ARM Macro Assembler    Page 9 Alphabetic symbol ordering
-Relocatable symbols
-
-      At line 99 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 205 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-UsageFault_Handler 00000010
-
-Symbol: UsageFault_Handler
-   Definitions
-      At line 161 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 67 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 162 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-WWDG_IRQHandler 0000001A
-
-Symbol: WWDG_IRQHandler
-   Definitions
-      At line 229 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 79 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-      At line 185 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-
-55 symbols
-
-
-
-ARM Macro Assembler    Page 1 Alphabetic symbol ordering
-Absolute symbols
-
-Heap_Size 00000200
-
-Symbol: Heap_Size
-   Definitions
-      At line 44 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 48 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: Heap_Size used once
-Stack_Size 00000400
-
-Symbol: Stack_Size
-   Definitions
-      At line 33 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 36 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: Stack_Size used once
-__Vectors_Size 000000EC
-
-Symbol: __Vectors_Size
-   Definitions
-      At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 59 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: __Vectors_Size used once
-3 symbols
-
-
-
-ARM Macro Assembler    Page 1 Alphabetic symbol ordering
-External symbols
-
-SystemInit 00000000
-
-Symbol: SystemInit
-   Definitions
-      At line 132 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 133 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: SystemInit used once
-__main 00000000
-
-Symbol: __main
-   Definitions
-      At line 131 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-   Uses
-      At line 135 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s
-Comment: __main used once
-2 symbols
-407 symbols in table
diff --git a/Lumiere.asm b/Lumiere.asm
new file mode 100644
index 0000000..a52a5bd
--- /dev/null
+++ b/Lumiere.asm
@@ -0,0 +1,34 @@
+;***************************************************************************
+	THUMB	
+	REQUIRE8
+	PRESERVE8
+
+;**************************************************************************
+;  Lumiere.asm
+; Auteur : Yohan Boujon et Simon Paris
+; Date :  16/03/2023
+;**************************************************************************
+
+;***************IMPORT/EXPORT**********************************************
+
+
+
+;**************************************************************************
+
+
+
+;***************CONSTANTES*************************************************
+
+	include REG_UTILES.inc 
+
+;**************************************************************************
+
+;***************VARIABLES**************************************************
+	 AREA  MesDonnees, data, readwrite
+;**************************************************************************
+
+;***************CODE*******************************************************
+   	AREA  moncode, code, readonly
+;**************************************************************************
+	
+END
\ No newline at end of file
diff --git a/Mire.asm b/Mire.asm
new file mode 100644
index 0000000..683bc21
--- /dev/null
+++ b/Mire.asm
@@ -0,0 +1,68 @@
+;************************************************************************
+	THUMB	
+	REQUIRE8
+	PRESERVE8
+;************************************************************************
+
+
+;**************************************
+;     Affectation des bits GPIO 	
+;***************************************
+; GSLCK..... PA0 
+; DSPRG..... PA1 
+; BLANK..... PA2 
+; XLAT...... PA3
+; VPRG...... PA4
+; SCLK...... PA5
+; SIN1...... PA7
+;Capteur.....PA8
+
+;LED.........PB10
+;****************************************/
+
+
+;***************CONSTANTES*************************************************
+
+
+Nbsecteurs		   equ 8
+PuissanceNbSecteur equ 3
+
+
+
+
+
+;************************************************************************
+; 					IMPORT/EXPORT Système
+;************************************************************************
+
+	IMPORT ||Lib$$Request$$armlib|| [CODE,WEAK]
+
+
+; IMPORT/EXPORT de procédure           
+
+
+
+	EXPORT mire
+
+;*******************************************************************************
+
+
+;*******************************************************************************
+	AREA  mesdonnees, data, readonly
+
+
+		
+mire DCB 255,0,0, 255,0,0, 255,0,0, 255,0,0, 255,0,0, 255,0,0, 255,0,0, 255,0,0, 255,0,0, 255,0,0, 255,0,0, 255,0,0, 255,0,0, 255,0,0, 255,0,0, 255,0,0
+	 DCB 0,255,0, 0,255,0, 0,255,0, 0,255,0, 0,255,0, 0,255,0, 0,255,0, 0,255,0, 0,255,0, 0,255,0, 0,255,0, 0,255,0, 0,255,0, 0,255,0, 0,255,0, 0,255,0
+	 DCB 0,0,255, 0,0,255, 0,0,255, 0,0,255, 0,0,255, 0,0,255, 0,0,255, 0,0,255, 0,0,255, 0,0,255, 0,0,255, 0,0,255, 0,0,255, 0,0,255, 0,0,255, 0,0,255
+	 DCB 255,255,0, 255,255,0, 255,255,0, 255,255,0, 255,255,0, 255,255,0, 255,255,0, 255,255,0, 255,255,0, 255,255,0, 255,255,0, 255,255,0, 255,255,0, 255,255,0, 255,255,0, 255,255,0
+	 DCB 255,0,255, 255,0,255, 255,0,255, 255,0,255, 255,0,255, 255,0,255, 255,0,255, 255,0,255, 255,0,255, 255,0,255, 255,0,255, 255,0,255, 255,0,255, 255,0,255, 255,0,255, 255,0,255
+	 DCB 0,255,255, 0,255,255, 0,255,255, 0,255,255, 0,255,255, 0,255,255, 0,255,255, 0,255,255, 0,255,255, 0,255,255, 0,255,255, 0,255,255, 0,255,255, 0,255,255, 0,255,255, 0,255,255
+	 DCB 255,255,255, 255,255,255, 255,255,255, 255,255,255, 255,255,255, 255,255,255, 255,255,255, 255,255,255, 255,255,255, 255,255,255, 255,255,255, 255,255,255, 255,255,255, 255,255,255, 255,255,255, 255,255,255
+	 DCB 5,5,5, 5,5,5, 5,5,5, 5,5,5, 5,5,5, 5,5,5, 5,5,5, 5,5,5, 5,5,5, 5,5,5, 5,5,5, 5,5,5, 5,5,5, 5,5,5, 5,5,5, 5,5,5
+	 
+	  
+
+
+;*******************************************************************************
+	END		
\ No newline at end of file
diff --git a/Objects/Etape_0_Réel.dep b/Objects/Etape_0_Réel.dep
deleted file mode 100644
index ac22227..0000000
--- a/Objects/Etape_0_Réel.dep
+++ /dev/null
@@ -1,19 +0,0 @@
-Dependencies for Project 'Etape_0', Target 'Réel': (DO NOT MODIFY !)
-F (.\Principale.asm)(0x5ADC5482)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1"

-I.\RTE\Device\STM32F107VC

-I.\RTE\_R_el

-IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

--pd "__UVISION_VERSION SETA 524" --pd "_RTE_ SETA 1" --pd "STM32F10X_CL SETA 1" --pd "STM32F10X_CL SETA 1"

--list .\listings\principale.lst --xref -o .\objects\principale.o --depend .\objects\principale.d)
-I (REG_UTILES.inc)(0x5AB8C188)
-F (.\FonctionEtape.asm)(0x5ABB4DF4)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1"

-I.\RTE\Device\STM32F107VC

-I.\RTE\_R_el

-IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

--pd "__UVISION_VERSION SETA 524" --pd "_RTE_ SETA 1" --pd "STM32F10X_CL SETA 1" --pd "STM32F10X_CL SETA 1"

--list .\listings\fonctionetape.lst --xref -o .\objects\fonctionetape.o --depend .\objects\fonctionetape.d)
-I (REG_UTILES.inc)(0x5AB8C188)
-F (.\Matos.lib)(0x5C7F9FAC)()
-F (RTE\Device\STM32F103RB\RTE_Device.h)(0x57D2B1E0)()
-F (RTE\Device\STM32F103RB\startup_stm32f10x_md.s)(0x58259ADC)()
-F (RTE\Device\STM32F103RB\system_stm32f10x.c)(0x58259ADC)()
-F (RTE\Device\STM32F107VC\RTE_Device.h)(0x57D2B1E0)()
-F (RTE\Device\STM32F107VC\startup_stm32f10x_cl.s)(0x58259ADC)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1"

-I.\RTE\Device\STM32F107VC

-I.\RTE\_R_el

-IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

--pd "__UVISION_VERSION SETA 524" --pd "_RTE_ SETA 1" --pd "STM32F10X_CL SETA 1" --pd "STM32F10X_CL SETA 1"

--list .\listings\startup_stm32f10x_cl.lst --xref -o .\objects\startup_stm32f10x_cl.o --depend .\objects\startup_stm32f10x_cl.d)
-F (RTE\Device\STM32F107VC\system_stm32f10x.c)(0x58259ADC)(--c99 -c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\pilotes\Include

-I.\RTE\Device\STM32F107VC

-I.\RTE\_R_el

-IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-D__UVISION_VERSION="524" -D_RTE_ -DSTM32F10X_CL -DSTM32F10X_CL

-o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h)(0x58258CCC)
-I (.\RTE\_R_el\RTE_Components.h)(0x5C7F99B8)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\core_cm3.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x588BD7A4)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_compiler.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_armcc.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h)(0x58258CCC)
diff --git a/Objects/Etape_0_Simulé.dep b/Objects/Etape_0_Simulé.dep
deleted file mode 100644
index fdcb17e..0000000
--- a/Objects/Etape_0_Simulé.dep
+++ /dev/null
@@ -1,120 +0,0 @@
-Dependencies for Project 'Etape_0', Target 'Simulé': (DO NOT MODIFY !)
-F (.\Principale.asm)(0x5ADC5482)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1"

-I.\RTE\Device\STM32F103RB

-I.\RTE\_Simul_

-IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\RTE_Driver

--pd "__UVISION_VERSION SETA 524" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "STM32F10X_MD SETA 1"

--list .\listings\principale.lst --xref -o .\objects\principale.o --depend .\objects\principale.d)
-I (REG_UTILES.inc)(0x5AB8C188)
-F (.\FonctionEtape.asm)(0x5ABB4DF4)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1"

-I.\RTE\Device\STM32F103RB

-I.\RTE\_Simul_

-IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\RTE_Driver

--pd "__UVISION_VERSION SETA 524" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "STM32F10X_MD SETA 1"

--list .\listings\fonctionetape.lst --xref -o .\objects\fonctionetape.o --depend .\objects\fonctionetape.d)
-I (REG_UTILES.inc)(0x5AB8C188)
-F (.\Matos.lib)(0x5AEC06A6)()
-F (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\src\misc.c)(0x52FA3F80)(--c99 -c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\pilotes\Include

-I.\RTE\Device\STM32F103RB

-I.\RTE\_Simul_

-IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\RTE_Driver

-D__UVISION_VERSION="524" -D_RTE_ -DSTM32F10X_MD -DSTM32F10X_MD

-o .\objects\misc.o --omf_browse .\objects\misc.crf --depend .\objects\misc.d)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\misc.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h)(0x58258CCC)
-I (.\RTE\_Simul_\RTE_Components.h)(0x5AB220C0)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\core_cm3.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x588BD7A4)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_compiler.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_armcc.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h)(0x58258CCC)
-I (.\RTE\Device\STM32F103RB\stm32f10x_conf.h)(0x52FA5040)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_spi.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_tim.h)(0x52FA3F80)
-F (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\src\stm32f10x_rcc.c)(0x52FA3F80)(--c99 -c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\pilotes\Include

-I.\RTE\Device\STM32F103RB

-I.\RTE\_Simul_

-IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\RTE_Driver

-D__UVISION_VERSION="524" -D_RTE_ -DSTM32F10X_MD -DSTM32F10X_MD

-o .\objects\stm32f10x_rcc.o --omf_browse .\objects\stm32f10x_rcc.crf --depend .\objects\stm32f10x_rcc.d)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h)(0x58258CCC)
-I (.\RTE\_Simul_\RTE_Components.h)(0x5AB220C0)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\core_cm3.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x588BD7A4)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_compiler.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_armcc.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h)(0x58258CCC)
-I (.\RTE\Device\STM32F103RB\stm32f10x_conf.h)(0x52FA5040)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_spi.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_tim.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\misc.h)(0x52FA3F80)
-F (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\src\stm32f10x_spi.c)(0x52FA3F80)(--c99 -c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\pilotes\Include

-I.\RTE\Device\STM32F103RB

-I.\RTE\_Simul_

-IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\RTE_Driver

-D__UVISION_VERSION="524" -D_RTE_ -DSTM32F10X_MD -DSTM32F10X_MD

-o .\objects\stm32f10x_spi.o --omf_browse .\objects\stm32f10x_spi.crf --depend .\objects\stm32f10x_spi.d)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_spi.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h)(0x58258CCC)
-I (.\RTE\_Simul_\RTE_Components.h)(0x5AB220C0)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\core_cm3.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x588BD7A4)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_compiler.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_armcc.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h)(0x58258CCC)
-I (.\RTE\Device\STM32F103RB\stm32f10x_conf.h)(0x52FA5040)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_tim.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\misc.h)(0x52FA3F80)
-F (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\src\stm32f10x_tim.c)(0x52FA3F80)(--c99 -c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\pilotes\Include

-I.\RTE\Device\STM32F103RB

-I.\RTE\_Simul_

-IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\RTE_Driver

-D__UVISION_VERSION="524" -D_RTE_ -DSTM32F10X_MD -DSTM32F10X_MD

-o .\objects\stm32f10x_tim.o --omf_browse .\objects\stm32f10x_tim.crf --depend .\objects\stm32f10x_tim.d)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_tim.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h)(0x58258CCC)
-I (.\RTE\_Simul_\RTE_Components.h)(0x5AB220C0)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\core_cm3.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x588BD7A4)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_compiler.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_armcc.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h)(0x58258CCC)
-I (.\RTE\Device\STM32F103RB\stm32f10x_conf.h)(0x52FA5040)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_spi.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\misc.h)(0x52FA3F80)
-F (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\RTE_Driver\DMA_STM32F10x.c)(0x56177D7E)(--c99 -c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\pilotes\Include

-I.\RTE\Device\STM32F103RB

-I.\RTE\_Simul_

-IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\RTE_Driver

-D__UVISION_VERSION="524" -D_RTE_ -DSTM32F10X_MD -DSTM32F10X_MD

-o .\objects\dma_stm32f10x.o --omf_browse .\objects\dma_stm32f10x.crf --depend .\objects\dma_stm32f10x.d)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\RTE_Driver\DMA_STM32F10x.h)(0x52B2C56E)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x588BD7A4)
-I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x588BD7A4)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\STM32F10x.h)(0x58258CCC)
-I (.\RTE\_Simul_\RTE_Components.h)(0x5AB220C0)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\core_cm3.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_compiler.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_armcc.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h)(0x58258CCC)
-I (.\RTE\Device\STM32F103RB\stm32f10x_conf.h)(0x52FA5040)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_spi.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_tim.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\misc.h)(0x52FA3F80)
-F (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\RTE_Driver\GPIO_STM32F10x.c)(0x571F4B6A)(--c99 -c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\pilotes\Include

-I.\RTE\Device\STM32F103RB

-I.\RTE\_Simul_

-IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\RTE_Driver

-D__UVISION_VERSION="524" -D_RTE_ -DSTM32F10X_MD -DSTM32F10X_MD

-o .\objects\gpio_stm32f10x.o --omf_browse .\objects\gpio_stm32f10x.crf --depend .\objects\gpio_stm32f10x.d)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\RTE_Driver\GPIO_STM32F10x.h)(0x56177D7E)
-I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x588BD7A4)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h)(0x58258CCC)
-I (.\RTE\_Simul_\RTE_Components.h)(0x5AB220C0)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\core_cm3.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x588BD7A4)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_compiler.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_armcc.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h)(0x58258CCC)
-I (.\RTE\Device\STM32F103RB\stm32f10x_conf.h)(0x52FA5040)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_spi.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_tim.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\misc.h)(0x52FA3F80)
-F (RTE\Device\STM32F103RB\RTE_Device.h)(0x57D2B1E0)()
-F (RTE\Device\STM32F103RB\startup_stm32f10x_md.s)(0x58259ADC)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1"

-I.\RTE\Device\STM32F103RB

-I.\RTE\_Simul_

-IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\RTE_Driver

--pd "__UVISION_VERSION SETA 524" --pd "_RTE_ SETA 1" --pd "STM32F10X_MD SETA 1" --pd "STM32F10X_MD SETA 1"

--list .\listings\startup_stm32f10x_md.lst --xref -o .\objects\startup_stm32f10x_md.o --depend .\objects\startup_stm32f10x_md.d)
-F (RTE\Device\STM32F103RB\stm32f10x_conf.h)(0x52FA5040)()
-F (RTE\Device\STM32F103RB\system_stm32f10x.c)(0x58259ADC)(--c99 -c --cpu Cortex-M3 -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\pilotes\Include

-I.\RTE\Device\STM32F103RB

-I.\RTE\_Simul_

-IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc

-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\RTE_Driver

-D__UVISION_VERSION="524" -D_RTE_ -DSTM32F10X_MD -DSTM32F10X_MD

-o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h)(0x58258CCC)
-I (.\RTE\_Simul_\RTE_Components.h)(0x5AB220C0)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\core_cm3.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x588BD7A4)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_compiler.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_armcc.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h)(0x58258CCC)
-I (.\RTE\Device\STM32F103RB\stm32f10x_conf.h)(0x52FA5040)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_spi.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_tim.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\misc.h)(0x52FA3F80)
-F (RTE\Device\STM32F107VC\RTE_Device.h)(0x57D2B1E0)()
-F (RTE\Device\STM32F107VC\startup_stm32f10x_cl.s)(0x58259ADC)()
-F (RTE\Device\STM32F107VC\stm32f10x_conf.h)(0x52FA5040)()
-F (RTE\Device\STM32F107VC\system_stm32f10x.c)(0x58259ADC)()
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h)(0x58258CCC)
-I (.\RTE\_R_el\RTE_Components.h)(0x5ABB4966)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\core_cm3.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x588BD7A4)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_compiler.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_armcc.h)(0x58989DEA)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h)(0x58258CCC)
-I (.\RTE\Device\STM32F107VC\stm32f10x_conf.h)(0x52FA5040)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_spi.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_tim.h)(0x52FA3F80)
-I (C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\misc.h)(0x52FA3F80)
diff --git a/Objects/ExtDll.iex b/Objects/ExtDll.iex
deleted file mode 100644
index 6c0896e..0000000
--- a/Objects/ExtDll.iex
+++ /dev/null
@@ -1,2 +0,0 @@
-[EXTDLL]
-Count=0
diff --git a/Objects/Reel_Etape0.axf b/Objects/Reel_Etape0.axf
deleted file mode 100644
index 8dc0510..0000000
Binary files a/Objects/Reel_Etape0.axf and /dev/null differ
diff --git a/Objects/Reel_Etape0.build_log.htm b/Objects/Reel_Etape0.build_log.htm
deleted file mode 100644
index 31ae382..0000000
--- a/Objects/Reel_Etape0.build_log.htm
+++ /dev/null
@@ -1,66 +0,0 @@
-<html>
-<body>
-<pre>
-<h1>µVision Build Log</h1>
-<h2>Tool Versions:</h2>
-IDE-Version: µVision V5.24.2.0
-Copyright (C) 2017 ARM Ltd and ARM Germany GmbH. All rights reserved.
-License Information: Vincent MAHOUT, INSA, LIC=----
- 
-Tool Versions:
-Toolchain:       MDK-Lite  Version: 5.24.1
-Toolchain Path:  C:\Keil_v5\ARM\ARMCC\Bin
-C Compiler:      Armcc.exe V5.06 update 5 (build 528)
-Assembler:       Armasm.exe V5.06 update 5 (build 528)
-Linker/Locator:  ArmLink.exe V5.06 update 5 (build 528)
-Library Manager: ArmAr.exe V5.06 update 5 (build 528)
-Hex Converter:   FromElf.exe V5.06 update 5 (build 528)
-CPU DLL:         SARMCM3.DLL V5.24.1
-Dialog DLL:      DCM.DLL V1.16.0.0
-Target DLL:      UL2CM3.DLL V1.160.3.0
-Dialog DLL:      TCM.DLL V1.32.0.0
- 
-<h2>Project:</h2>
-C:\Users\vmahout\Documents\Enseignement\Informatique_Materielle\Assembleur\TP 2019\Roue Magique TP Etape 0\Etape_0.uvprojx
-Project File Date:  03/06/2019
-
-<h2>Output:</h2>
-*** Using Compiler 'V5.06 update 5 (build 528)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
-Build target 'Réel'
-linking...
-Program Size: Code=4708 RO-data=368 RW-data=144 ZI-data=1024  
-".\Objects\Reel_Etape0.axf" - 0 Error(s), 0 Warning(s).
-
-<h2>Software Packages used:</h2>
-
-Package Vendor: ARM
-                http://www.keil.com/pack/ARM.CMSIS.5.0.1.pack
-                ARM.CMSIS.5.0.1
-                CMSIS (Cortex Microcontroller Software Interface Standard)
-   * Component: CORE Version: 5.0.1
-
-Package Vendor: Keil
-                http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack
-                Keil.STM32F1xx_DFP.2.2.0
-                STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
-   * Component: Startup Version: 1.0.0
-
-<h2>Collection of Component include folders:</h2>
-  .\RTE\Device\STM32F107VC
-  .\RTE\_R_el
-  C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include
-  C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include
-
-<h2>Collection of Component Files used:</h2>
-
-   * Component: Keil::Device:Startup:1.0.0
-      Source file:   Device\Source\ARM\STM32F1xx_OPT.s
-      Source file:   Device\Source\ARM\startup_stm32f10x_cl.s
-      Source file:   Device\Source\system_stm32f10x.c
-      Include file:  RTE_Driver\Config\RTE_Device.h
-
-   * Component: ARM::CMSIS:CORE:5.0.1
-Build Time Elapsed:  00:00:00
-</pre>
-</body>
-</html>
diff --git a/Objects/Reel_Etape0.htm b/Objects/Reel_Etape0.htm
deleted file mode 100644
index f3c6821..0000000
--- a/Objects/Reel_Etape0.htm
+++ /dev/null
@@ -1,685 +0,0 @@
-<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
-<html><head>
-<title>Static Call Graph - [.\Objects\Reel_Etape0.axf]</title></head>
-<body><HR>
-<H1>Static Call Graph for image .\Objects\Reel_Etape0.axf</H1><HR>
-<BR><P>#&#060CALLGRAPH&#062# ARM Linker, 5060528: Last Updated: Wed Mar 06 11:26:32 2019
-<BR><P>
-<H3>Maximum Stack Usage =        168 bytes + Unknown(Cycles, Untraceable Function Pointers)</H3><H3>
-Call chain for Maximum Stack Depth:</H3>
-main &rArr; Init_Cible &rArr; Init_Timer1 &rArr; __aeabi_dmul &rArr; _double_epilogue &rArr; _double_round
-<P>
-<H3>
-Mutually Recursive functions
-</H3> <LI><a href="#[1]">NMI_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[1]">NMI_Handler</a><BR>
- <LI><a href="#[2]">HardFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[2]">HardFault_Handler</a><BR>
- <LI><a href="#[3]">MemManage_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[3]">MemManage_Handler</a><BR>
- <LI><a href="#[4]">BusFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[4]">BusFault_Handler</a><BR>
- <LI><a href="#[5]">UsageFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[5]">UsageFault_Handler</a><BR>
- <LI><a href="#[6]">SVC_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[6]">SVC_Handler</a><BR>
- <LI><a href="#[7]">DebugMon_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[7]">DebugMon_Handler</a><BR>
- <LI><a href="#[8]">PendSV_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[8]">PendSV_Handler</a><BR>
- <LI><a href="#[1c]">ADC1_2_IRQHandler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[1c]">ADC1_2_IRQHandler</a><BR>
-</UL>
-<P>
-<H3>
-Function Pointers
-</H3><UL>
- <LI><a href="#[1c]">ADC1_2_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[4a]">Anim</a> from fonctiontimer.o(i.Anim) referenced from initialisation.o(i.Init_Cible)
- <LI><a href="#[4]">BusFault_Handler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[1e]">CAN1_RX0_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[1f]">CAN1_RX1_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[20]">CAN1_SCE_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[1d]">CAN1_TX_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[43]">CAN2_RX0_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[44]">CAN2_RX1_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[45]">CAN2_SCE_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[42]">CAN2_TX_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[15]">DMA1_Channel1_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[16]">DMA1_Channel2_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[17]">DMA1_Channel3_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[18]">DMA1_Channel4_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[19]">DMA1_Channel5_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[1a]">DMA1_Channel6_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[1b]">DMA1_Channel7_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[3b]">DMA2_Channel1_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[3c]">DMA2_Channel2_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[3d]">DMA2_Channel3_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[3e]">DMA2_Channel4_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[3f]">DMA2_Channel5_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[7]">DebugMon_Handler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[40]">ETH_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[41]">ETH_WKUP_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[10]">EXTI0_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[32]">EXTI15_10_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[11]">EXTI1_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[12]">EXTI2_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[13]">EXTI3_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[14]">EXTI4_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[21]">EXTI9_5_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[e]">FLASH_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[2]">HardFault_Handler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[2a]">I2C1_ER_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[29]">I2C1_EV_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[2c]">I2C2_ER_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[2b]">I2C2_EV_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[3]">MemManage_Handler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[1]">NMI_Handler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[46]">OTG_FS_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[34]">OTG_FS_WKUP_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[b]">PVD_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[8]">PendSV_Handler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[f]">RCC_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[33]">RTCAlarm_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[d]">RTC_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[0]">Reset_Handler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[2d]">SPI1_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[2e]">SPI2_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[36]">SPI3_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[6]">SVC_Handler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[9]">SysTick_Handler</a> from timer_systick_1.o(i.SysTick_Handler) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[48]">SystemInit</a> from system_stm32f10x.o(i.SystemInit) referenced from startup_stm32f10x_cl.o(.text)
- <LI><a href="#[c]">TAMPER_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[22]">TIM1_BRK_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[25]">TIM1_CC_IRQHandler</a> from fonctiontimer.o(i.TIM1_CC_IRQHandler) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[24]">TIM1_TRG_COM_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[23]">TIM1_UP_IRQHandler</a> from fonctiontimer.o(i.TIM1_UP_IRQHandler) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[26]">TIM2_IRQHandler</a> from fonctiontimer.o(i.TIM2_IRQHandler) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[27]">TIM3_IRQHandler</a> from fonctiontimer.o(i.TIM3_IRQHandler) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[28]">TIM4_IRQHandler</a> from fonctiontimer.o(i.TIM4_IRQHandler) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[35]">TIM5_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[39]">TIM6_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[3a]">TIM7_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[37]">UART4_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[38]">UART5_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[2f]">USART1_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[30]">USART2_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[31]">USART3_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[5]">UsageFault_Handler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[a]">WWDG_IRQHandler</a> from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
- <LI><a href="#[49]">__main</a> from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f10x_cl.o(.text)
- <LI><a href="#[47]">main</a> from principale.o(moncode) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
-</UL>
-<P>
-<H3>
-Global Symbols
-</H3>
-<P><STRONG><a name="[49]"></a>__main</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(.text)
-</UL>
-<P><STRONG><a name="[6e]"></a>_main_stk</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))
-
-<P><STRONG><a name="[4b]"></a>_main_scatterload</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
-<BR><BR>[Calls]<UL><LI><a href="#[4c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload
-</UL>
-
-<P><STRONG><a name="[57]"></a>__main_after_scatterload</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
-<BR><BR>[Called By]<UL><LI><a href="#[4c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload
-</UL>
-
-<P><STRONG><a name="[6f]"></a>_main_clock</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))
-
-<P><STRONG><a name="[70]"></a>_main_cpp_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))
-
-<P><STRONG><a name="[71]"></a>_main_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))
-
-<P><STRONG><a name="[72]"></a>__rt_final_cpp</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000D))
-
-<P><STRONG><a name="[73]"></a>__rt_final_exit</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$0000000F))
-
-<P><STRONG><a name="[0]"></a>Reset_Handler</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[1]"></a>NMI_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR><BR>[Calls]<UL><LI><a href="#[1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NMI_Handler
-</UL>
-<BR>[Called By]<UL><LI><a href="#[1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NMI_Handler
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[2]"></a>HardFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR><BR>[Calls]<UL><LI><a href="#[2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HardFault_Handler
-</UL>
-<BR>[Called By]<UL><LI><a href="#[2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HardFault_Handler
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[3]"></a>MemManage_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR><BR>[Calls]<UL><LI><a href="#[3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MemManage_Handler
-</UL>
-<BR>[Called By]<UL><LI><a href="#[3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MemManage_Handler
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[4]"></a>BusFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR><BR>[Calls]<UL><LI><a href="#[4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BusFault_Handler
-</UL>
-<BR>[Called By]<UL><LI><a href="#[4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BusFault_Handler
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[5]"></a>UsageFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR><BR>[Calls]<UL><LI><a href="#[5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UsageFault_Handler
-</UL>
-<BR>[Called By]<UL><LI><a href="#[5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UsageFault_Handler
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[6]"></a>SVC_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR><BR>[Calls]<UL><LI><a href="#[6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SVC_Handler
-</UL>
-<BR>[Called By]<UL><LI><a href="#[6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SVC_Handler
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[7]"></a>DebugMon_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR><BR>[Calls]<UL><LI><a href="#[7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DebugMon_Handler
-</UL>
-<BR>[Called By]<UL><LI><a href="#[7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DebugMon_Handler
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[8]"></a>PendSV_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR><BR>[Calls]<UL><LI><a href="#[8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;PendSV_Handler
-</UL>
-<BR>[Called By]<UL><LI><a href="#[8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;PendSV_Handler
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[1c]"></a>ADC1_2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR><BR>[Calls]<UL><LI><a href="#[1c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC1_2_IRQHandler
-</UL>
-<BR>[Called By]<UL><LI><a href="#[1c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC1_2_IRQHandler
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[1e]"></a>CAN1_RX0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[1f]"></a>CAN1_RX1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[20]"></a>CAN1_SCE_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[1d]"></a>CAN1_TX_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[43]"></a>CAN2_RX0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[44]"></a>CAN2_RX1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[45]"></a>CAN2_SCE_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[42]"></a>CAN2_TX_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[15]"></a>DMA1_Channel1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[16]"></a>DMA1_Channel2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[17]"></a>DMA1_Channel3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[18]"></a>DMA1_Channel4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[19]"></a>DMA1_Channel5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[1a]"></a>DMA1_Channel6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[1b]"></a>DMA1_Channel7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[3b]"></a>DMA2_Channel1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[3c]"></a>DMA2_Channel2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[3d]"></a>DMA2_Channel3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[3e]"></a>DMA2_Channel4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[3f]"></a>DMA2_Channel5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[40]"></a>ETH_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[41]"></a>ETH_WKUP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[10]"></a>EXTI0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[32]"></a>EXTI15_10_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[11]"></a>EXTI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[12]"></a>EXTI2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[13]"></a>EXTI3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[14]"></a>EXTI4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[21]"></a>EXTI9_5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[e]"></a>FLASH_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[2a]"></a>I2C1_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[29]"></a>I2C1_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[2c]"></a>I2C2_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[2b]"></a>I2C2_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[46]"></a>OTG_FS_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[34]"></a>OTG_FS_WKUP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[b]"></a>PVD_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[f]"></a>RCC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[33]"></a>RTCAlarm_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[d]"></a>RTC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[2d]"></a>SPI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[2e]"></a>SPI2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[36]"></a>SPI3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[c]"></a>TAMPER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[22]"></a>TIM1_BRK_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[24]"></a>TIM1_TRG_COM_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[35]"></a>TIM5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[39]"></a>TIM6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[3a]"></a>TIM7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[37]"></a>UART4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[38]"></a>UART5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[2f]"></a>USART1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[30]"></a>USART2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[31]"></a>USART3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[a]"></a>WWDG_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[68]"></a>__aeabi_fmul</STRONG> (Thumb, 100 bytes, Stack size 8 bytes, fmul.o(.text))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = __aeabi_fmul
-</UL>
-<BR>[Called By]<UL><LI><a href="#[62]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Systick_Period
-<LI><a href="#[5c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer2_PWM
-<LI><a href="#[5b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer1
-</UL>
-
-<P><STRONG><a name="[4d]"></a>__aeabi_fdiv</STRONG> (Thumb, 124 bytes, Stack size 8 bytes, fdiv.o(.text))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = __aeabi_fdiv
-</UL>
-<BR>[Calls]<UL><LI><a href="#[4e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_float_round
-</UL>
-<BR>[Called By]<UL><LI><a href="#[62]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Systick_Period
-<LI><a href="#[5c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer2_PWM
-</UL>
-
-<P><STRONG><a name="[4f]"></a>__aeabi_dmul</STRONG> (Thumb, 228 bytes, Stack size 48 bytes, dmul.o(.text))
-<BR><BR>[Stack]<UL><LI>Max Depth = 88<LI>Call Chain = __aeabi_dmul &rArr; _double_epilogue &rArr; _double_round
-</UL>
-<BR>[Calls]<UL><LI><a href="#[50]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_epilogue
-</UL>
-<BR>[Called By]<UL><LI><a href="#[62]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Systick_Period
-<LI><a href="#[5b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer1
-</UL>
-
-<P><STRONG><a name="[51]"></a>__aeabi_ddiv</STRONG> (Thumb, 222 bytes, Stack size 32 bytes, ddiv.o(.text))
-<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = __aeabi_ddiv &rArr; _double_round
-</UL>
-<BR>[Calls]<UL><LI><a href="#[52]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_round
-</UL>
-<BR>[Called By]<UL><LI><a href="#[62]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Systick_Period
-<LI><a href="#[5c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer2_PWM
-<LI><a href="#[5b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer1
-</UL>
-
-<P><STRONG><a name="[53]"></a>__aeabi_ui2f</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, ffltui.o(.text))
-<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = __aeabi_ui2f &rArr; _float_epilogue
-</UL>
-<BR>[Calls]<UL><LI><a href="#[54]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_float_epilogue
-</UL>
-<BR>[Called By]<UL><LI><a href="#[62]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Systick_Period
-<LI><a href="#[5c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer2_PWM
-<LI><a href="#[5b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer1
-</UL>
-
-<P><STRONG><a name="[6b]"></a>__aeabi_f2uiz</STRONG> (Thumb, 40 bytes, Stack size 0 bytes, ffixui.o(.text))
-<BR><BR>[Called By]<UL><LI><a href="#[62]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Systick_Period
-<LI><a href="#[5c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer2_PWM
-<LI><a href="#[5b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer1
-</UL>
-
-<P><STRONG><a name="[66]"></a>__aeabi_f2d</STRONG> (Thumb, 38 bytes, Stack size 0 bytes, f2d.o(.text))
-<BR><BR>[Called By]<UL><LI><a href="#[62]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Systick_Period
-<LI><a href="#[5c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer2_PWM
-<LI><a href="#[5b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer1
-</UL>
-
-<P><STRONG><a name="[74]"></a>__aeabi_cdcmpeq</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, cdcmple.o(.text), UNUSED)
-
-<P><STRONG><a name="[69]"></a>__aeabi_cdcmple</STRONG> (Thumb, 48 bytes, Stack size 0 bytes, cdcmple.o(.text))
-<BR><BR>[Called By]<UL><LI><a href="#[5b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer1
-</UL>
-
-<P><STRONG><a name="[6a]"></a>__aeabi_cdrcmple</STRONG> (Thumb, 48 bytes, Stack size 0 bytes, cdrcmple.o(.text))
-<BR><BR>[Called By]<UL><LI><a href="#[62]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Systick_Period
-<LI><a href="#[5b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer1
-</UL>
-
-<P><STRONG><a name="[67]"></a>__aeabi_d2f</STRONG> (Thumb, 56 bytes, Stack size 8 bytes, d2f.o(.text))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = __aeabi_d2f
-</UL>
-<BR>[Called By]<UL><LI><a href="#[62]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Systick_Period
-<LI><a href="#[5c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer2_PWM
-<LI><a href="#[5b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer1
-</UL>
-
-<P><STRONG><a name="[75]"></a>__I$use$fp</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, iusefp.o(.text), UNUSED)
-
-<P><STRONG><a name="[4e]"></a>_float_round</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, fepilogue.o(.text))
-<BR><BR>[Called By]<UL><LI><a href="#[4d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_fdiv
-</UL>
-
-<P><STRONG><a name="[54]"></a>_float_epilogue</STRONG> (Thumb, 92 bytes, Stack size 4 bytes, fepilogue.o(.text))
-<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = _float_epilogue
-</UL>
-<BR>[Called By]<UL><LI><a href="#[53]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ui2f
-</UL>
-
-<P><STRONG><a name="[52]"></a>_double_round</STRONG> (Thumb, 30 bytes, Stack size 8 bytes, depilogue.o(.text))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = _double_round
-</UL>
-<BR>[Called By]<UL><LI><a href="#[50]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_epilogue
-<LI><a href="#[51]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ddiv
-</UL>
-
-<P><STRONG><a name="[50]"></a>_double_epilogue</STRONG> (Thumb, 156 bytes, Stack size 32 bytes, depilogue.o(.text))
-<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = _double_epilogue &rArr; _double_round
-</UL>
-<BR>[Calls]<UL><LI><a href="#[56]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_llsr
-<LI><a href="#[55]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_llsl
-<LI><a href="#[52]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_round
-</UL>
-<BR>[Called By]<UL><LI><a href="#[4f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_dmul
-</UL>
-
-<P><STRONG><a name="[4c]"></a>__scatterload</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
-<BR><BR>[Calls]<UL><LI><a href="#[57]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__main_after_scatterload
-</UL>
-<BR>[Called By]<UL><LI><a href="#[4b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_main_scatterload
-</UL>
-
-<P><STRONG><a name="[76]"></a>__scatterload_rt2</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)
-
-<P><STRONG><a name="[55]"></a>__aeabi_llsl</STRONG> (Thumb, 30 bytes, Stack size 0 bytes, llshl.o(.text))
-<BR><BR>[Called By]<UL><LI><a href="#[50]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_epilogue
-</UL>
-
-<P><STRONG><a name="[77]"></a>_ll_shift_l</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, llshl.o(.text), UNUSED)
-
-<P><STRONG><a name="[56]"></a>__aeabi_llsr</STRONG> (Thumb, 32 bytes, Stack size 0 bytes, llushr.o(.text))
-<BR><BR>[Called By]<UL><LI><a href="#[50]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_epilogue
-</UL>
-
-<P><STRONG><a name="[78]"></a>_ll_ushift_r</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, llushr.o(.text), UNUSED)
-
-<P><STRONG><a name="[4a]"></a>Anim</STRONG> (Thumb, 32 bytes, Stack size 0 bytes, fonctiontimer.o(i.Anim))
-<BR>[Address Reference Count : 1]<UL><LI> initialisation.o(i.Init_Cible)
-</UL>
-<P><STRONG><a name="[65]"></a>GPIO_Configure</STRONG> (Thumb, 314 bytes, Stack size 24 bytes, pilote_io_1.o(i.GPIO_Configure))
-<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = GPIO_Configure
-</UL>
-<BR>[Called By]<UL><LI><a href="#[59]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Port
-</UL>
-
-<P><STRONG><a name="[58]"></a>Init_Cible</STRONG> (Thumb, 218 bytes, Stack size 16 bytes, initialisation.o(i.Init_Cible))
-<BR><BR>[Stack]<UL><LI>Max Depth = 168<LI>Call Chain = Init_Cible &rArr; Init_Timer1 &rArr; __aeabi_dmul &rArr; _double_epilogue &rArr; _double_round
-</UL>
-<BR>[Calls]<UL><LI><a href="#[63]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Systick_Prio_IT
-<LI><a href="#[62]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Systick_Period
-<LI><a href="#[60]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Port_IO_Set
-<LI><a href="#[61]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Port_IO_Reset
-<LI><a href="#[5f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Envoie192Boucle
-<LI><a href="#[5e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer4
-<LI><a href="#[5d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer3_Slave
-<LI><a href="#[5c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer2_PWM
-<LI><a href="#[5b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer1
-<LI><a href="#[59]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Port
-<LI><a href="#[5a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Dot
-</UL>
-<BR>[Called By]<UL><LI><a href="#[47]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
-</UL>
-
-<P><STRONG><a name="[5a]"></a>Init_Dot</STRONG> (Thumb, 112 bytes, Stack size 16 bytes, initialisation.o(i.Init_Dot))
-<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = Init_Dot
-</UL>
-<BR>[Calls]<UL><LI><a href="#[60]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Port_IO_Set
-<LI><a href="#[61]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Port_IO_Reset
-<LI><a href="#[64]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Envoie96Dot
-</UL>
-<BR>[Called By]<UL><LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-</UL>
-
-<P><STRONG><a name="[59]"></a>Init_Port</STRONG> (Thumb, 134 bytes, Stack size 8 bytes, initialisation.o(i.Init_Port))
-<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = Init_Port &rArr; GPIO_Configure
-</UL>
-<BR>[Calls]<UL><LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_Configure
-</UL>
-<BR>[Called By]<UL><LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-</UL>
-
-<P><STRONG><a name="[5b]"></a>Init_Timer1</STRONG> (Thumb, 336 bytes, Stack size 64 bytes, initialisation.o(i.Init_Timer1))
-<BR><BR>[Stack]<UL><LI>Max Depth = 152<LI>Call Chain = Init_Timer1 &rArr; __aeabi_dmul &rArr; _double_epilogue &rArr; _double_round
-</UL>
-<BR>[Calls]<UL><LI><a href="#[53]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ui2f
-<LI><a href="#[68]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_fmul
-<LI><a href="#[6b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_f2uiz
-<LI><a href="#[66]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_f2d
-<LI><a href="#[4f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_dmul
-<LI><a href="#[51]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ddiv
-<LI><a href="#[67]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_d2f
-<LI><a href="#[6a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_cdrcmple
-<LI><a href="#[69]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_cdcmple
-</UL>
-<BR>[Called By]<UL><LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-</UL>
-
-<P><STRONG><a name="[5c]"></a>Init_Timer2_PWM</STRONG> (Thumb, 262 bytes, Stack size 56 bytes, initialisation.o(i.Init_Timer2_PWM))
-<BR><BR>[Stack]<UL><LI>Max Depth = 96<LI>Call Chain = Init_Timer2_PWM &rArr; __aeabi_ddiv &rArr; _double_round
-</UL>
-<BR>[Calls]<UL><LI><a href="#[53]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ui2f
-<LI><a href="#[68]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_fmul
-<LI><a href="#[4d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_fdiv
-<LI><a href="#[6b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_f2uiz
-<LI><a href="#[66]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_f2d
-<LI><a href="#[51]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ddiv
-<LI><a href="#[67]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_d2f
-</UL>
-<BR>[Called By]<UL><LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-</UL>
-
-<P><STRONG><a name="[5d]"></a>Init_Timer3_Slave</STRONG> (Thumb, 94 bytes, Stack size 0 bytes, initialisation.o(i.Init_Timer3_Slave))
-<BR><BR>[Called By]<UL><LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-</UL>
-
-<P><STRONG><a name="[5e]"></a>Init_Timer4</STRONG> (Thumb, 100 bytes, Stack size 0 bytes, initialisation.o(i.Init_Timer4))
-<BR><BR>[Called By]<UL><LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-</UL>
-
-<P><STRONG><a name="[61]"></a>Port_IO_Reset</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, pilote_io_1.o(i.Port_IO_Reset))
-<BR><BR>[Called By]<UL><LI><a href="#[27]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIM3_IRQHandler
-<LI><a href="#[5a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Dot
-<LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-</UL>
-
-<P><STRONG><a name="[60]"></a>Port_IO_Set</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, pilote_io_1.o(i.Port_IO_Set))
-<BR><BR>[Called By]<UL><LI><a href="#[27]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIM3_IRQHandler
-<LI><a href="#[5a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Dot
-<LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-</UL>
-
-<P><STRONG><a name="[9]"></a>SysTick_Handler</STRONG> (Thumb, 10 bytes, Stack size 8 bytes, timer_systick_1.o(i.SysTick_Handler))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = SysTick_Handler
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[48]"></a>SystemInit</STRONG> (Thumb, 92 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SystemInit))
-<BR><BR>[Stack]<UL><LI>Max Depth = 28<LI>Call Chain = SystemInit &rArr; SetSysClock &rArr; SetSysClockTo72
-</UL>
-<BR>[Calls]<UL><LI><a href="#[6c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SetSysClock
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(.text)
-</UL>
-<P><STRONG><a name="[62]"></a>Systick_Period</STRONG> (Thumb, 256 bytes, Stack size 48 bytes, timer_systick_1.o(i.Systick_Period))
-<BR><BR>[Stack]<UL><LI>Max Depth = 136<LI>Call Chain = Systick_Period &rArr; __aeabi_dmul &rArr; _double_epilogue &rArr; _double_round
-</UL>
-<BR>[Calls]<UL><LI><a href="#[53]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ui2f
-<LI><a href="#[68]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_fmul
-<LI><a href="#[4d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_fdiv
-<LI><a href="#[6b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_f2uiz
-<LI><a href="#[66]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_f2d
-<LI><a href="#[4f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_dmul
-<LI><a href="#[51]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ddiv
-<LI><a href="#[67]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_d2f
-<LI><a href="#[6a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_cdrcmple
-</UL>
-<BR>[Called By]<UL><LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-</UL>
-
-<P><STRONG><a name="[63]"></a>Systick_Prio_IT</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, timer_systick_1.o(i.Systick_Prio_IT))
-<BR><BR>[Called By]<UL><LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-</UL>
-
-<P><STRONG><a name="[25]"></a>TIM1_CC_IRQHandler</STRONG> (Thumb, 158 bytes, Stack size 0 bytes, fonctiontimer.o(i.TIM1_CC_IRQHandler))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[23]"></a>TIM1_UP_IRQHandler</STRONG> (Thumb, 134 bytes, Stack size 8 bytes, fonctiontimer.o(i.TIM1_UP_IRQHandler))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = TIM1_UP_IRQHandler
-</UL>
-<BR>[Calls]<UL><LI><a href="#[5f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Envoie192Boucle
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[26]"></a>TIM2_IRQHandler</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, fonctiontimer.o(i.TIM2_IRQHandler))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[27]"></a>TIM3_IRQHandler</STRONG> (Thumb, 68 bytes, Stack size 8 bytes, fonctiontimer.o(i.TIM3_IRQHandler))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = TIM3_IRQHandler
-</UL>
-<BR>[Calls]<UL><LI><a href="#[60]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Port_IO_Set
-<LI><a href="#[61]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Port_IO_Reset
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[28]"></a>TIM4_IRQHandler</STRONG> (Thumb, 84 bytes, Stack size 8 bytes, fonctiontimer.o(i.TIM4_IRQHandler))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = TIM4_IRQHandler
-</UL>
-<BR>[Calls]<UL><LI><a href="#[5f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Envoie192Boucle
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_cl.o(RESET)
-</UL>
-<P><STRONG><a name="[79]"></a>__scatterload_copy</STRONG> (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)
-
-<P><STRONG><a name="[7a]"></a>__scatterload_null</STRONG> (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)
-
-<P><STRONG><a name="[7b]"></a>__scatterload_zeroinit</STRONG> (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)
-
-<P><STRONG><a name="[47]"></a>main</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, principale.o(moncode))
-<BR><BR>[Stack]<UL><LI>Max Depth = 168<LI>Call Chain = main &rArr; Init_Cible &rArr; Init_Timer1 &rArr; __aeabi_dmul &rArr; _double_epilogue &rArr; _double_round
-</UL>
-<BR>[Calls]<UL><LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> entry9a.o(.ARM.Collect$$$$0000000B)
-</UL>
-<P><STRONG><a name="[5f]"></a>Envoie192Boucle</STRONG> (Thumb, 116 bytes, Stack size 0 bytes, foncasm.o(moncode))
-<BR><BR>[Called By]<UL><LI><a href="#[28]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIM4_IRQHandler
-<LI><a href="#[23]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIM1_UP_IRQHandler
-<LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-</UL>
-
-<P><STRONG><a name="[64]"></a>Envoie96Dot</STRONG> (Thumb, 78 bytes, Stack size 0 bytes, foncasm.o(moncode))
-<BR><BR>[Called By]<UL><LI><a href="#[5a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Dot
-</UL>
-<P>
-<H3>
-Local Symbols
-</H3>
-<P><STRONG><a name="[6c]"></a>SetSysClock</STRONG> (Thumb, 8 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SetSysClock))
-<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = SetSysClock &rArr; SetSysClockTo72
-</UL>
-<BR>[Calls]<UL><LI><a href="#[6d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SetSysClockTo72
-</UL>
-<BR>[Called By]<UL><LI><a href="#[48]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemInit
-</UL>
-
-<P><STRONG><a name="[6d]"></a>SetSysClockTo72</STRONG> (Thumb, 264 bytes, Stack size 12 bytes, system_stm32f10x.o(i.SetSysClockTo72))
-<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = SetSysClockTo72
-</UL>
-<BR>[Called By]<UL><LI><a href="#[6c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SetSysClock
-</UL>
-<P>
-<H3>
-Undefined Global Symbols
-</H3><HR></body></html>
diff --git a/Objects/Reel_Etape0.lnp b/Objects/Reel_Etape0.lnp
deleted file mode 100644
index b60d6f7..0000000
--- a/Objects/Reel_Etape0.lnp
+++ /dev/null
@@ -1,10 +0,0 @@
---cpu Cortex-M3
-".\objects\principale.o"
-".\objects\fonctionetape.o"
-".\Matos.lib"
-".\objects\startup_stm32f10x_cl.o"
-".\objects\system_stm32f10x.o"
---library_type=microlib --strict --scatter ".\Objects\Reel_Etape0.sct"
---summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
---info sizes --info totals --info unused --info veneers
---list ".\Listings\Reel_Etape0.map" -o .\Objects\Reel_Etape0.axf
\ No newline at end of file
diff --git a/Objects/Reel_Etape0.sct b/Objects/Reel_Etape0.sct
deleted file mode 100644
index a8c9a15..0000000
--- a/Objects/Reel_Etape0.sct
+++ /dev/null
@@ -1,15 +0,0 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x08000000 0x00040000  {    ; load region size_region
-  ER_IROM1 0x08000000 0x00040000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  RW_IRAM1 0x20000000 0x00010000  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-}
-
diff --git a/Objects/Simu_Etape0.axf b/Objects/Simu_Etape0.axf
deleted file mode 100644
index a1037fc..0000000
Binary files a/Objects/Simu_Etape0.axf and /dev/null differ
diff --git a/Objects/Simu_Etape0.build_log.htm b/Objects/Simu_Etape0.build_log.htm
deleted file mode 100644
index d3fefe6..0000000
--- a/Objects/Simu_Etape0.build_log.htm
+++ /dev/null
@@ -1,110 +0,0 @@
-<html>
-<body>
-<pre>
-<h1>µVision Build Log</h1>
-<h2>Tool Versions:</h2>
-IDE-Version: µVision V5.24.2.0
-Copyright (C) 2017 ARM Ltd and ARM Germany GmbH. All rights reserved.
-License Information: Vincent MAHOUT, INSA, LIC=----
- 
-Tool Versions:
-Toolchain:       MDK-Lite  Version: 5.24.1
-Toolchain Path:  C:\Keil_v5\ARM\ARMCC\Bin
-C Compiler:      Armcc.exe V5.06 update 5 (build 528)
-Assembler:       Armasm.exe V5.06 update 5 (build 528)
-Linker/Locator:  ArmLink.exe V5.06 update 5 (build 528)
-Library Manager: ArmAr.exe V5.06 update 5 (build 528)
-Hex Converter:   FromElf.exe V5.06 update 5 (build 528)
-CPU DLL:         SARMCM3.DLL V5.24.1
-Dialog DLL:      DARMSTM.DLL V1.68.0.0
-Target DLL:      UL2CM3.DLL V1.160.3.0
-Dialog DLL:      TCM.DLL V1.32.0.0
- 
-<h2>Project:</h2>
-C:\Users\vmahout\Documents\Enseignement\Informatique_Materielle\Assembleur\TP 2019\Roue Magique TP Etape 0\Etape_0.uvprojx
-Project File Date:  03/28/2018
-
-<h2>Output:</h2>
-*** Using Compiler 'V5.06 update 5 (build 528)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
-Build target 'Simulé'
-assembling FonctionEtape.asm...
-assembling Principale.asm...
-compiling misc.c...
-compiling stm32f10x_rcc.c...
-compiling stm32f10x_spi.c...
-compiling stm32f10x_tim.c...
-compiling DMA_STM32F10x.c...
-compiling GPIO_STM32F10x.c...
-compiling system_stm32f10x.c...
-linking...
-Program Size: Code=5164 RO-data=268 RW-data=144 ZI-data=1048  
-".\Objects\Simu_Etape0.axf" - 0 Error(s), 0 Warning(s).
-
-<h2>Software Packages used:</h2>
-
-Package Vendor: ARM
-                http://www.keil.com/pack/ARM.CMSIS.5.0.1.pack
-                ARM.CMSIS.5.0.1
-                CMSIS (Cortex Microcontroller Software Interface Standard)
-   * Component: CORE Version: 5.0.1
-
-Package Vendor: Keil
-                http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack
-                Keil.STM32F1xx_DFP.2.2.0
-                STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
-   * Component: TIM Version: 3.5.0
-   * Component: SPI Version: 3.5.0
-   * Component: RCC Version: 3.5.0
-   * Component: Framework Version: 3.5.1
-   * Component: Startup Version: 1.0.0
-   * Component: GPIO Version: 1.3
-   * Component: DMA Version: 1.2
-
-<h2>Collection of Component include folders:</h2>
-  .\RTE\Device\STM32F103RB
-  .\RTE\_Simul_
-  C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include
-  C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include
-  C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc
-  C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\RTE_Driver
-
-<h2>Collection of Component Files used:</h2>
-
-   * Component: Keil::Device:StdPeriph Drivers:TIM:3.5.0
-      Include file:  Device\StdPeriph_Driver\inc\stm32f10x_tim.h
-      Source file:   Device\StdPeriph_Driver\src\stm32f10x_tim.c
-
-   * Component: Keil::Device:StdPeriph Drivers:SPI:3.5.0
-      Include file:  Device\StdPeriph_Driver\inc\stm32f10x_spi.h
-      Source file:   Device\StdPeriph_Driver\src\stm32f10x_spi.c
-
-   * Component: Keil::Device:StdPeriph Drivers:RCC:3.5.0
-      Source file:   Device\StdPeriph_Driver\src\stm32f10x_rcc.c
-      Include file:  Device\StdPeriph_Driver\inc\stm32f10x_rcc.h
-
-   * Component: Keil::Device:StdPeriph Drivers:Framework:3.5.1
-      Include file:  Device\StdPeriph_Driver\inc\misc.h
-      Source file:   Device\StdPeriph_Driver\templates\stm32f10x_it.c
-      Source file:   Device\StdPeriph_Driver\templates\stm32f10x_conf.h
-      Include file:  Device\StdPeriph_Driver\templates\stm32f10x_it.h
-      Source file:   Device\StdPeriph_Driver\src\misc.c
-
-   * Component: Keil::Device:Startup:1.0.0
-      Source file:   Device\Source\ARM\STM32F1xx_OPT.s
-      Include file:  RTE_Driver\Config\RTE_Device.h
-      Source file:   Device\Source\system_stm32f10x.c
-      Source file:   Device\Source\ARM\startup_stm32f10x_md.s
-
-   * Component: Keil::Device:GPIO:1.3
-      Source file:   RTE_Driver\GPIO_STM32F10x.c
-      Include file:  RTE_Driver\GPIO_STM32F10x.h
-
-   * Component: Keil::Device:DMA:1.2
-      Source file:   RTE_Driver\DMA_STM32F10x.c
-      Include file:  RTE_Driver\DMA_STM32F10x.h
-
-   * Component: ARM::CMSIS:CORE:5.0.1
-Build Time Elapsed:  00:00:03
-</pre>
-</body>
-</html>
diff --git a/Objects/Simu_Etape0.htm b/Objects/Simu_Etape0.htm
deleted file mode 100644
index 0f0f562..0000000
--- a/Objects/Simu_Etape0.htm
+++ /dev/null
@@ -1,705 +0,0 @@
-<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
-<html><head>
-<title>Static Call Graph - [.\Objects\Simu_Etape0.axf]</title></head>
-<body><HR>
-<H1>Static Call Graph for image .\Objects\Simu_Etape0.axf</H1><HR>
-<BR><P>#&#060CALLGRAPH&#062# ARM Linker, 5060528: Last Updated: Wed Mar 06 10:41:45 2019
-<BR><P>
-<H3>Maximum Stack Usage =        168 bytes + Unknown(Cycles, Untraceable Function Pointers)</H3><H3>
-Call chain for Maximum Stack Depth:</H3>
-main &rArr; Init_Cible &rArr; Init_Timer1 &rArr; __aeabi_dmul &rArr; _double_epilogue &rArr; _double_round
-<P>
-<H3>
-Mutually Recursive functions
-</H3> <LI><a href="#[1]">NMI_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[1]">NMI_Handler</a><BR>
- <LI><a href="#[2]">HardFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[2]">HardFault_Handler</a><BR>
- <LI><a href="#[3]">MemManage_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[3]">MemManage_Handler</a><BR>
- <LI><a href="#[4]">BusFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[4]">BusFault_Handler</a><BR>
- <LI><a href="#[5]">UsageFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[5]">UsageFault_Handler</a><BR>
- <LI><a href="#[6]">SVC_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[6]">SVC_Handler</a><BR>
- <LI><a href="#[7]">DebugMon_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[7]">DebugMon_Handler</a><BR>
- <LI><a href="#[8]">PendSV_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[8]">PendSV_Handler</a><BR>
- <LI><a href="#[1c]">ADC1_2_IRQHandler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[1c]">ADC1_2_IRQHandler</a><BR>
-</UL>
-<P>
-<H3>
-Function Pointers
-</H3><UL>
- <LI><a href="#[1c]">ADC1_2_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[38]">Anim</a> from fonctiontimer.o(i.Anim) referenced from initialisation.o(i.Init_Cible)
- <LI><a href="#[4]">BusFault_Handler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[1f]">CAN1_RX1_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[20]">CAN1_SCE_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[15]">DMA1_Channel1_IRQHandler</a> from dma_stm32f10x.o(i.DMA1_Channel1_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[16]">DMA1_Channel2_IRQHandler</a> from dma_stm32f10x.o(i.DMA1_Channel2_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[17]">DMA1_Channel3_IRQHandler</a> from dma_stm32f10x.o(i.DMA1_Channel3_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[18]">DMA1_Channel4_IRQHandler</a> from dma_stm32f10x.o(i.DMA1_Channel4_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[19]">DMA1_Channel5_IRQHandler</a> from dma_stm32f10x.o(i.DMA1_Channel5_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[1a]">DMA1_Channel6_IRQHandler</a> from dma_stm32f10x.o(i.DMA1_Channel6_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[1b]">DMA1_Channel7_IRQHandler</a> from dma_stm32f10x.o(i.DMA1_Channel7_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[7]">DebugMon_Handler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[10]">EXTI0_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[32]">EXTI15_10_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[11]">EXTI1_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[12]">EXTI2_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[13]">EXTI3_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[14]">EXTI4_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[21]">EXTI9_5_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[e]">FLASH_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[2]">HardFault_Handler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[2a]">I2C1_ER_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[29]">I2C1_EV_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[2c]">I2C2_ER_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[2b]">I2C2_EV_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[3]">MemManage_Handler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[1]">NMI_Handler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[b]">PVD_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[8]">PendSV_Handler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[f]">RCC_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[33]">RTCAlarm_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[d]">RTC_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[0]">Reset_Handler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[2d]">SPI1_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[2e]">SPI2_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[6]">SVC_Handler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[9]">SysTick_Handler</a> from timer_systick_1.o(i.SysTick_Handler) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[36]">SystemInit</a> from system_stm32f10x.o(i.SystemInit) referenced from startup_stm32f10x_md.o(.text)
- <LI><a href="#[c]">TAMPER_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[22]">TIM1_BRK_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[25]">TIM1_CC_IRQHandler</a> from fonctiontimer.o(i.TIM1_CC_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[24]">TIM1_TRG_COM_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[23]">TIM1_UP_IRQHandler</a> from fonctiontimer.o(i.TIM1_UP_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[26]">TIM2_IRQHandler</a> from fonctiontimer.o(i.TIM2_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[27]">TIM3_IRQHandler</a> from fonctiontimer.o(i.TIM3_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[28]">TIM4_IRQHandler</a> from fonctiontimer.o(i.TIM4_IRQHandler) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[2f]">USART1_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[30]">USART2_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[31]">USART3_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[34]">USBWakeUp_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[1d]">USB_HP_CAN1_TX_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[1e]">USB_LP_CAN1_RX0_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[5]">UsageFault_Handler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[a]">WWDG_IRQHandler</a> from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
- <LI><a href="#[37]">__main</a> from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f10x_md.o(.text)
- <LI><a href="#[35]">main</a> from principale.o(moncode) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
-</UL>
-<P>
-<H3>
-Global Symbols
-</H3>
-<P><STRONG><a name="[37]"></a>__main</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(.text)
-</UL>
-<P><STRONG><a name="[69]"></a>_main_stk</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))
-
-<P><STRONG><a name="[39]"></a>_main_scatterload</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
-<BR><BR>[Calls]<UL><LI><a href="#[3a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload
-</UL>
-
-<P><STRONG><a name="[45]"></a>__main_after_scatterload</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
-<BR><BR>[Called By]<UL><LI><a href="#[3a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload
-</UL>
-
-<P><STRONG><a name="[6a]"></a>_main_clock</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))
-
-<P><STRONG><a name="[6b]"></a>_main_cpp_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))
-
-<P><STRONG><a name="[6c]"></a>_main_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))
-
-<P><STRONG><a name="[6d]"></a>__rt_final_cpp</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000D))
-
-<P><STRONG><a name="[6e]"></a>__rt_final_exit</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$0000000F))
-
-<P><STRONG><a name="[0]"></a>Reset_Handler</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[1]"></a>NMI_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR><BR>[Calls]<UL><LI><a href="#[1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NMI_Handler
-</UL>
-<BR>[Called By]<UL><LI><a href="#[1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NMI_Handler
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[2]"></a>HardFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR><BR>[Calls]<UL><LI><a href="#[2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HardFault_Handler
-</UL>
-<BR>[Called By]<UL><LI><a href="#[2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HardFault_Handler
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[3]"></a>MemManage_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR><BR>[Calls]<UL><LI><a href="#[3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MemManage_Handler
-</UL>
-<BR>[Called By]<UL><LI><a href="#[3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MemManage_Handler
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[4]"></a>BusFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR><BR>[Calls]<UL><LI><a href="#[4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BusFault_Handler
-</UL>
-<BR>[Called By]<UL><LI><a href="#[4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BusFault_Handler
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[5]"></a>UsageFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR><BR>[Calls]<UL><LI><a href="#[5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UsageFault_Handler
-</UL>
-<BR>[Called By]<UL><LI><a href="#[5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UsageFault_Handler
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[6]"></a>SVC_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR><BR>[Calls]<UL><LI><a href="#[6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SVC_Handler
-</UL>
-<BR>[Called By]<UL><LI><a href="#[6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SVC_Handler
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[7]"></a>DebugMon_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR><BR>[Calls]<UL><LI><a href="#[7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DebugMon_Handler
-</UL>
-<BR>[Called By]<UL><LI><a href="#[7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DebugMon_Handler
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[8]"></a>PendSV_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR><BR>[Calls]<UL><LI><a href="#[8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;PendSV_Handler
-</UL>
-<BR>[Called By]<UL><LI><a href="#[8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;PendSV_Handler
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[1c]"></a>ADC1_2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR><BR>[Calls]<UL><LI><a href="#[1c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC1_2_IRQHandler
-</UL>
-<BR>[Called By]<UL><LI><a href="#[1c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC1_2_IRQHandler
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[1f]"></a>CAN1_RX1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[20]"></a>CAN1_SCE_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[10]"></a>EXTI0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[32]"></a>EXTI15_10_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[11]"></a>EXTI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[12]"></a>EXTI2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[13]"></a>EXTI3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[14]"></a>EXTI4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[21]"></a>EXTI9_5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[e]"></a>FLASH_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[2a]"></a>I2C1_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[29]"></a>I2C1_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[2c]"></a>I2C2_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[2b]"></a>I2C2_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[b]"></a>PVD_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[f]"></a>RCC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[33]"></a>RTCAlarm_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[d]"></a>RTC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[2d]"></a>SPI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[2e]"></a>SPI2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[c]"></a>TAMPER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[22]"></a>TIM1_BRK_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[24]"></a>TIM1_TRG_COM_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[2f]"></a>USART1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[30]"></a>USART2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[31]"></a>USART3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[34]"></a>USBWakeUp_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[1d]"></a>USB_HP_CAN1_TX_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[1e]"></a>USB_LP_CAN1_RX0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[a]"></a>WWDG_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[60]"></a>__aeabi_fmul</STRONG> (Thumb, 100 bytes, Stack size 8 bytes, fmul.o(.text))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = __aeabi_fmul
-</UL>
-<BR>[Called By]<UL><LI><a href="#[5a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Systick_Period
-<LI><a href="#[54]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer2_PWM
-<LI><a href="#[53]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer1
-</UL>
-
-<P><STRONG><a name="[3b]"></a>__aeabi_fdiv</STRONG> (Thumb, 124 bytes, Stack size 8 bytes, fdiv.o(.text))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = __aeabi_fdiv
-</UL>
-<BR>[Calls]<UL><LI><a href="#[3c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_float_round
-</UL>
-<BR>[Called By]<UL><LI><a href="#[5a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Systick_Period
-<LI><a href="#[54]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer2_PWM
-</UL>
-
-<P><STRONG><a name="[3d]"></a>__aeabi_dmul</STRONG> (Thumb, 228 bytes, Stack size 48 bytes, dmul.o(.text))
-<BR><BR>[Stack]<UL><LI>Max Depth = 88<LI>Call Chain = __aeabi_dmul &rArr; _double_epilogue &rArr; _double_round
-</UL>
-<BR>[Calls]<UL><LI><a href="#[3e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_epilogue
-</UL>
-<BR>[Called By]<UL><LI><a href="#[5a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Systick_Period
-<LI><a href="#[53]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer1
-</UL>
-
-<P><STRONG><a name="[3f]"></a>__aeabi_ddiv</STRONG> (Thumb, 222 bytes, Stack size 32 bytes, ddiv.o(.text))
-<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = __aeabi_ddiv &rArr; _double_round
-</UL>
-<BR>[Calls]<UL><LI><a href="#[40]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_round
-</UL>
-<BR>[Called By]<UL><LI><a href="#[5a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Systick_Period
-<LI><a href="#[54]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer2_PWM
-<LI><a href="#[53]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer1
-</UL>
-
-<P><STRONG><a name="[41]"></a>__aeabi_ui2f</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, ffltui.o(.text))
-<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = __aeabi_ui2f &rArr; _float_epilogue
-</UL>
-<BR>[Calls]<UL><LI><a href="#[42]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_float_epilogue
-</UL>
-<BR>[Called By]<UL><LI><a href="#[5a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Systick_Period
-<LI><a href="#[54]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer2_PWM
-<LI><a href="#[53]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer1
-</UL>
-
-<P><STRONG><a name="[63]"></a>__aeabi_f2uiz</STRONG> (Thumb, 40 bytes, Stack size 0 bytes, ffixui.o(.text))
-<BR><BR>[Called By]<UL><LI><a href="#[5a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Systick_Period
-<LI><a href="#[54]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer2_PWM
-<LI><a href="#[53]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer1
-</UL>
-
-<P><STRONG><a name="[5e]"></a>__aeabi_f2d</STRONG> (Thumb, 38 bytes, Stack size 0 bytes, f2d.o(.text))
-<BR><BR>[Called By]<UL><LI><a href="#[5a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Systick_Period
-<LI><a href="#[54]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer2_PWM
-<LI><a href="#[53]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer1
-</UL>
-
-<P><STRONG><a name="[6f]"></a>__aeabi_cdcmpeq</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, cdcmple.o(.text), UNUSED)
-
-<P><STRONG><a name="[61]"></a>__aeabi_cdcmple</STRONG> (Thumb, 48 bytes, Stack size 0 bytes, cdcmple.o(.text))
-<BR><BR>[Called By]<UL><LI><a href="#[53]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer1
-</UL>
-
-<P><STRONG><a name="[62]"></a>__aeabi_cdrcmple</STRONG> (Thumb, 48 bytes, Stack size 0 bytes, cdrcmple.o(.text))
-<BR><BR>[Called By]<UL><LI><a href="#[5a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Systick_Period
-<LI><a href="#[53]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer1
-</UL>
-
-<P><STRONG><a name="[5f]"></a>__aeabi_d2f</STRONG> (Thumb, 56 bytes, Stack size 8 bytes, d2f.o(.text))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = __aeabi_d2f
-</UL>
-<BR>[Called By]<UL><LI><a href="#[5a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Systick_Period
-<LI><a href="#[54]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer2_PWM
-<LI><a href="#[53]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer1
-</UL>
-
-<P><STRONG><a name="[70]"></a>__I$use$fp</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, iusefp.o(.text), UNUSED)
-
-<P><STRONG><a name="[3c]"></a>_float_round</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, fepilogue.o(.text))
-<BR><BR>[Called By]<UL><LI><a href="#[3b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_fdiv
-</UL>
-
-<P><STRONG><a name="[42]"></a>_float_epilogue</STRONG> (Thumb, 92 bytes, Stack size 4 bytes, fepilogue.o(.text))
-<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = _float_epilogue
-</UL>
-<BR>[Called By]<UL><LI><a href="#[41]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ui2f
-</UL>
-
-<P><STRONG><a name="[40]"></a>_double_round</STRONG> (Thumb, 30 bytes, Stack size 8 bytes, depilogue.o(.text))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = _double_round
-</UL>
-<BR>[Called By]<UL><LI><a href="#[3e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_epilogue
-<LI><a href="#[3f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ddiv
-</UL>
-
-<P><STRONG><a name="[3e]"></a>_double_epilogue</STRONG> (Thumb, 156 bytes, Stack size 32 bytes, depilogue.o(.text))
-<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = _double_epilogue &rArr; _double_round
-</UL>
-<BR>[Calls]<UL><LI><a href="#[44]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_llsr
-<LI><a href="#[43]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_llsl
-<LI><a href="#[40]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_round
-</UL>
-<BR>[Called By]<UL><LI><a href="#[3d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_dmul
-</UL>
-
-<P><STRONG><a name="[3a]"></a>__scatterload</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
-<BR><BR>[Calls]<UL><LI><a href="#[45]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__main_after_scatterload
-</UL>
-<BR>[Called By]<UL><LI><a href="#[39]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_main_scatterload
-</UL>
-
-<P><STRONG><a name="[71]"></a>__scatterload_rt2</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)
-
-<P><STRONG><a name="[43]"></a>__aeabi_llsl</STRONG> (Thumb, 30 bytes, Stack size 0 bytes, llshl.o(.text))
-<BR><BR>[Called By]<UL><LI><a href="#[3e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_epilogue
-</UL>
-
-<P><STRONG><a name="[72]"></a>_ll_shift_l</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, llshl.o(.text), UNUSED)
-
-<P><STRONG><a name="[44]"></a>__aeabi_llsr</STRONG> (Thumb, 32 bytes, Stack size 0 bytes, llushr.o(.text))
-<BR><BR>[Called By]<UL><LI><a href="#[3e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_epilogue
-</UL>
-
-<P><STRONG><a name="[73]"></a>_ll_ushift_r</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, llushr.o(.text), UNUSED)
-
-<P><STRONG><a name="[38]"></a>Anim</STRONG> (Thumb, 32 bytes, Stack size 0 bytes, fonctiontimer.o(i.Anim))
-<BR>[Address Reference Count : 1]<UL><LI> initialisation.o(i.Init_Cible)
-</UL>
-<P><STRONG><a name="[46]"></a>Config_SPI</STRONG> (Thumb, 58 bytes, Stack size 8 bytes, spi.o(i.Config_SPI))
-<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = Config_SPI &rArr; SPI_Init
-</UL>
-<BR>[Calls]<UL><LI><a href="#[47]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI_Init
-<LI><a href="#[48]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI_Cmd
-</UL>
-<BR>[Called By]<UL><LI><a href="#[50]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-</UL>
-
-<P><STRONG><a name="[49]"></a>DMA1_Channel1_Event</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, dma_stm32f10x.o(i.DMA1_Channel1_Event))
-<BR><BR>[Called By]<UL><LI><a href="#[15]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA1_Channel1_IRQHandler
-</UL>
-
-<P><STRONG><a name="[15]"></a>DMA1_Channel1_IRQHandler</STRONG> (Thumb, 22 bytes, Stack size 8 bytes, dma_stm32f10x.o(i.DMA1_Channel1_IRQHandler))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = DMA1_Channel1_IRQHandler
-</UL>
-<BR>[Calls]<UL><LI><a href="#[49]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA1_Channel1_Event
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[4a]"></a>DMA1_Channel2_Event</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, dma_stm32f10x.o(i.DMA1_Channel2_Event))
-<BR><BR>[Called By]<UL><LI><a href="#[16]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA1_Channel2_IRQHandler
-</UL>
-
-<P><STRONG><a name="[16]"></a>DMA1_Channel2_IRQHandler</STRONG> (Thumb, 24 bytes, Stack size 8 bytes, dma_stm32f10x.o(i.DMA1_Channel2_IRQHandler))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = DMA1_Channel2_IRQHandler
-</UL>
-<BR>[Calls]<UL><LI><a href="#[4a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA1_Channel2_Event
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[4b]"></a>DMA1_Channel3_Event</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, dma_stm32f10x.o(i.DMA1_Channel3_Event))
-<BR><BR>[Called By]<UL><LI><a href="#[17]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA1_Channel3_IRQHandler
-</UL>
-
-<P><STRONG><a name="[17]"></a>DMA1_Channel3_IRQHandler</STRONG> (Thumb, 24 bytes, Stack size 8 bytes, dma_stm32f10x.o(i.DMA1_Channel3_IRQHandler))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = DMA1_Channel3_IRQHandler
-</UL>
-<BR>[Calls]<UL><LI><a href="#[4b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA1_Channel3_Event
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[4c]"></a>DMA1_Channel4_Event</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, dma_stm32f10x.o(i.DMA1_Channel4_Event))
-<BR><BR>[Called By]<UL><LI><a href="#[18]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA1_Channel4_IRQHandler
-</UL>
-
-<P><STRONG><a name="[18]"></a>DMA1_Channel4_IRQHandler</STRONG> (Thumb, 24 bytes, Stack size 8 bytes, dma_stm32f10x.o(i.DMA1_Channel4_IRQHandler))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = DMA1_Channel4_IRQHandler
-</UL>
-<BR>[Calls]<UL><LI><a href="#[4c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA1_Channel4_Event
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[4d]"></a>DMA1_Channel5_Event</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, dma_stm32f10x.o(i.DMA1_Channel5_Event))
-<BR><BR>[Called By]<UL><LI><a href="#[19]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA1_Channel5_IRQHandler
-</UL>
-
-<P><STRONG><a name="[19]"></a>DMA1_Channel5_IRQHandler</STRONG> (Thumb, 24 bytes, Stack size 8 bytes, dma_stm32f10x.o(i.DMA1_Channel5_IRQHandler))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = DMA1_Channel5_IRQHandler
-</UL>
-<BR>[Calls]<UL><LI><a href="#[4d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA1_Channel5_Event
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[4e]"></a>DMA1_Channel6_Event</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, dma_stm32f10x.o(i.DMA1_Channel6_Event))
-<BR><BR>[Called By]<UL><LI><a href="#[1a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA1_Channel6_IRQHandler
-</UL>
-
-<P><STRONG><a name="[1a]"></a>DMA1_Channel6_IRQHandler</STRONG> (Thumb, 24 bytes, Stack size 8 bytes, dma_stm32f10x.o(i.DMA1_Channel6_IRQHandler))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = DMA1_Channel6_IRQHandler
-</UL>
-<BR>[Calls]<UL><LI><a href="#[4e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA1_Channel6_Event
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[4f]"></a>DMA1_Channel7_Event</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, dma_stm32f10x.o(i.DMA1_Channel7_Event))
-<BR><BR>[Called By]<UL><LI><a href="#[1b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA1_Channel7_IRQHandler
-</UL>
-
-<P><STRONG><a name="[1b]"></a>DMA1_Channel7_IRQHandler</STRONG> (Thumb, 24 bytes, Stack size 8 bytes, dma_stm32f10x.o(i.DMA1_Channel7_IRQHandler))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = DMA1_Channel7_IRQHandler
-</UL>
-<BR>[Calls]<UL><LI><a href="#[4f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA1_Channel7_Event
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[5d]"></a>GPIO_Configure</STRONG> (Thumb, 314 bytes, Stack size 24 bytes, pilote_io_1.o(i.GPIO_Configure))
-<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = GPIO_Configure
-</UL>
-<BR>[Called By]<UL><LI><a href="#[51]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Port
-</UL>
-
-<P><STRONG><a name="[50]"></a>Init_Cible</STRONG> (Thumb, 218 bytes, Stack size 16 bytes, initialisation.o(i.Init_Cible))
-<BR><BR>[Stack]<UL><LI>Max Depth = 168<LI>Call Chain = Init_Cible &rArr; Init_Timer1 &rArr; __aeabi_dmul &rArr; _double_epilogue &rArr; _double_round
-</UL>
-<BR>[Calls]<UL><LI><a href="#[5b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Systick_Prio_IT
-<LI><a href="#[5a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Systick_Period
-<LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Port_IO_Set
-<LI><a href="#[59]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Port_IO_Reset
-<LI><a href="#[57]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Envoie192Boucle
-<LI><a href="#[46]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Config_SPI
-<LI><a href="#[56]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer4
-<LI><a href="#[55]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer3_Slave
-<LI><a href="#[54]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer2_PWM
-<LI><a href="#[53]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Timer1
-<LI><a href="#[51]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Port
-<LI><a href="#[52]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Dot
-</UL>
-<BR>[Called By]<UL><LI><a href="#[35]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
-</UL>
-
-<P><STRONG><a name="[52]"></a>Init_Dot</STRONG> (Thumb, 112 bytes, Stack size 16 bytes, initialisation.o(i.Init_Dot))
-<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = Init_Dot
-</UL>
-<BR>[Calls]<UL><LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Port_IO_Set
-<LI><a href="#[59]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Port_IO_Reset
-<LI><a href="#[5c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Envoie96Dot
-</UL>
-<BR>[Called By]<UL><LI><a href="#[50]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-</UL>
-
-<P><STRONG><a name="[51]"></a>Init_Port</STRONG> (Thumb, 134 bytes, Stack size 8 bytes, initialisation.o(i.Init_Port))
-<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = Init_Port &rArr; GPIO_Configure
-</UL>
-<BR>[Calls]<UL><LI><a href="#[5d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_Configure
-</UL>
-<BR>[Called By]<UL><LI><a href="#[50]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-</UL>
-
-<P><STRONG><a name="[53]"></a>Init_Timer1</STRONG> (Thumb, 336 bytes, Stack size 64 bytes, initialisation.o(i.Init_Timer1))
-<BR><BR>[Stack]<UL><LI>Max Depth = 152<LI>Call Chain = Init_Timer1 &rArr; __aeabi_dmul &rArr; _double_epilogue &rArr; _double_round
-</UL>
-<BR>[Calls]<UL><LI><a href="#[41]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ui2f
-<LI><a href="#[60]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_fmul
-<LI><a href="#[63]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_f2uiz
-<LI><a href="#[5e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_f2d
-<LI><a href="#[3d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_dmul
-<LI><a href="#[3f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ddiv
-<LI><a href="#[5f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_d2f
-<LI><a href="#[62]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_cdrcmple
-<LI><a href="#[61]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_cdcmple
-</UL>
-<BR>[Called By]<UL><LI><a href="#[50]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-</UL>
-
-<P><STRONG><a name="[54]"></a>Init_Timer2_PWM</STRONG> (Thumb, 262 bytes, Stack size 56 bytes, initialisation.o(i.Init_Timer2_PWM))
-<BR><BR>[Stack]<UL><LI>Max Depth = 96<LI>Call Chain = Init_Timer2_PWM &rArr; __aeabi_ddiv &rArr; _double_round
-</UL>
-<BR>[Calls]<UL><LI><a href="#[41]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ui2f
-<LI><a href="#[60]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_fmul
-<LI><a href="#[3b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_fdiv
-<LI><a href="#[63]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_f2uiz
-<LI><a href="#[5e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_f2d
-<LI><a href="#[3f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ddiv
-<LI><a href="#[5f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_d2f
-</UL>
-<BR>[Called By]<UL><LI><a href="#[50]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-</UL>
-
-<P><STRONG><a name="[55]"></a>Init_Timer3_Slave</STRONG> (Thumb, 94 bytes, Stack size 0 bytes, initialisation.o(i.Init_Timer3_Slave))
-<BR><BR>[Called By]<UL><LI><a href="#[50]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-</UL>
-
-<P><STRONG><a name="[56]"></a>Init_Timer4</STRONG> (Thumb, 100 bytes, Stack size 0 bytes, initialisation.o(i.Init_Timer4))
-<BR><BR>[Called By]<UL><LI><a href="#[50]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-</UL>
-
-<P><STRONG><a name="[59]"></a>Port_IO_Reset</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, pilote_io_1.o(i.Port_IO_Reset))
-<BR><BR>[Called By]<UL><LI><a href="#[50]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-<LI><a href="#[27]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIM3_IRQHandler
-<LI><a href="#[52]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Dot
-</UL>
-
-<P><STRONG><a name="[58]"></a>Port_IO_Set</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, pilote_io_1.o(i.Port_IO_Set))
-<BR><BR>[Called By]<UL><LI><a href="#[50]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-<LI><a href="#[27]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIM3_IRQHandler
-<LI><a href="#[52]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Dot
-</UL>
-
-<P><STRONG><a name="[48]"></a>SPI_Cmd</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, stm32f10x_spi.o(i.SPI_Cmd))
-<BR><BR>[Called By]<UL><LI><a href="#[46]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Config_SPI
-</UL>
-
-<P><STRONG><a name="[65]"></a>SPI_I2S_GetFlagStatus</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_spi.o(i.SPI_I2S_GetFlagStatus))
-<BR><BR>[Called By]<UL><LI><a href="#[64]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SendSPI
-</UL>
-
-<P><STRONG><a name="[66]"></a>SPI_I2S_SendData16</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, spi.o(i.SPI_I2S_SendData16))
-<BR><BR>[Called By]<UL><LI><a href="#[64]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SendSPI
-</UL>
-
-<P><STRONG><a name="[47]"></a>SPI_Init</STRONG> (Thumb, 60 bytes, Stack size 8 bytes, stm32f10x_spi.o(i.SPI_Init))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = SPI_Init
-</UL>
-<BR>[Called By]<UL><LI><a href="#[46]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Config_SPI
-</UL>
-
-<P><STRONG><a name="[64]"></a>SendSPI</STRONG> (Thumb, 130 bytes, Stack size 24 bytes, spi.o(i.SendSPI))
-<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = SendSPI
-</UL>
-<BR>[Calls]<UL><LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI_I2S_GetFlagStatus
-<LI><a href="#[66]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI_I2S_SendData16
-</UL>
-<BR>[Called By]<UL><LI><a href="#[28]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIM4_IRQHandler
-</UL>
-
-<P><STRONG><a name="[9]"></a>SysTick_Handler</STRONG> (Thumb, 10 bytes, Stack size 8 bytes, timer_systick_1.o(i.SysTick_Handler))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = SysTick_Handler
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[36]"></a>SystemInit</STRONG> (Thumb, 78 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SystemInit))
-<BR><BR>[Stack]<UL><LI>Max Depth = 28<LI>Call Chain = SystemInit &rArr; SetSysClock &rArr; SetSysClockTo72
-</UL>
-<BR>[Calls]<UL><LI><a href="#[67]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SetSysClock
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(.text)
-</UL>
-<P><STRONG><a name="[5a]"></a>Systick_Period</STRONG> (Thumb, 256 bytes, Stack size 48 bytes, timer_systick_1.o(i.Systick_Period))
-<BR><BR>[Stack]<UL><LI>Max Depth = 136<LI>Call Chain = Systick_Period &rArr; __aeabi_dmul &rArr; _double_epilogue &rArr; _double_round
-</UL>
-<BR>[Calls]<UL><LI><a href="#[41]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ui2f
-<LI><a href="#[60]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_fmul
-<LI><a href="#[3b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_fdiv
-<LI><a href="#[63]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_f2uiz
-<LI><a href="#[5e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_f2d
-<LI><a href="#[3d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_dmul
-<LI><a href="#[3f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ddiv
-<LI><a href="#[5f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_d2f
-<LI><a href="#[62]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_cdrcmple
-</UL>
-<BR>[Called By]<UL><LI><a href="#[50]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-</UL>
-
-<P><STRONG><a name="[5b]"></a>Systick_Prio_IT</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, timer_systick_1.o(i.Systick_Prio_IT))
-<BR><BR>[Called By]<UL><LI><a href="#[50]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-</UL>
-
-<P><STRONG><a name="[25]"></a>TIM1_CC_IRQHandler</STRONG> (Thumb, 158 bytes, Stack size 0 bytes, fonctiontimer.o(i.TIM1_CC_IRQHandler))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[23]"></a>TIM1_UP_IRQHandler</STRONG> (Thumb, 130 bytes, Stack size 8 bytes, fonctiontimer.o(i.TIM1_UP_IRQHandler))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = TIM1_UP_IRQHandler
-</UL>
-<BR>[Calls]<UL><LI><a href="#[57]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Envoie192Boucle
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[26]"></a>TIM2_IRQHandler</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, fonctiontimer.o(i.TIM2_IRQHandler))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[27]"></a>TIM3_IRQHandler</STRONG> (Thumb, 68 bytes, Stack size 8 bytes, fonctiontimer.o(i.TIM3_IRQHandler))
-<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = TIM3_IRQHandler
-</UL>
-<BR>[Calls]<UL><LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Port_IO_Set
-<LI><a href="#[59]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Port_IO_Reset
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[28]"></a>TIM4_IRQHandler</STRONG> (Thumb, 90 bytes, Stack size 8 bytes, fonctiontimer.o(i.TIM4_IRQHandler))
-<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = TIM4_IRQHandler &rArr; SendSPI
-</UL>
-<BR>[Calls]<UL><LI><a href="#[64]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SendSPI
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_md.o(RESET)
-</UL>
-<P><STRONG><a name="[74]"></a>__scatterload_copy</STRONG> (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)
-
-<P><STRONG><a name="[75]"></a>__scatterload_null</STRONG> (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)
-
-<P><STRONG><a name="[76]"></a>__scatterload_zeroinit</STRONG> (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)
-
-<P><STRONG><a name="[35]"></a>main</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, principale.o(moncode))
-<BR><BR>[Stack]<UL><LI>Max Depth = 168<LI>Call Chain = main &rArr; Init_Cible &rArr; Init_Timer1 &rArr; __aeabi_dmul &rArr; _double_epilogue &rArr; _double_round
-</UL>
-<BR>[Calls]<UL><LI><a href="#[50]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-</UL>
-<BR>[Address Reference Count : 1]<UL><LI> entry9a.o(.ARM.Collect$$$$0000000B)
-</UL>
-<P><STRONG><a name="[57]"></a>Envoie192Boucle</STRONG> (Thumb, 108 bytes, Stack size 0 bytes, foncasm.o(moncode))
-<BR><BR>[Called By]<UL><LI><a href="#[50]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Cible
-<LI><a href="#[23]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIM1_UP_IRQHandler
-</UL>
-
-<P><STRONG><a name="[5c]"></a>Envoie96Dot</STRONG> (Thumb, 78 bytes, Stack size 0 bytes, foncasm.o(moncode))
-<BR><BR>[Called By]<UL><LI><a href="#[52]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Init_Dot
-</UL>
-<P>
-<H3>
-Local Symbols
-</H3>
-<P><STRONG><a name="[67]"></a>SetSysClock</STRONG> (Thumb, 8 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SetSysClock))
-<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = SetSysClock &rArr; SetSysClockTo72
-</UL>
-<BR>[Calls]<UL><LI><a href="#[68]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SetSysClockTo72
-</UL>
-<BR>[Called By]<UL><LI><a href="#[36]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemInit
-</UL>
-
-<P><STRONG><a name="[68]"></a>SetSysClockTo72</STRONG> (Thumb, 214 bytes, Stack size 12 bytes, system_stm32f10x.o(i.SetSysClockTo72))
-<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = SetSysClockTo72
-</UL>
-<BR>[Called By]<UL><LI><a href="#[67]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SetSysClock
-</UL>
-<P>
-<H3>
-Undefined Global Symbols
-</H3><HR></body></html>
diff --git a/Objects/Simu_Etape0.lnp b/Objects/Simu_Etape0.lnp
deleted file mode 100644
index d8562e0..0000000
--- a/Objects/Simu_Etape0.lnp
+++ /dev/null
@@ -1,16 +0,0 @@
---cpu Cortex-M3
-".\objects\principale.o"
-".\objects\fonctionetape.o"
-".\Matos.lib"
-".\objects\misc.o"
-".\objects\stm32f10x_rcc.o"
-".\objects\stm32f10x_spi.o"
-".\objects\stm32f10x_tim.o"
-".\objects\dma_stm32f10x.o"
-".\objects\gpio_stm32f10x.o"
-".\objects\startup_stm32f10x_md.o"
-".\objects\system_stm32f10x.o"
---library_type=microlib --strict --scatter ".\Objects\Simu_Etape0.sct"
---summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
---info sizes --info totals --info unused --info veneers
---list ".\Listings\Simu_Etape0.map" -o .\Objects\Simu_Etape0.axf
\ No newline at end of file
diff --git a/Objects/Simu_Etape0.sct b/Objects/Simu_Etape0.sct
deleted file mode 100644
index c26b647..0000000
--- a/Objects/Simu_Etape0.sct
+++ /dev/null
@@ -1,15 +0,0 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x08000000 0x00020000  {    ; load region size_region
-  ER_IROM1 0x08000000 0x00020000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  RW_IRAM1 0x20000000 0x00005000  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-}
-
diff --git a/Objects/dma_stm32f10x.crf b/Objects/dma_stm32f10x.crf
deleted file mode 100644
index 56752db..0000000
Binary files a/Objects/dma_stm32f10x.crf and /dev/null differ
diff --git a/Objects/dma_stm32f10x.d b/Objects/dma_stm32f10x.d
deleted file mode 100644
index ee5eeb8..0000000
--- a/Objects/dma_stm32f10x.d
+++ /dev/null
@@ -1,16 +0,0 @@
-.\objects\dma_stm32f10x.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\RTE_Driver\DMA_STM32F10x.c
-.\objects\dma_stm32f10x.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\RTE_Driver\DMA_STM32F10x.h
-.\objects\dma_stm32f10x.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
-.\objects\dma_stm32f10x.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdbool.h
-.\objects\dma_stm32f10x.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\STM32F10x.h
-.\objects\dma_stm32f10x.o: .\RTE\_Simul_\RTE_Components.h
-.\objects\dma_stm32f10x.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\core_cm3.h
-.\objects\dma_stm32f10x.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_compiler.h
-.\objects\dma_stm32f10x.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_armcc.h
-.\objects\dma_stm32f10x.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h
-.\objects\dma_stm32f10x.o: .\RTE\Device\STM32F103RB\stm32f10x_conf.h
-.\objects\dma_stm32f10x.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h
-.\objects\dma_stm32f10x.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h
-.\objects\dma_stm32f10x.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_spi.h
-.\objects\dma_stm32f10x.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_tim.h
-.\objects\dma_stm32f10x.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\misc.h
diff --git a/Objects/dma_stm32f10x.o b/Objects/dma_stm32f10x.o
deleted file mode 100644
index 9887d39..0000000
Binary files a/Objects/dma_stm32f10x.o and /dev/null differ
diff --git a/Objects/fonctionetape.d b/Objects/fonctionetape.d
deleted file mode 100644
index eb6ee88..0000000
--- a/Objects/fonctionetape.d
+++ /dev/null
@@ -1,2 +0,0 @@
-.\objects\fonctionetape.o: FonctionEtape.asm
-.\objects\fonctionetape.o: REG_UTILES.inc
diff --git a/Objects/fonctionetape.o b/Objects/fonctionetape.o
deleted file mode 100644
index 91b8aa9..0000000
Binary files a/Objects/fonctionetape.o and /dev/null differ
diff --git a/Objects/gpio_stm32f10x.crf b/Objects/gpio_stm32f10x.crf
deleted file mode 100644
index a6dfd02..0000000
Binary files a/Objects/gpio_stm32f10x.crf and /dev/null differ
diff --git a/Objects/gpio_stm32f10x.d b/Objects/gpio_stm32f10x.d
deleted file mode 100644
index a5d2a99..0000000
--- a/Objects/gpio_stm32f10x.d
+++ /dev/null
@@ -1,16 +0,0 @@
-.\objects\gpio_stm32f10x.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\RTE_Driver\GPIO_STM32F10x.c
-.\objects\gpio_stm32f10x.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\RTE_Driver\GPIO_STM32F10x.h
-.\objects\gpio_stm32f10x.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdbool.h
-.\objects\gpio_stm32f10x.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h
-.\objects\gpio_stm32f10x.o: .\RTE\_Simul_\RTE_Components.h
-.\objects\gpio_stm32f10x.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\core_cm3.h
-.\objects\gpio_stm32f10x.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
-.\objects\gpio_stm32f10x.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_compiler.h
-.\objects\gpio_stm32f10x.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_armcc.h
-.\objects\gpio_stm32f10x.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h
-.\objects\gpio_stm32f10x.o: .\RTE\Device\STM32F103RB\stm32f10x_conf.h
-.\objects\gpio_stm32f10x.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h
-.\objects\gpio_stm32f10x.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h
-.\objects\gpio_stm32f10x.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_spi.h
-.\objects\gpio_stm32f10x.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_tim.h
-.\objects\gpio_stm32f10x.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\misc.h
diff --git a/Objects/gpio_stm32f10x.o b/Objects/gpio_stm32f10x.o
deleted file mode 100644
index e645fc6..0000000
Binary files a/Objects/gpio_stm32f10x.o and /dev/null differ
diff --git a/Objects/misc.crf b/Objects/misc.crf
deleted file mode 100644
index e78a85e..0000000
Binary files a/Objects/misc.crf and /dev/null differ
diff --git a/Objects/misc.d b/Objects/misc.d
deleted file mode 100644
index e2555a2..0000000
--- a/Objects/misc.d
+++ /dev/null
@@ -1,15 +0,0 @@
-.\objects\misc.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\src\misc.c
-.\objects\misc.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\misc.h
-.\objects\misc.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h
-.\objects\misc.o: .\RTE\_Simul_\RTE_Components.h
-.\objects\misc.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\core_cm3.h
-.\objects\misc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
-.\objects\misc.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_compiler.h
-.\objects\misc.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_armcc.h
-.\objects\misc.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h
-.\objects\misc.o: .\RTE\Device\STM32F103RB\stm32f10x_conf.h
-.\objects\misc.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h
-.\objects\misc.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h
-.\objects\misc.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_spi.h
-.\objects\misc.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_tim.h
-.\objects\misc.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\misc.h
diff --git a/Objects/misc.o b/Objects/misc.o
deleted file mode 100644
index fe2350c..0000000
Binary files a/Objects/misc.o and /dev/null differ
diff --git a/Objects/principale.d b/Objects/principale.d
deleted file mode 100644
index b241556..0000000
--- a/Objects/principale.d
+++ /dev/null
@@ -1,2 +0,0 @@
-.\objects\principale.o: Principale.asm
-.\objects\principale.o: REG_UTILES.inc
diff --git a/Objects/principale.o b/Objects/principale.o
deleted file mode 100644
index c9b30be..0000000
Binary files a/Objects/principale.o and /dev/null differ
diff --git a/Objects/startup_stm32f10x_cl.d b/Objects/startup_stm32f10x_cl.d
deleted file mode 100644
index 54017af..0000000
--- a/Objects/startup_stm32f10x_cl.d
+++ /dev/null
@@ -1 +0,0 @@
-.\objects\startup_stm32f10x_cl.o: RTE\Device\STM32F107VC\startup_stm32f10x_cl.s
diff --git a/Objects/startup_stm32f10x_cl.o b/Objects/startup_stm32f10x_cl.o
deleted file mode 100644
index 1d6bead..0000000
Binary files a/Objects/startup_stm32f10x_cl.o and /dev/null differ
diff --git a/Objects/startup_stm32f10x_md.d b/Objects/startup_stm32f10x_md.d
deleted file mode 100644
index 96d5fcf..0000000
--- a/Objects/startup_stm32f10x_md.d
+++ /dev/null
@@ -1 +0,0 @@
-.\objects\startup_stm32f10x_md.o: RTE\Device\STM32F103RB\startup_stm32f10x_md.s
diff --git a/Objects/startup_stm32f10x_md.o b/Objects/startup_stm32f10x_md.o
deleted file mode 100644
index 28f1c86..0000000
Binary files a/Objects/startup_stm32f10x_md.o and /dev/null differ
diff --git a/Objects/stm32f10x_rcc.crf b/Objects/stm32f10x_rcc.crf
deleted file mode 100644
index f71b345..0000000
Binary files a/Objects/stm32f10x_rcc.crf and /dev/null differ
diff --git a/Objects/stm32f10x_rcc.d b/Objects/stm32f10x_rcc.d
deleted file mode 100644
index c1a524d..0000000
--- a/Objects/stm32f10x_rcc.d
+++ /dev/null
@@ -1,15 +0,0 @@
-.\objects\stm32f10x_rcc.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\src\stm32f10x_rcc.c
-.\objects\stm32f10x_rcc.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h
-.\objects\stm32f10x_rcc.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h
-.\objects\stm32f10x_rcc.o: .\RTE\_Simul_\RTE_Components.h
-.\objects\stm32f10x_rcc.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\core_cm3.h
-.\objects\stm32f10x_rcc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
-.\objects\stm32f10x_rcc.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_compiler.h
-.\objects\stm32f10x_rcc.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_armcc.h
-.\objects\stm32f10x_rcc.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h
-.\objects\stm32f10x_rcc.o: .\RTE\Device\STM32F103RB\stm32f10x_conf.h
-.\objects\stm32f10x_rcc.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h
-.\objects\stm32f10x_rcc.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_spi.h
-.\objects\stm32f10x_rcc.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h
-.\objects\stm32f10x_rcc.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_tim.h
-.\objects\stm32f10x_rcc.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\misc.h
diff --git a/Objects/stm32f10x_rcc.o b/Objects/stm32f10x_rcc.o
deleted file mode 100644
index 9fdc201..0000000
Binary files a/Objects/stm32f10x_rcc.o and /dev/null differ
diff --git a/Objects/stm32f10x_spi.crf b/Objects/stm32f10x_spi.crf
deleted file mode 100644
index 9ccfe8a..0000000
Binary files a/Objects/stm32f10x_spi.crf and /dev/null differ
diff --git a/Objects/stm32f10x_spi.d b/Objects/stm32f10x_spi.d
deleted file mode 100644
index 32cee08..0000000
--- a/Objects/stm32f10x_spi.d
+++ /dev/null
@@ -1,15 +0,0 @@
-.\objects\stm32f10x_spi.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\src\stm32f10x_spi.c
-.\objects\stm32f10x_spi.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_spi.h
-.\objects\stm32f10x_spi.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h
-.\objects\stm32f10x_spi.o: .\RTE\_Simul_\RTE_Components.h
-.\objects\stm32f10x_spi.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\core_cm3.h
-.\objects\stm32f10x_spi.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
-.\objects\stm32f10x_spi.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_compiler.h
-.\objects\stm32f10x_spi.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_armcc.h
-.\objects\stm32f10x_spi.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h
-.\objects\stm32f10x_spi.o: .\RTE\Device\STM32F103RB\stm32f10x_conf.h
-.\objects\stm32f10x_spi.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h
-.\objects\stm32f10x_spi.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h
-.\objects\stm32f10x_spi.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_spi.h
-.\objects\stm32f10x_spi.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_tim.h
-.\objects\stm32f10x_spi.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\misc.h
diff --git a/Objects/stm32f10x_spi.o b/Objects/stm32f10x_spi.o
deleted file mode 100644
index a34b157..0000000
Binary files a/Objects/stm32f10x_spi.o and /dev/null differ
diff --git a/Objects/stm32f10x_tim.crf b/Objects/stm32f10x_tim.crf
deleted file mode 100644
index 3928902..0000000
Binary files a/Objects/stm32f10x_tim.crf and /dev/null differ
diff --git a/Objects/stm32f10x_tim.d b/Objects/stm32f10x_tim.d
deleted file mode 100644
index 3653cb8..0000000
--- a/Objects/stm32f10x_tim.d
+++ /dev/null
@@ -1,15 +0,0 @@
-.\objects\stm32f10x_tim.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\src\stm32f10x_tim.c
-.\objects\stm32f10x_tim.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_tim.h
-.\objects\stm32f10x_tim.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h
-.\objects\stm32f10x_tim.o: .\RTE\_Simul_\RTE_Components.h
-.\objects\stm32f10x_tim.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\core_cm3.h
-.\objects\stm32f10x_tim.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
-.\objects\stm32f10x_tim.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_compiler.h
-.\objects\stm32f10x_tim.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_armcc.h
-.\objects\stm32f10x_tim.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h
-.\objects\stm32f10x_tim.o: .\RTE\Device\STM32F103RB\stm32f10x_conf.h
-.\objects\stm32f10x_tim.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_rcc.h
-.\objects\stm32f10x_tim.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h
-.\objects\stm32f10x_tim.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_spi.h
-.\objects\stm32f10x_tim.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\stm32f10x_tim.h
-.\objects\stm32f10x_tim.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\StdPeriph_Driver\inc\misc.h
diff --git a/Objects/stm32f10x_tim.o b/Objects/stm32f10x_tim.o
deleted file mode 100644
index bf5bd41..0000000
Binary files a/Objects/stm32f10x_tim.o and /dev/null differ
diff --git a/Objects/system_stm32f10x.crf b/Objects/system_stm32f10x.crf
deleted file mode 100644
index e0d3c9e..0000000
Binary files a/Objects/system_stm32f10x.crf and /dev/null differ
diff --git a/Objects/system_stm32f10x.d b/Objects/system_stm32f10x.d
deleted file mode 100644
index 21393ad..0000000
--- a/Objects/system_stm32f10x.d
+++ /dev/null
@@ -1,8 +0,0 @@
-.\objects\system_stm32f10x.o: RTE\Device\STM32F107VC\system_stm32f10x.c
-.\objects\system_stm32f10x.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h
-.\objects\system_stm32f10x.o: .\RTE\_R_el\RTE_Components.h
-.\objects\system_stm32f10x.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\core_cm3.h
-.\objects\system_stm32f10x.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
-.\objects\system_stm32f10x.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_compiler.h
-.\objects\system_stm32f10x.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\cmsis_armcc.h
-.\objects\system_stm32f10x.o: C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h
diff --git a/Objects/system_stm32f10x.o b/Objects/system_stm32f10x.o
deleted file mode 100644
index 09df696..0000000
Binary files a/Objects/system_stm32f10x.o and /dev/null differ
diff --git a/Principale.asm b/Principale.asm
index af34ba9..ed5b7c8 100644
--- a/Principale.asm
+++ b/Principale.asm
@@ -7,7 +7,7 @@
 ;************************************************************************
 
 	include REG_UTILES.inc
-
+	include LUMIERES.inc
 
 ;************************************************************************
 ; 					IMPORT/EXPORT Système
@@ -21,40 +21,113 @@
 ; IMPORT/EXPORT de procédure           
 
 	IMPORT Init_Cible
-	
+	IMPORT Run_Timer3
+	IMPORT Run_Timer1
+		
+;******ETAPE 1*********
+		
+	IMPORT Eteint_LED
+	IMPORT Allume_LED
+	IMPORT Inverse_LED
+
+;******ETAPE 2*********
+
+	IMPORT Set_SCLK
+	IMPORT Reset_SCLK
+	IMPORT DriverGlobal
+	IMPORT DriverReg
+	IMPORT Tempo
+
+;******ETAPE 3*********
+
+	IMPORT Init_TVI
+	IMPORT Timer1_IRQHandler
+	IMPORT Timer1Up_IRQHandler
+	IMPORT setIRQFunction
+	IMPORT Timer4_IRQHandler
 
 	EXPORT main
 	
-;*******************************************************************************
-
-
-;*******************************************************************************
+;***************VARIABLES*******************************************************
 	AREA  mesdonnees, data, readwrite
-
-	
-
-
 ;*******************************************************************************
-	
-	AREA  moncode, code, readonly
 		
+M						EQU 20
+Timer_Up_Reg			EQU	(25*4)+0x40
+Timer_Cc_Reg			EQU	(27*4)+0x40
+Timer4_Reg				EQU	(30*4)+0x40
 
-
+;***************CODE************************************************************
+   	AREA  moncode, code, readonly
+; 	Procédure principale et point d'entrée du projet
+;*******************************************************************************	
+main   PROC 
 ;*******************************************************************************
-; Procédure principale et point d'entrée du projet
-;*******************************************************************************
-main  	PROC 
-;*******************************************************************************
-
-		
-		MOV R0,#0
+		BL Init_TVI;
+		MOV R0,#2
 		BL Init_Cible;
-		
+;*******************************************************************************
+; ETAPE 3
+;*******************************************************************************
+		MOV R0, #Timer_Up_Reg
+		LDR R1,=Timer1Up_IRQHandler
+		BL setIRQFunction
+		MOV R0, #Timer_Cc_Reg
+		LDR R1,=Timer1_IRQHandler
+		BL setIRQFunction
+		MOV R0, #Timer4_Reg
+		LDR R1,=Timer4_IRQHandler
+		BL setIRQFunction
+		BL Run_Timer3			;Allumage du Timer 3
+		BL Run_Timer1
+;*******************************************************************************
+; ETAPE 2
+;*******************************************************************************
+;		MOV R7,#0
+;Etape2								;for(int=0;i<M;i++)
+;		LDR R0, =Barette3			;Adresse Jeu de led 1 : Argument
+;		BL DriverReg				;*******************
+;		MOV R0, #500					;Argument : 500ms
+;		BL Tempo;					:Tempo(10)
+;		LDR R0, =Barette2			;Adresse Jeu de led 2 : Argument
+;		BL DriverReg				;*******************
+;		MOV R0, #500					;Argument : 500ms
+;		BL Tempo;					:Tempo(10)
+;		
+;		LDR R6,=GPIOBASEA			;On récup l'adresse	du GPIOA
+;		LDR R6,[R6,#OffsetInput]	;On lit le GPIOA_IDR
+;		AND R6, R6, #(0x01<<8)		;On masque pour n'avoir que le 9ème bit (Capteur)
+;		CMP R6, #(0x01<<8)			;On vérifie que ce dernier bit est bien à 1.
+;		BNE TheEnd					;if capteur = true -> on sort de la boucle
+;		ADD R7,R7,#1				;i++
+;		CMP R7, #M					;i==M ?
+;		BNE Etape2					;if i!=10 -> on continue la boucle (Au final : R7 == M || R6)
+;*******************************************************************************
+; ETAPE 1
+;*******************************************************************************
+;		MOV R0,#0;
+;		MOV R1,#0;
+;		MOV R3,#0;
+;Boucle
+;		LDR R12,=GPIOBASEA			;On récup l'adresse	du GPIOA		
+;		LDR R0,[R12,#OffsetInput]	;On charge sa valeur avec l'OffsetInput
+;		AND R0, R0, #(0x01 << 8)	;R0 est masqué pour n'avoir que le bit de l'offset input
+;		CMP R0, #(0x01 << 8)		;On compare R0 doit etre egal à 1 pour le front montant
+;		BNE Is_detect				;On allume
+;		MOV R1,R0					;R1 possède la valeur de R0 avant
+;		BL Boucle					;Sinon on boucle
+;				
+;Is_detect
+;		CMP R1, #(0x01 << 8)		;R1 doit etre egal à 0 pour le front montant
+;		BNE Boucle
+;
+;T_Oui
+;		BL Inverse_LED				;On inverse le status de la led grace a R3
+;		B Boucle
+;		
+;*******************************************************************************
+TheEnd
 		B .			 ; boucle inifinie terminale...
-
-
-
-
 		ENDP
 
 	END
diff --git a/README.md b/README.md
index 2d04234..b155863 100644
--- a/README.md
+++ b/README.md
@@ -1 +1,127 @@
-# roue_assembler
+# But du projet
+Le but sera de faire fonctionner diverses LEDS à l'aide d'un STM32 et tout cela en langage Assembler.
+# Fonctionnalitées
+
+## Variables
+|Nom|Description|Source|Type|
+|---|---|---|---|
+|Barette1|Jeu de LED : 16\*3 Données sur 1 octet|[LUMIERES.inc](LUMIERES.inc)|```Data Memory```|
+|Barette2|2ème jeu de LED avec des couleurs différentes|[LUMIERES.inc](LUMIERES.inc)|```Data Memory```|
+|SCLK|PIN pour SCLK (5)|[FonctionEtape2.asm](FonctionEtape2.asm)|```Egalitée```|
+|SIN1|PIN pour SIN1 (7)|[FonctionEtape2.asm](FonctionEtape2.asm)|```Egalitée```|
+|MILSEC|Pour Tempo(Nms) -> Le nombre d'itération pour avoir 1ms|[FonctionEtape2.asm](FonctionEtape2.asm)|```Egalitée```|
+|PF|Décalage à 31 bits pour le Poid Fort|[FonctionEtape2.asm](FonctionEtape2.asm)|```Data Memory```|
+|DataSend|Variable globale pour savoir si une donnée est transmise|[FonctionEtape2.asm](FonctionEtape2.asm)|```Data Memory```|
+## Fonctions
+|Nom|Argument(s)|Retour|Description|
+|---|---|---|---|
+|Set_X|**1** - R0 : PINAX||Pour un output donné, met à 1 ce dernier.|
+|Reset_X|**1** - R0 : PINAX||Pour un output donné, force à 0 ce dernier.|
+|DriverGlobal|||Envoie les signaux liés à la LED|
+|Tempo|**1** - R0 : Nms||Pour un temps donné, le processeur se met en attente (similaire à sleep)|
+|DriverReg|**1** - R0 : \*LEDArray||Pour une Barette de LED donnée, envoie les signaux demandés|
+
+---
+Chaque fonction prendra des arguments de R0 à R3 (avec R3 étant une référence au tas si le besoin d'argument est supérieur à 3). Le renvoi se fait sur R0.
+
+## Main
+
+La première chose pour l'étape 2 est de mettre l'argument de Init_Cible à 1. Malheuresement cette partie étant précompilé, il n'est pas possible de modifier directement les variables qu'il lit dans la pile. En effet en lisant les premières lignes nous pouvons appercevoir quelques lectures de variables :
+```assembly
+Init_Cible PROC
+	PUSH {R4-R6}
+	MOV R4,R0
+	LDR R0,[pc,#212]  ; @0x080009A4
+	LDR R0,[R0,#0x18] ; On lit dans 0x40021000 la variable en 0x18
+	ORR R0,R0,#0x0C   ; On force la valeur 0x0C dans R0
+ENDP
+```
+
+Visiblement, d'après la librairie STM32 0x40021000 correspond au RCC, plus précisement au APB2ENR *(décalé de 24 octets.)* :
+
+```c
+	RCC_TypeDef * rccPointer = RCC ;                  //0x40021000
+	volatile uint32_t * apb2enrValue = &(RCC->APB2ENR);		//0x40021018
+```
+
+En réalité j'ai par la suite changé ce paramètre en 1. Avec la valeur forcée en 0x0C, cela va donner 0x0D soit 1101. D'après la datasheet cela devrait activer la clock sur le GPIOA et B. le 0x01 lui va activer le AFIO qui est étrange ? L'argument de la fonction ne serait donc pas cette variable, qui est juste globale. Mais je ne vois pas d'autre solution pour le moment.. En effet bien que R4 et R6 sont égaux à 0 dès le lancement de cette fonction, elles sont directement modifiée pour lire des variables stockées dans le tas. 
+
+(Par la suite le Timer2,3,4 sont allumés (APB1ENR |= 0x07))
+
+On appelle ensuite DriverReg qui va lire dans R0 l'adresse du tableau de LEDS. Ce dernier doit contenir les 16\*3 valeurs de leds. Une tempo est ensuite lancée, et un nouveau jeu de led est lu.
+
+## Variables globales
+
+- SCLK *(5)* et SIN1 *(7)* sont des variables globales permettant avec la fonction Set/Reset_X de définir l'état de sortie d'une pin X. 
+- PF *(1<<31)* est le poids fort, comme il n'est pas possible d'utiliser l'instruction **MOV** avec des nombres supérieurs à 1 octet, il est préférable d'utiliser une variable globale avec cette valeur.
+- Barette1 (16\*3 valeurs), tableau contenant pour chaque LED *(16)*, le niveau RVB.
+
+## Chronogramme
+
+Voici le premier chronogramme observable avec les états de SCLK et SIN1. Aucun test matériel n'a encore été réalisé :
+![SIN SCLK Graph](assets/graph_complete.png)
+Dans la dernière version du programme, deux jeux de LEDS sont envoyés après une tempo de quelques millisecondes. Voici les chronogrammes de ces dernières en simulation :
+
+![SIN SCLK Animated GIF](assets/graph_animated.gif)
+
+# Réaliser un code assembler à partir de C
+Comme vous le savez le code en langage C peut être compilé puis récupéré en assembler. C'est justement ici une solution que j'ai trouvé pour mieux comprendre différents principes, ou si certaines instructions ne me paraissent pas clair.
+Bien évidemment le but du projet n'est pas de recopier bêtement du code que le compilateur peut réaliser, mais de comprendre et de voir comment faire différents algorithmes en Assembler.
+
+La première chose est d'installer le package suivant sur une machine Linux :
+```bash
+sudo dnf install arm-none-eabi-gcc
+```
+*J'utilise Fedora donc mon package manager est dnf, mais cela fonctionne avec apt ou pacman*
+
+Ensuite il suffit de créer un programme en C, voici en un par exemple qui m'a aidé à comprendre l'inversion des bits, ou comment le C récupère les arguments d'une fonction :
+```c
+void set(int pin);
+int invert(int x);
+
+void * gpioA = (void *)0x40010800;
+
+int main(void)
+{
+	set(5);
+	invert(0x20);
+	return 0;
+}
+
+void set(int pin){ *((short *)(globalPtr+0xc)) |= (0x01 << pin) }
+int invert(int x){ return ~x }
+```
+
+Ensuite je lance la commande suivante pour compiler le tout dans un niveau d'optimisation choisi :
+```shell
+arm-bibe-eabi-gcc -OX -c test.c -o test.o
+```
+
+|Argument|Type d'optimisation du compilateur|
+|---|---|
+|-O0|Zero|
+|-O1|Normale|
+|-O2|Maximale|
+
+Et enfin pour voir le résultat en assembler dans la le terminal :
+```shell
+arm-none-eabi-objdump -D test.o
+```
+
+Nous obtenons le résultat suivant :
+
+```assembly
+00000000 <invert>:
+   0:e1e00000 mvn   r0, r0
+   4:e12fff1e bx    lr
+
+00000008 <set>:
+   8:e3a01001 mov   r1, #1
+   c:e59f3010 ldr   r3, [pc, #16]@ 24 <add+0x1c>
+  10:e5932000 ldr   r2, [r3]
+  14:e1d230b5 ldrh  r3, [r2, #5]
+  18:e1c33011 bic   r3, r3, r1, lsl r0
+  1c:e1c230b5 strh  r3, [r2, #5]
+  20:e12fff1e bx    lr
+  24:00000000 andeq r0, r0, r0
+```
\ No newline at end of file
diff --git a/REG_UTILES.inc b/REG_UTILES.inc
index 6eea1dc..c5b9576 100644
--- a/REG_UTILES.inc
+++ b/REG_UTILES.inc
@@ -45,9 +45,6 @@ TIM1_SR			EQU 0x40012c10
 TIM1_CNT 		EQU 0x40012c24
 TIM4_ARR 		EQU 0x4000082C 
 TIM4_SR 		EQU 0x40000810
-
-	
-	
 	
 	
 	END
\ No newline at end of file
diff --git a/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2 b/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2
new file mode 100644
index 0000000..0d10ed8
--- /dev/null
+++ b/RTE/Device/STM32F103RB/RTE_Device.h.base@1.1.2
@@ -0,0 +1,1828 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013-2016 Arm Limited (or its affiliates). All 
+ * rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * $Date:        09. September 2016
+ * $Revision:    V1.1.2
+ *
+ * Project:      RTE Device Configuration for STMicroelectronics STM32F1xx
+ *
+ * -------------------------------------------------------------------------- */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+
+#define GPIO_PORT(num) \
+ ((num == 0) ? GPIOA : \
+  (num == 1) ? GPIOB : \
+  (num == 2) ? GPIOC : \
+  (num == 3) ? GPIOD : \
+  (num == 4) ? GPIOE : \
+  (num == 5) ? GPIOF : \
+  (num == 6) ? GPIOG : \
+  NULL)
+
+
+// <h> Clock Configuration
+//   <o> High-speed Internal Clock <1-999999999>
+#define RTE_HSI                         8000000
+//   <o> High-speed External Clock <1-999999999>
+#define RTE_HSE                         25000000
+//   <o> System Clock <1-999999999>
+#define RTE_SYSCLK                      72000000
+//   <o> HCLK Clock   <1-999999999>
+#define RTE_HCLK                        72000000
+//   <o> APB1 Clock   <1-999999999>
+#define RTE_PCLK1                       36000000
+//   <o> APB2 Clock   <1-999999999>
+#define RTE_PCLK2                       72000000
+//   <o> ADC Clock    <1-999999999>
+#define RTE_ADCCLK                      36000000
+//       USB Clock
+#define RTE_USBCLK                      48000000
+// </h>
+
+
+// <e> USART1 (Universal synchronous asynchronous receiver transmitter)
+// <i> Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART
+#define RTE_USART1                       0
+
+//   <o> USART1_TX Pin <0=>Not Used <1=>PA9
+#define RTE_USART1_TX_PORT_ID_DEF       0
+#if    (RTE_USART1_TX_PORT_ID_DEF == 0)
+#define RTE_USART1_TX_DEF               0
+#elif  (RTE_USART1_TX_PORT_ID_DEF == 1)
+#define RTE_USART1_TX_DEF               1
+#define RTE_USART1_TX_PORT_DEF          GPIOA
+#define RTE_USART1_TX_BIT_DEF           9
+#else
+#error "Invalid USART1_TX Pin Configuration!"
+#endif
+
+//   <o> USART1_RX Pin <0=>Not Used <1=>PA10
+#define RTE_USART1_RX_PORT_ID_DEF       0
+#if    (RTE_USART1_RX_PORT_ID_DEF == 0)
+#define RTE_USART1_RX_DEF               0
+#elif  (RTE_USART1_RX_PORT_ID_DEF == 1)
+#define RTE_USART1_RX_DEF               1
+#define RTE_USART1_RX_PORT_DEF          GPIOA
+#define RTE_USART1_RX_BIT_DEF           10
+#else
+#error "Invalid USART1_RX Pin Configuration!"
+#endif
+
+//   <o> USART1_CK Pin <0=>Not Used <1=>PA8
+#define RTE_USART1_CK_PORT_ID_DEF       0
+#if    (RTE_USART1_CK_PORT_ID_DEF == 0)
+#define RTE_USART1_CK                   0
+#elif  (RTE_USART1_CK_PORT_ID_DEF == 1)
+#define RTE_USART1_CK                   1
+#define RTE_USART1_CK_PORT_DEF          GPIOA
+#define RTE_USART1_CK_BIT_DEF           8
+#else
+#error "Invalid USART1_CK Pin Configuration!"
+#endif
+
+//   <o> USART1_CTS Pin <0=>Not Used <1=>PA11
+#define RTE_USART1_CTS_PORT_ID_DEF      0
+#if    (RTE_USART1_CTS_PORT_ID_DEF == 0)
+#define RTE_USART1_CTS                  0
+#elif  (RTE_USART1_CTS_PORT_ID_DEF == 1)
+#define RTE_USART1_CTS                  1
+#define RTE_USART1_CTS_PORT_DEF         GPIOA
+#define RTE_USART1_CTS_BIT_DEF          11
+#else
+#error "Invalid USART1_CTS Pin Configuration!"
+#endif
+
+//   <o> USART1_RTS Pin <0=>Not Used <1=>PA12
+#define RTE_USART1_RTS_PORT_ID_DEF      0
+#if    (RTE_USART1_RTS_PORT_ID_DEF == 0)
+#define RTE_USART1_RTS                  0
+#elif  (RTE_USART1_RTS_PORT_ID_DEF == 1)
+#define RTE_USART1_RTS                  1
+#define RTE_USART1_RTS_PORT_DEF         GPIOA
+#define RTE_USART1_RTS_BIT_DEF          12
+#else
+#error "Invalid USART1_RTS Pin Configuration!"
+#endif
+
+//   <e> USART1 Pin Remap
+//   <i> Enable USART1 Pin Remapping
+#define RTE_USART1_REMAP_FULL           0
+
+//     <o> USART1_TX Pin <0=>Not Used <1=>PB6
+#define RTE_USART1_TX_PORT_ID_FULL      0
+#if    (RTE_USART1_TX_PORT_ID_FULL == 0)
+#define RTE_USART1_TX_FULL              0
+#elif  (RTE_USART1_TX_PORT_ID_FULL == 1)
+#define RTE_USART1_TX_FULL              1
+#define RTE_USART1_TX_PORT_FULL         GPIOB
+#define RTE_USART1_TX_BIT_FULL          6
+#else
+#error "Invalid USART1_TX Pin Configuration!"
+#endif
+
+//     <o> USART1_RX Pin <0=>Not Used <1=>PB7
+#define RTE_USART1_RX_PORT_ID_FULL      0
+#if    (RTE_USART1_RX_PORT_ID_FULL == 0)
+#define RTE_USART1_RX_FULL              0
+#elif  (RTE_USART1_RX_PORT_ID_FULL == 1)
+#define RTE_USART1_RX_FULL              1
+#define RTE_USART1_RX_PORT_FULL         GPIOB
+#define RTE_USART1_RX_BIT_FULL          7
+#else
+#error "Invalid USART1_RX Pin Configuration!"
+#endif
+//   </e>
+
+#if    (RTE_USART1_REMAP_FULL)
+#define RTE_USART1_AF_REMAP              AFIO_USART1_REMAP
+#define RTE_USART1_TX                    RTE_USART1_TX_FULL
+#define RTE_USART1_TX_PORT               RTE_USART1_TX_PORT_FULL
+#define RTE_USART1_TX_BIT                RTE_USART1_TX_BIT_FULL
+#define RTE_USART1_RX                    RTE_USART1_RX_FULL
+#define RTE_USART1_RX_PORT               RTE_USART1_RX_PORT_FULL
+#define RTE_USART1_RX_BIT                RTE_USART1_RX_BIT_FULL
+#define RTE_USART1_CK_PORT               RTE_USART1_CK_PORT_DEF
+#define RTE_USART1_CK_BIT                RTE_USART1_CK_BIT_DEF
+#define RTE_USART1_CTS_PORT              RTE_USART1_CTS_PORT_DEF
+#define RTE_USART1_CTS_BIT               RTE_USART1_CTS_BIT_DEF
+#define RTE_USART1_RTS_PORT              RTE_USART1_RTS_PORT_DEF
+#define RTE_USART1_RTS_BIT               RTE_USART1_RTS_BIT_DEF
+#else 
+#define RTE_USART1_AF_REMAP              AFIO_USART1_NO_REMAP
+#define RTE_USART1_TX                    RTE_USART1_TX_DEF
+#define RTE_USART1_TX_PORT               RTE_USART1_TX_PORT_DEF
+#define RTE_USART1_TX_BIT                RTE_USART1_TX_BIT_DEF
+#define RTE_USART1_RX                    RTE_USART1_RX_DEF
+#define RTE_USART1_RX_PORT               RTE_USART1_RX_PORT_DEF
+#define RTE_USART1_RX_BIT                RTE_USART1_RX_BIT_DEF
+#define RTE_USART1_CK_PORT               RTE_USART1_CK_PORT_DEF
+#define RTE_USART1_CK_BIT                RTE_USART1_CK_BIT_DEF
+#define RTE_USART1_CTS_PORT              RTE_USART1_CTS_PORT_DEF
+#define RTE_USART1_CTS_BIT               RTE_USART1_CTS_BIT_DEF
+#define RTE_USART1_RTS_PORT              RTE_USART1_RTS_PORT_DEF
+#define RTE_USART1_RTS_BIT               RTE_USART1_RTS_BIT_DEF
+#endif
+
+//   <e> DMA Rx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <5=>5
+//     <i>  Selects DMA Channel (only Channel 5 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Set DMA Channel priority
+//   </e>
+#define RTE_USART1_RX_DMA               0
+#define RTE_USART1_RX_DMA_NUMBER        1
+#define RTE_USART1_RX_DMA_CHANNEL       5
+#define RTE_USART1_RX_DMA_PRIORITY      0
+//   <e> DMA Tx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <4=>4
+//     <i>  Selects DMA Channel (only Channel 4 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Set DMA Channel priority
+//   </e>
+#define RTE_USART1_TX_DMA               0
+#define RTE_USART1_TX_DMA_NUMBER        1
+#define RTE_USART1_TX_DMA_CHANNEL       4
+#define RTE_USART1_TX_DMA_PRIORITY      0
+// </e>
+
+
+// <e> USART2 (Universal synchronous asynchronous receiver transmitter)
+// <i> Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART
+#define RTE_USART2                      0
+
+//   <o> USART2_TX Pin <0=>Not Used <1=>PA2
+#define RTE_USART2_TX_PORT_ID_DEF       0
+#if    (RTE_USART2_TX_PORT_ID_DEF == 0)
+#define RTE_USART2_TX_DEF               0
+#elif  (RTE_USART2_TX_PORT_ID_DEF == 1)
+#define RTE_USART2_TX_DEF               1
+#define RTE_USART2_TX_PORT_DEF          GPIOA
+#define RTE_USART2_TX_BIT_DEF           2
+#else
+#error "Invalid USART2_TX Pin Configuration!"
+#endif
+
+//   <o> USART2_RX Pin <0=>Not Used <1=>PA3
+#define RTE_USART2_RX_PORT_ID_DEF       0
+#if    (RTE_USART2_RX_PORT_ID_DEF == 0)
+#define RTE_USART2_RX_DEF               0
+#elif  (RTE_USART2_RX_PORT_ID_DEF == 1)
+#define RTE_USART2_RX_DEF               1
+#define RTE_USART2_RX_PORT_DEF          GPIOA
+#define RTE_USART2_RX_BIT_DEF           3
+#else
+#error "Invalid USART2_RX Pin Configuration!"
+#endif
+
+//   <o> USART2_CK Pin <0=>Not Used <1=>PA4
+#define RTE_USART2_CK_PORT_ID_DEF       0
+#if    (RTE_USART2_CK_PORT_ID_DEF == 0)
+#define RTE_USART2_CK_DEF               0
+#elif  (RTE_USART2_CK_PORT_ID_DEF == 1)
+#define RTE_USART2_CK_DEF               1
+#define RTE_USART2_CK_PORT_DEF          GPIOA
+#define RTE_USART2_CK_BIT_DEF           4
+#else
+#error "Invalid USART2_CK Pin Configuration!"
+#endif
+
+//   <o> USART2_CTS Pin <0=>Not Used <1=>PA0
+#define RTE_USART2_CTS_PORT_ID_DEF      0
+#if    (RTE_USART2_CTS_PORT_ID_DEF == 0)
+#define RTE_USART2_CTS_DEF              0
+#elif  (RTE_USART2_CTS_PORT_ID_DEF == 1)
+#define RTE_USART2_CTS_DEF              1
+#define RTE_USART2_CTS_PORT_DEF         GPIOA
+#define RTE_USART2_CTS_BIT_DEF          0
+#else
+#error "Invalid USART2_CTS Pin Configuration!"
+#endif
+
+//   <o> USART2_RTS Pin <0=>Not Used <1=>PA1
+#define RTE_USART2_RTS_PORT_ID_DEF      0
+#if    (RTE_USART2_RTS_PORT_ID_DEF == 0)
+#define RTE_USART2_RTS_DEF              0
+#elif  (RTE_USART2_RTS_PORT_ID_DEF == 1)
+#define RTE_USART2_RTS_DEF              1
+#define RTE_USART2_RTS_PORT_DEF         GPIOA
+#define RTE_USART2_RTS_BIT_DEF          1
+#else
+#error "Invalid USART2_RTS Pin Configuration!"
+#endif
+
+//   <e> USART2 Pin Remap
+//   <i> Enable USART2 Pin Remapping
+#define RTE_USART2_REMAP_FULL           0
+
+//     <o> USART2_TX Pin <0=>Not Used <1=>PD5
+#define RTE_USART2_TX_PORT_ID_FULL      0
+#if    (RTE_USART2_TX_PORT_ID_FULL == 0)
+#define RTE_USART2_TX_FULL              0
+#elif  (RTE_USART2_TX_PORT_ID_FULL == 1)
+#define RTE_USART2_TX_FULL              1
+#define RTE_USART2_TX_PORT_FULL         GPIOD
+#define RTE_USART2_TX_BIT_FULL          5
+#else
+#error "Invalid USART2_TX Pin Configuration!"
+#endif
+
+//     <o> USART2_RX Pin <0=>Not Used <1=>PD6
+#define RTE_USART2_RX_PORT_ID_FULL      0
+#if    (RTE_USART2_RX_PORT_ID_FULL == 0)
+#define RTE_USART2_RX_FULL              0
+#elif  (RTE_USART2_RX_PORT_ID_FULL == 1)
+#define RTE_USART2_RX_FULL              1
+#define RTE_USART2_RX_PORT_FULL         GPIOD
+#define RTE_USART2_RX_BIT_FULL          6
+#else
+#error "Invalid USART2_RX Pin Configuration!"
+#endif
+
+//     <o> USART2_CK Pin <0=>Not Used <1=>PD7
+#define RTE_USART2_CK_PORT_ID_FULL      0
+#if    (RTE_USART2_CK_PORT_ID_FULL == 0)
+#define RTE_USART2_CK_FULL              0
+#elif  (RTE_USART2_CK_PORT_ID_FULL == 1)
+#define RTE_USART2_CK_FULL              1
+#define RTE_USART2_CK_PORT_FULL         GPIOD
+#define RTE_USART2_CK_BIT_FULL          7
+#else
+#error "Invalid USART2_CK Pin Configuration!"
+#endif
+
+//     <o> USART2_CTS Pin <0=>Not Used <1=>PD3
+#define RTE_USART2_CTS_PORT_ID_FULL     0
+#if    (RTE_USART2_CTS_PORT_ID_FULL == 0)
+#define RTE_USART2_CTS_FULL             0
+#elif  (RTE_USART2_CTS_PORT_ID_FULL == 1)
+#define RTE_USART2_CTS_FULL             1
+#define RTE_USART2_CTS_PORT_FULL        GPIOD
+#define RTE_USART2_CTS_BIT_FULL         3
+#else
+#error "Invalid USART2_CTS Pin Configuration!"
+#endif
+
+//     <o> USART2_RTS Pin <0=>Not Used <1=>PD4
+#define RTE_USART2_RTS_PORT_ID_FULL     0
+#if    (RTE_USART2_RTS_PORT_ID_FULL == 0)
+#define RTE_USART2_RTS_FULL             0
+#elif  (RTE_USART2_RTS_PORT_ID_FULL == 1)
+#define RTE_USART2_RTS_FULL             1
+#define RTE_USART2_RTS_PORT_FULL        GPIOD
+#define RTE_USART2_RTS_BIT_FULL         4
+#else
+#error "Invalid USART2_RTS Pin Configuration!"
+#endif
+//   </e>
+
+#if    (RTE_USART2_REMAP_FULL)
+#define RTE_USART2_AF_REMAP              AFIO_USART2_REMAP
+#define RTE_USART2_TX                    RTE_USART2_TX_FULL
+#define RTE_USART2_TX_PORT               RTE_USART2_TX_PORT_FULL
+#define RTE_USART2_TX_BIT                RTE_USART2_TX_BIT_FULL
+#define RTE_USART2_RX                    RTE_USART2_RX_FULL
+#define RTE_USART2_RX_PORT               RTE_USART2_RX_PORT_FULL
+#define RTE_USART2_RX_BIT                RTE_USART2_RX_BIT_FULL
+#define RTE_USART2_CK                    RTE_USART2_CK_FULL
+#define RTE_USART2_CK_PORT               RTE_USART2_CK_PORT_FULL
+#define RTE_USART2_CK_BIT                RTE_USART2_CK_BIT_FULL
+#define RTE_USART2_CTS                   RTE_USART2_CTS_FULL
+#define RTE_USART2_CTS_PORT              RTE_USART2_CTS_PORT_FULL
+#define RTE_USART2_CTS_BIT               RTE_USART2_CTS_BIT_FULL
+#define RTE_USART2_RTS                   RTE_USART2_RTS_FULL
+#define RTE_USART2_RTS_PORT              RTE_USART2_RTS_PORT_FULL
+#define RTE_USART2_RTS_BIT               RTE_USART2_RTS_BIT_FULL
+#else 
+#define RTE_USART2_AF_REMAP              AFIO_USART2_NO_REMAP
+#define RTE_USART2_TX                    RTE_USART2_TX_DEF
+#define RTE_USART2_TX_PORT               RTE_USART2_TX_PORT_DEF
+#define RTE_USART2_TX_BIT                RTE_USART2_TX_BIT_DEF
+#define RTE_USART2_RX                    RTE_USART2_RX_DEF
+#define RTE_USART2_RX_PORT               RTE_USART2_RX_PORT_DEF
+#define RTE_USART2_RX_BIT                RTE_USART2_RX_BIT_DEF
+#define RTE_USART2_CK                    RTE_USART2_CK_DEF
+#define RTE_USART2_CK_PORT               RTE_USART2_CK_PORT_DEF
+#define RTE_USART2_CK_BIT                RTE_USART2_CK_BIT_DEF
+#define RTE_USART2_CTS                   RTE_USART2_CTS_DEF
+#define RTE_USART2_CTS_PORT              RTE_USART2_CTS_PORT_DEF
+#define RTE_USART2_CTS_BIT               RTE_USART2_CTS_BIT_DEF
+#define RTE_USART2_RTS                   RTE_USART2_RTS_DEF
+#define RTE_USART2_RTS_PORT              RTE_USART2_RTS_PORT_DEF
+#define RTE_USART2_RTS_BIT               RTE_USART2_RTS_BIT_DEF
+#endif
+
+//   <e> DMA Rx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <6=>6
+//     <i>  Selects DMA Channel (only Channel 6 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Set DMA Channel priority
+//   </e>
+#define RTE_USART2_RX_DMA               0
+#define RTE_USART2_RX_DMA_NUMBER        1
+#define RTE_USART2_RX_DMA_CHANNEL       6
+#define RTE_USART2_RX_DMA_PRIORITY      0
+
+//   <e> DMA Tx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <7=>7
+//     <i>  Selects DMA Channel (only Channel 7 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Set DMA Channel priority
+//   </e>
+#define RTE_USART2_TX_DMA               0
+#define RTE_USART2_TX_DMA_NUMBER        1
+#define RTE_USART2_TX_DMA_CHANNEL       7
+#define RTE_USART2_TX_DMA_PRIORITY      0
+
+// </e>
+
+
+// <e> USART3 (Universal synchronous asynchronous receiver transmitter)
+// <i> Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART
+#define RTE_USART3                      0
+
+//   <o> USART3_TX Pin <0=>Not Used <1=>PB10
+#define RTE_USART3_TX_PORT_ID_DEF       0
+#if    (RTE_USART3_TX_PORT_ID_DEF == 0)
+#define RTE_USART3_TX_DEF               0
+#elif  (RTE_USART3_TX_PORT_ID_DEF == 1)
+#define RTE_USART3_TX_DEF               1
+#define RTE_USART3_TX_PORT_DEF          GPIOB
+#define RTE_USART3_TX_BIT_DEF           10
+#else
+#error "Invalid USART3_TX Pin Configuration!"
+#endif
+
+//   <o> USART3_RX Pin <0=>Not Used <1=>PB11
+#define RTE_USART3_RX_PORT_ID_DEF       0
+#if    (RTE_USART3_RX_PORT_ID_DEF == 0)
+#define RTE_USART3_RX_DEF               0
+#elif  (RTE_USART3_RX_PORT_ID_DEF == 1)
+#define RTE_USART3_RX_DEF               1
+#define RTE_USART3_RX_PORT_DEF          GPIOB
+#define RTE_USART3_RX_BIT_DEF           11
+#else
+#error "Invalid USART3_RX Pin Configuration!"
+#endif
+
+//   <o> USART3_CK Pin <0=>Not Used <1=>PB12
+#define RTE_USART3_CK_PORT_ID_DEF       0
+#if    (RTE_USART3_CK_PORT_ID_DEF == 0)
+#define RTE_USART3_CK_DEF               0
+#elif  (RTE_USART3_CK_PORT_ID_DEF == 1)
+#define RTE_USART3_CK_DEF               1
+#define RTE_USART3_CK_PORT_DEF          GPIOB
+#define RTE_USART3_CK_BIT_DEF           12
+#else
+#error "Invalid USART3_CK Pin Configuration!"
+#endif
+
+//   <o> USART3_CTS Pin <0=>Not Used <1=>PB13
+#define RTE_USART3_CTS_PORT_ID_DEF      0
+#if    (RTE_USART3_CTS_PORT_ID_DEF == 0)
+#define RTE_USART3_CTS_DEF              0
+#elif  (RTE_USART3_CTS_PORT_ID_DEF == 1)
+#define RTE_USART3_CTS_DEF              1
+#define RTE_USART3_CTS_PORT_DEF         GPIOB
+#define RTE_USART3_CTS_BIT_DEF          13
+#else
+#error "Invalid USART3_CTS Pin Configuration!"
+#endif
+
+//   <o> USART3_RTS Pin <0=>Not Used <1=>PB14
+#define RTE_USART3_RTS_PORT_ID_DEF      0
+#if    (RTE_USART3_RTS_PORT_ID_DEF == 0)
+#define RTE_USART3_RTS_DEF              0
+#elif  (RTE_USART3_RTS_PORT_ID_DEF == 1)
+#define RTE_USART3_RTS_DEF              1
+#define RTE_USART3_RTS_PORT_DEF         GPIOB
+#define RTE_USART3_RTS_BIT_DEF          14
+#else
+#error "Invalid USART3_RTS Pin Configuration!"
+#endif
+
+//   <e> USART3 Partial Pin Remap
+//   <i> Enable USART3 Partial Pin Remapping
+#define RTE_USART3_REMAP_PARTIAL        0
+
+//     <o> USART3_TX Pin <0=>Not Used <1=>PC10
+#define RTE_USART3_TX_PORT_ID_PARTIAL   0
+#if    (RTE_USART3_TX_PORT_ID_PARTIAL == 0)
+#define RTE_USART3_TX_PARTIAL           0
+#elif  (RTE_USART3_TX_PORT_ID_PARTIAL == 1)
+#define RTE_USART3_TX_PARTIAL           1
+#define RTE_USART3_TX_PORT_PARTIAL      GPIOC
+#define RTE_USART3_TX_BIT_PARTIAL       10
+#else
+#error "Invalid USART3_TX Pin Configuration!"
+#endif
+
+//     <o> USART3_RX Pin <0=>Not Used <1=>PC11
+#define RTE_USART3_RX_PORT_ID_PARTIAL   0
+#if    (RTE_USART3_RX_PORT_ID_PARTIAL == 0)
+#define RTE_USART3_RX_PARTIAL           0
+#elif  (RTE_USART3_RX_PORT_ID_PARTIAL == 1)
+#define RTE_USART3_RX_PARTIAL           1
+#define RTE_USART3_RX_PORT_PARTIAL      GPIOC
+#define RTE_USART3_RX_BIT_PARTIAL       11
+#else
+#error "Invalid USART3_RX Pin Configuration!"
+#endif
+
+//     <o> USART3_CK Pin <0=>Not Used <1=>PC12
+#define RTE_USART3_CK_PORT_ID_PARTIAL   0
+#if    (RTE_USART3_CK_PORT_ID_PARTIAL == 0)
+#define RTE_USART3_CK_PARTIAL           0
+#elif  (RTE_USART3_CK_PORT_ID_PARTIAL == 1)
+#define RTE_USART3_CK_PARTIAL           1
+#define RTE_USART3_CK_PORT_PARTIAL      GPIOC
+#define RTE_USART3_CK_BIT_PARTIAL       12
+#else
+#error "Invalid USART3_CK Pin Configuration!"
+#endif
+//   </e>
+
+//   <e> USART3 Full Pin Remap
+//   <i> Enable USART3 Full Pin Remapping
+#define RTE_USART3_REMAP_FULL           0
+
+//     <o> USART3_TX Pin <0=>Not Used <1=>PD8
+#define RTE_USART3_TX_PORT_ID_FULL      0
+#if    (RTE_USART3_TX_PORT_ID_FULL == 0)
+#define RTE_USART3_TX_FULL              0
+#elif  (RTE_USART3_TX_PORT_ID_FULL == 1)
+#define RTE_USART3_TX_FULL              1
+#define RTE_USART3_TX_PORT_FULL         GPIOD
+#define RTE_USART3_TX_BIT_FULL          8
+#else
+#error "Invalid USART3_TX Pin Configuration!"
+#endif
+
+//     <o> USART3_RX Pin <0=>Not Used <1=>PD9
+#define RTE_USART3_RX_PORT_ID_FULL      0
+#if    (RTE_USART3_RX_PORT_ID_FULL == 0)
+#define RTE_USART3_RX_FULL              0
+#elif  (RTE_USART3_RX_PORT_ID_FULL == 1)
+#define RTE_USART3_RX_FULL              1
+#define RTE_USART3_RX_PORT_FULL         GPIOD
+#define RTE_USART3_RX_BIT_FULL          9
+#else
+#error "Invalid USART3_RX Pin Configuration!"
+#endif
+
+//     <o> USART3_CK Pin <0=>Not Used <1=>PD10
+#define RTE_USART3_CK_PORT_ID_FULL      0
+#if    (RTE_USART3_CK_PORT_ID_FULL == 0)
+#define RTE_USART3_CK_FULL              0
+#elif  (RTE_USART3_CK_PORT_ID_FULL == 1)
+#define RTE_USART3_CK_FULL              1
+#define RTE_USART3_CK_PORT_FULL         GPIOD
+#define RTE_USART3_CK_BIT_FULL          10
+#else
+#error "Invalid USART3_CK Pin Configuration!"
+#endif
+
+//     <o> USART3_CTS Pin <0=>Not Used <1=>PD11
+#define RTE_USART3_CTS_PORT_ID_FULL     0
+#if    (RTE_USART3_CTS_PORT_ID_FULL == 0)
+#define RTE_USART3_CTS_FULL             0
+#elif  (RTE_USART3_CTS_PORT_ID_FULL == 1)
+#define RTE_USART3_CTS_FULL             1
+#define RTE_USART3_CTS_PORT_FULL        GPIOD
+#define RTE_USART3_CTS_BIT_FULL         11
+#else
+#error "Invalid USART3_CTS Pin Configuration!"
+#endif
+
+//     <o> USART3_RTS Pin <0=>Not Used <1=>PD12
+#define RTE_USART3_RTS_PORT_ID_FULL     0
+#if    (RTE_USART3_RTS_PORT_ID_FULL == 0)
+#define RTE_USART3_RTS_FULL             0
+#elif  (RTE_USART3_RTS_PORT_ID_FULL == 1)
+#define RTE_USART3_RTS_FULL             1
+#define RTE_USART3_RTS_PORT_FULL        GPIOD
+#define RTE_USART3_RTS_BIT_FULL         12
+#else
+#error "Invalid USART3_RTS Pin Configuration!"
+#endif
+//   </e>
+
+#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1))
+#error "Invalid USART3 Pin Remap Configuration!"
+#endif
+
+#if    (RTE_USART3_REMAP_FULL)
+#define RTE_USART3_AF_REMAP              AFIO_USART3_REMAP_FULL
+#define RTE_USART3_TX                    RTE_USART3_TX_FULL
+#define RTE_USART3_TX_PORT               RTE_USART3_TX_PORT_FULL
+#define RTE_USART3_TX_BIT                RTE_USART3_TX_BIT_FULL
+#define RTE_USART3_RX                    RTE_USART3_RX_FULL
+#define RTE_USART3_RX_PORT               RTE_USART3_RX_PORT_FULL
+#define RTE_USART3_RX_BIT                RTE_USART3_RX_BIT_FULL
+#define RTE_USART3_CK                    RTE_USART3_CK_FULL
+#define RTE_USART3_CK_PORT               RTE_USART3_CK_PORT_FULL
+#define RTE_USART3_CK_BIT                RTE_USART3_CK_BIT_FULL
+#define RTE_USART3_CTS                   RTE_USART3_CTS_FULL
+#define RTE_USART3_CTS_PORT              RTE_USART3_CTS_PORT_FULL
+#define RTE_USART3_CTS_BIT               RTE_USART3_CTS_BIT_FULL
+#define RTE_USART3_RTS                   RTE_USART3_RTS_FULL
+#define RTE_USART3_RTS_PORT              RTE_USART3_RTS_PORT_FULL
+#define RTE_USART3_RTS_BIT               RTE_USART3_RTS_BIT_FULL
+#elif  (RTE_USART3_REMAP_PARTIAL)
+#define RTE_USART3_AF_REMAP              AFIO_USART3_REMAP_PARTIAL
+#define RTE_USART3_TX                    RTE_USART3_TX_PARTIAL
+#define RTE_USART3_TX_PORT               RTE_USART3_TX_PORT_PARTIAL
+#define RTE_USART3_TX_BIT                RTE_USART3_TX_BIT_PARTIAL
+#define RTE_USART3_RX                    RTE_USART3_RX_PARTIAL
+#define RTE_USART3_RX_PORT               RTE_USART3_RX_PORT_PARTIAL
+#define RTE_USART3_RX_BIT                RTE_USART3_RX_BIT_PARTIAL
+#define RTE_USART3_CK                    RTE_USART3_CK_PARTIAL
+#define RTE_USART3_CK_PORT               RTE_USART3_CK_PORT_PARTIAL
+#define RTE_USART3_CK_BIT                RTE_USART3_CK_BIT_PARTIAL
+#define RTE_USART3_CTS                   RTE_USART3_CTS_DEF
+#define RTE_USART3_CTS_PORT              RTE_USART3_CTS_PORT_DEF
+#define RTE_USART3_CTS_BIT               RTE_USART3_CTS_BIT_DEF
+#define RTE_USART3_RTS                   RTE_USART3_RTS_DEF
+#define RTE_USART3_RTS_PORT              RTE_USART3_RTS_PORT_DEF
+#define RTE_USART3_RTS_BIT               RTE_USART3_RTS_BIT_DEF
+#else
+#define RTE_USART3_AF_REMAP              AFIO_USART3_NO_REMAP
+#define RTE_USART3_TX                    RTE_USART3_TX_DEF
+#define RTE_USART3_TX_PORT               RTE_USART3_TX_PORT_DEF
+#define RTE_USART3_TX_BIT                RTE_USART3_TX_BIT_DEF
+#define RTE_USART3_RX                    RTE_USART3_RX_DEF
+#define RTE_USART3_RX_PORT               RTE_USART3_RX_PORT_DEF
+#define RTE_USART3_RX_BIT                RTE_USART3_RX_BIT_DEF
+#define RTE_USART3_CK                    RTE_USART3_CK_DEF
+#define RTE_USART3_CK_PORT               RTE_USART3_CK_PORT_DEF
+#define RTE_USART3_CK_BIT                RTE_USART3_CK_BIT_DEF
+#define RTE_USART3_CTS                   RTE_USART3_CTS_DEF
+#define RTE_USART3_CTS_PORT              RTE_USART3_CTS_PORT_DEF
+#define RTE_USART3_CTS_BIT               RTE_USART3_CTS_BIT_DEF
+#define RTE_USART3_RTS                   RTE_USART3_RTS_DEF
+#define RTE_USART3_RTS_PORT              RTE_USART3_RTS_PORT_DEF
+#define RTE_USART3_RTS_BIT               RTE_USART3_RTS_BIT_DEF
+#endif
+
+//   <e> DMA Rx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <3=>3
+//     <i>  Selects DMA Channel (only Channel 3 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Sets DMA Channel priority
+//   </e>
+#define RTE_USART3_RX_DMA               0
+#define RTE_USART3_RX_DMA_NUMBER        1
+#define RTE_USART3_RX_DMA_CHANNEL       3
+#define RTE_USART3_RX_DMA_PRIORITY      0
+
+//   <e> DMA Tx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <2=>2
+//     <i>  Selects DMA Channel (only Channel 2 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Sets DMA Channel priority
+//   </e>
+#define RTE_USART3_TX_DMA               0
+#define RTE_USART3_TX_DMA_NUMBER        1
+#define RTE_USART3_TX_DMA_CHANNEL       2
+#define RTE_USART3_TX_DMA_PRIORITY      0
+
+// </e>
+
+
+// <e> UART4 (Universal asynchronous receiver transmitter)
+// <i> Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART
+#define RTE_UART4                       0
+#define RTE_UART4_AF_REMAP              AFIO_UNAVAILABLE_REMAP
+
+//   <o> UART4_TX Pin <0=>Not Used <1=>PC10
+#define RTE_UART4_TX_ID                 0
+#if    (RTE_UART4_TX_ID == 0)
+#define RTE_UART4_TX                    0
+#elif  (RTE_UART4_TX_ID == 1)
+#define RTE_UART4_TX                    1
+#define RTE_UART4_TX_PORT               GPIOC
+#define RTE_UART4_TX_BIT                10
+#else
+#error "Invalid UART4_TX Pin Configuration!"
+#endif
+
+//   <o> UART4_RX Pin <0=>Not Used <1=>PC11
+#define RTE_UART4_RX_ID                 0
+#if    (RTE_UART4_RX_ID == 0)
+#define RTE_UART4_RX                    0
+#elif  (RTE_UART4_RX_ID == 1)
+#define RTE_UART4_RX                    1
+#define RTE_UART4_RX_PORT               GPIOC
+#define RTE_UART4_RX_BIT                11
+#else
+#error "Invalid UART4_RX Pin Configuration!"
+#endif
+
+
+//   <e> DMA Rx
+//     <o1> Number <2=>2
+//     <i>  Selects DMA Number (only DMA2 can be used)
+//     <o2> Channel <3=>3
+//     <i>  Selects DMA Channel (only Channel 3 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Sets DMA Channel priority
+//   </e>
+#define RTE_UART4_RX_DMA                0
+#define RTE_UART4_RX_DMA_NUMBER         2
+#define RTE_UART4_RX_DMA_CHANNEL        3
+#define RTE_UART4_RX_DMA_PRIORITY       0
+
+//   <e> DMA Tx
+//     <o1> Number <2=>2
+//     <i>  Selects DMA Number (only DMA2 can be used)
+//     <o2> Channel <5=>5
+//     <i>  Selects DMA Channel (only Channel 5 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Sets DMA Channel priority
+//   </e>
+#define RTE_UART4_TX_DMA                0
+#define RTE_UART4_TX_DMA_NUMBER         2
+#define RTE_UART4_TX_DMA_CHANNEL        5
+#define RTE_UART4_TX_DMA_PRIORITY       0
+
+// </e>
+
+
+// <e> UART5 (Universal asynchronous receiver transmitter)
+// <i> Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART
+#define RTE_UART5                       0
+#define RTE_UART5_AF_REMAP              AFIO_UNAVAILABLE_REMAP
+
+//   <o> UART5_TX Pin <0=>Not Used <1=>PC12
+#define RTE_UART5_TX_ID                 0
+#if    (RTE_UART5_TX_ID == 0)
+#define RTE_UART5_TX                    0
+#elif  (RTE_UART5_TX_ID == 1)
+#define RTE_UART5_TX                    1
+#define RTE_UART5_TX_PORT               GPIOC
+#define RTE_UART5_TX_BIT                12
+#else
+#error "Invalid UART5_TX Pin Configuration!"
+#endif
+
+//   <o> UART5_RX Pin <0=>Not Used <1=>PD2
+#define RTE_UART5_RX_ID                 0
+#if    (RTE_UART5_RX_ID == 0)
+#define RTE_UART5_RX                    0
+#elif  (RTE_UART5_RX_ID == 1)
+#define RTE_UART5_RX                    1
+#define RTE_UART5_RX_PORT               GPIOD
+#define RTE_UART5_RX_BIT                2
+#else
+#error "Invalid UART5_RX Pin Configuration!"
+#endif
+// </e>
+
+
+// <e> I2C1 (Inter-integrated Circuit Interface 1)
+// <i> Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C
+#define RTE_I2C1                        0
+
+//   <o> I2C1_SCL Pin <0=>PB6
+#define RTE_I2C1_SCL_PORT_ID_DEF        0
+#if    (RTE_I2C1_SCL_PORT_ID_DEF == 0)
+#define RTE_I2C1_SCL_PORT_DEF           GPIOB
+#define RTE_I2C1_SCL_BIT_DEF            6
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+//   <o> I2C1_SDA Pin <0=>PB7
+#define RTE_I2C1_SDA_PORT_ID_DEF        0
+#if    (RTE_I2C1_SDA_PORT_ID_DEF == 0)
+#define RTE_I2C1_SDA_PORT_DEF           GPIOB
+#define RTE_I2C1_SDA_BIT_DEF            7
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+//   <e> I2C1 Pin Remap
+//   <i> Enable I2C1 Pin Remapping
+#define RTE_I2C1_REMAP_FULL             0
+
+//   <o> I2C1_SCL Pin <0=>PB8
+#define RTE_I2C1_SCL_PORT_ID_FULL       0
+#if    (RTE_I2C1_SCL_PORT_ID_FULL == 0)
+#define RTE_I2C1_SCL_PORT_FULL          GPIOB
+#define RTE_I2C1_SCL_BIT_FULL           8
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+//   <o> I2C1_SDA Pin <0=>PB9
+#define RTE_I2C1_SDA_PORT_ID_FULL       0
+#if    (RTE_I2C1_SDA_PORT_ID_FULL == 0)
+#define RTE_I2C1_SDA_PORT_FULL          GPIOB
+#define RTE_I2C1_SDA_BIT_FULL           9
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+//   </e>
+
+#if    (RTE_I2C1_REMAP_FULL)
+#define RTE_I2C1_AF_REMAP               AFIO_I2C1_REMAP
+#define RTE_I2C1_SCL_PORT               RTE_I2C1_SCL_PORT_FULL
+#define RTE_I2C1_SCL_BIT                RTE_I2C1_SCL_BIT_FULL
+#define RTE_I2C1_SDA_PORT               RTE_I2C1_SDA_PORT_FULL
+#define RTE_I2C1_SDA_BIT                RTE_I2C1_SDA_BIT_FULL
+#else
+#define RTE_I2C1_AF_REMAP               AFIO_I2C1_NO_REMAP
+#define RTE_I2C1_SCL_PORT               RTE_I2C1_SCL_PORT_DEF
+#define RTE_I2C1_SCL_BIT                RTE_I2C1_SCL_BIT_DEF
+#define RTE_I2C1_SDA_PORT               RTE_I2C1_SDA_PORT_DEF
+#define RTE_I2C1_SDA_BIT                RTE_I2C1_SDA_BIT_DEF
+#endif
+
+
+//   <e> DMA Rx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <7=>7
+//     <i>  Selects DMA Channel (only Channel 7 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_I2C1_RX_DMA                 0
+#define RTE_I2C1_RX_DMA_NUMBER          1
+#define RTE_I2C1_RX_DMA_CHANNEL         7
+#define RTE_I2C1_RX_DMA_PRIORITY        0
+
+//   <e> DMA Tx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <6=>6
+//     <i>  Selects DMA Channel (only Channel 6 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_I2C1_TX_DMA                 0
+#define RTE_I2C1_TX_DMA_NUMBER          1
+#define RTE_I2C1_TX_DMA_CHANNEL         6
+#define RTE_I2C1_TX_DMA_PRIORITY        0
+
+// </e>
+
+
+// <e> I2C2 (Inter-integrated Circuit Interface 2)
+// <i> Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C
+#define RTE_I2C2                        0
+#define RTE_I2C2_AF_REMAP              AFIO_UNAVAILABLE_REMAP
+
+//   <o> I2C2_SCL Pin <0=>PB10
+#define RTE_I2C2_SCL_PORT_ID            0
+#if    (RTE_I2C2_SCL_PORT_ID == 0)
+#define RTE_I2C2_SCL_PORT               GPIOB
+#define RTE_I2C2_SCL_BIT                10
+#else
+#error "Invalid I2C2_SCL Pin Configuration!"
+#endif
+
+//   <o> I2C2_SDA Pin <0=>PB11
+#define RTE_I2C2_SDA_PORT_ID            0
+#if    (RTE_I2C2_SDA_PORT_ID == 0)
+#define RTE_I2C2_SDA_PORT               GPIOB
+#define RTE_I2C2_SDA_BIT                11
+#else
+#error "Invalid I2C2_SCL Pin Configuration!"
+#endif
+
+//   <e> DMA Rx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <5=>5
+//     <i>  Selects DMA Channel (only Channel 5 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_I2C2_RX_DMA                 1
+#define RTE_I2C2_RX_DMA_NUMBER          1
+#define RTE_I2C2_RX_DMA_CHANNEL         5
+#define RTE_I2C2_RX_DMA_PRIORITY        0
+
+//   <e> DMA Tx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <4=>4
+//     <i>  Selects DMA Channel (only Channel 4 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_I2C2_TX_DMA                 1
+#define RTE_I2C2_TX_DMA_NUMBER          1
+#define RTE_I2C2_TX_DMA_CHANNEL         4
+#define RTE_I2C2_TX_DMA_PRIORITY        0
+
+// </e>
+
+
+// <e> SPI1 (Serial Peripheral Interface 1) [Driver_SPI1]
+// <i> Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI
+#define RTE_SPI1                        0
+
+//   <e> SPI1_NSS Pin
+//   <i> Configure Pin if exists
+//   <i> GPIO Pxy (x = A..G, y = 0..15)
+//     <o1> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//     <i>  Selects Port Name
+//     <o2> Bit <0-15>
+//     <i>  Selects Port Bit
+//   </e>
+#define RTE_SPI1_NSS_PIN                1
+#define RTE_SPI1_NSS_PORT               GPIO_PORT(0)
+#define RTE_SPI1_NSS_BIT                4
+
+//   <o> SPI1_SCK Pin <0=>PA5
+#define RTE_SPI1_SCK_PORT_ID_DEF        0
+#if    (RTE_SPI1_SCK_PORT_ID_DEF == 0)
+#define RTE_SPI1_SCK_PORT_DEF           GPIOA
+#define RTE_SPI1_SCK_BIT_DEF            5
+#else
+#error "Invalid SPI1_SCK Pin Configuration!"
+#endif
+
+//   <o> SPI1_MISO Pin <0=>Not Used <1=>PA6
+#define RTE_SPI1_MISO_PORT_ID_DEF       0
+#if    (RTE_SPI1_MISO_PORT_ID_DEF == 0)
+#define RTE_SPI1_MISO_DEF               0
+#elif   (RTE_SPI1_MISO_PORT_ID_DEF == 1)
+#define RTE_SPI1_MISO_DEF               1
+#define RTE_SPI1_MISO_PORT_DEF          GPIOA
+#define RTE_SPI1_MISO_BIT_DEF           6
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+
+//   <o> SPI1_MOSI Pin <0=>Not Used <1=>PA7
+#define RTE_SPI1_MOSI_PORT_ID_DEF       0
+#if    (RTE_SPI1_MOSI_PORT_ID_DEF == 0)
+#define RTE_SPI1_MOSI_DEF               0
+#elif  (RTE_SPI1_MOSI_PORT_ID_DEF == 1)
+#define RTE_SPI1_MOSI_DEF               1
+#define RTE_SPI1_MOSI_PORT_DEF          GPIOA
+#define RTE_SPI1_MOSI_BIT_DEF           7
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+
+//   <e> SPI1 Pin Remap
+//   <i> Enable SPI1 Pin Remapping.
+#define RTE_SPI1_REMAP                  0
+
+//   <o> SPI1_SCK Pin <0=>PB3
+#define RTE_SPI1_SCK_PORT_ID_FULL       0
+#if    (RTE_SPI1_SCK_PORT_ID_FULL == 0)
+#define RTE_SPI1_SCK_PORT_FULL          GPIOB
+#define RTE_SPI1_SCK_BIT_FULL           3
+#else
+#error "Invalid SPI1_SCK Pin Configuration!"
+#endif
+
+//   <o> SPI1_MISO Pin <0=>Not Used <1=>PB4
+#define RTE_SPI1_MISO_PORT_ID_FULL      0
+#if    (RTE_SPI1_MISO_PORT_ID_FULL == 0)
+#define RTE_SPI1_MISO_FULL              0
+#elif  (RTE_SPI1_MISO_PORT_ID_FULL == 1)
+#define RTE_SPI1_MISO_FULL              1
+#define RTE_SPI1_MISO_PORT_FULL         GPIOB
+#define RTE_SPI1_MISO_BIT_FULL          4
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+//   <o> SPI1_MOSI Pin <0=>Not Used <1=>PB5
+#define RTE_SPI1_MOSI_PORT_ID_FULL      0
+#if    (RTE_SPI1_MOSI_PORT_ID_FULL == 0)
+#define RTE_SPI1_MOSI_FULL              0
+#elif  (RTE_SPI1_MOSI_PORT_ID_FULL == 1)
+#define RTE_SPI1_MOSI_FULL              1
+#define RTE_SPI1_MOSI_PORT_FULL         GPIOB
+#define RTE_SPI1_MOSI_BIT_FULL          5
+#else
+#error "Invalid SPI1_MOSI Pin Configuration!"
+#endif
+
+//   </e>
+
+#if    (RTE_SPI1_REMAP)
+#define RTE_SPI1_AF_REMAP               AFIO_SPI1_REMAP
+#define RTE_SPI1_SCK_PORT               RTE_SPI1_SCK_PORT_FULL
+#define RTE_SPI1_SCK_BIT                RTE_SPI1_SCK_BIT_FULL
+#define RTE_SPI1_MISO                   RTE_SPI1_MISO_FULL
+#define RTE_SPI1_MISO_PORT              RTE_SPI1_MISO_PORT_FULL
+#define RTE_SPI1_MISO_BIT               RTE_SPI1_MISO_BIT_FULL
+#define RTE_SPI1_MOSI                   RTE_SPI1_MOSI_FULL
+#define RTE_SPI1_MOSI_PORT              RTE_SPI1_MOSI_PORT_FULL
+#define RTE_SPI1_MOSI_BIT               RTE_SPI1_MOSI_BIT_FULL
+#else 
+#define RTE_SPI1_AF_REMAP               AFIO_SPI1_NO_REMAP
+#define RTE_SPI1_SCK_PORT               RTE_SPI1_SCK_PORT_DEF
+#define RTE_SPI1_SCK_BIT                RTE_SPI1_SCK_BIT_DEF
+#define RTE_SPI1_MISO                   RTE_SPI1_MISO_DEF
+#define RTE_SPI1_MISO_PORT              RTE_SPI1_MISO_PORT_DEF
+#define RTE_SPI1_MISO_BIT               RTE_SPI1_MISO_BIT_DEF
+#define RTE_SPI1_MOSI                   RTE_SPI1_MOSI_DEF
+#define RTE_SPI1_MOSI_PORT              RTE_SPI1_MOSI_PORT_DEF
+#define RTE_SPI1_MOSI_BIT               RTE_SPI1_MOSI_BIT_DEF
+#endif
+
+//   <e> DMA Rx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <2=>2
+//     <i>  Selects DMA Channel (only Channel 2 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_SPI1_RX_DMA                 0
+#define RTE_SPI1_RX_DMA_NUMBER          1
+#define RTE_SPI1_RX_DMA_CHANNEL         2
+#define RTE_SPI1_RX_DMA_PRIORITY        0
+
+//   <e> DMA Tx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <3=>3
+//     <i>  Selects DMA Channel (only Channel 3 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_SPI1_TX_DMA                 0
+#define RTE_SPI1_TX_DMA_NUMBER          1
+#define RTE_SPI1_TX_DMA_CHANNEL         3
+#define RTE_SPI1_TX_DMA_PRIORITY        0
+
+// </e>
+
+
+// <e> SPI2 (Serial Peripheral Interface 2) [Driver_SPI2]
+// <i> Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI
+#define RTE_SPI2                        0
+
+//   <e> SPI2_NSS Pin
+//   <i> Configure Pin if exists
+//   <i> GPIO Pxy (x = A..G, y = 0..15)
+//     <o1> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//     <i>  Selects Port Name
+//     <o2> Bit <0-15>
+//     <i>  Selects Port Bit
+//   </e>
+#define RTE_SPI2_NSS_PIN                1
+#define RTE_SPI2_NSS_PORT               GPIO_PORT(1)
+#define RTE_SPI2_NSS_BIT                12
+
+//   <o> SPI2_SCK Pin <0=>PB13
+#define RTE_SPI2_SCK_PORT_ID            0
+#if    (RTE_SPI2_SCK_PORT_ID == 0)
+#define RTE_SPI2_SCK_PORT               GPIOB
+#define RTE_SPI2_SCK_BIT                13
+#define RTE_SPI2_SCK_REMAP              0
+#else
+#error "Invalid SPI2_SCK Pin Configuration!"
+#endif
+
+//   <o> SPI2_MISO Pin <0=>Not Used <1=>PB14
+#define RTE_SPI2_MISO_PORT_ID           0
+#if    (RTE_SPI2_MISO_PORT_ID == 0)
+#define RTE_SPI2_MISO                   0
+#elif  (RTE_SPI2_MISO_PORT_ID == 1)
+#define RTE_SPI2_MISO                   1
+#define RTE_SPI2_MISO_PORT              GPIOB
+#define RTE_SPI2_MISO_BIT               14
+#define RTE_SPI2_MISO_REMAP             0
+#else
+#error "Invalid SPI2_MISO Pin Configuration!"
+#endif
+
+//   <o> SPI2_MOSI Pin <0=>Not Used <1=>PB15
+#define RTE_SPI2_MOSI_PORT_ID           0
+#if    (RTE_SPI2_MOSI_PORT_ID == 0)
+#define RTE_SPI2_MOSI                   0
+#elif  (RTE_SPI2_MOSI_PORT_ID == 1)
+#define RTE_SPI2_MOSI                   1
+#define RTE_SPI2_MOSI_PORT              GPIOB
+#define RTE_SPI2_MOSI_BIT               15
+#define RTE_SPI2_MOSI_REMAP             0
+#else
+#error "Invalid SPI2_MISO Pin Configuration!"
+#endif
+
+//   <e> DMA Rx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <4=>4
+//     <i>  Selects DMA Channel (only Channel 4 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_SPI2_RX_DMA                 0
+#define RTE_SPI2_RX_DMA_NUMBER          1
+#define RTE_SPI2_RX_DMA_CHANNEL         4
+#define RTE_SPI2_RX_DMA_PRIORITY        0
+
+//   <e> DMA Tx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <5=>5
+//     <i>  Selects DMA Channel (only Channel 5 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_SPI2_TX_DMA                 0
+#define RTE_SPI2_TX_DMA_NUMBER          1
+#define RTE_SPI2_TX_DMA_CHANNEL         5
+#define RTE_SPI2_TX_DMA_PRIORITY        0
+
+// </e>
+
+
+// <e> SPI3 (Serial Peripheral Interface 3) [Driver_SPI3]
+// <i> Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI
+#define RTE_SPI3                        0
+
+//   <e> SPI3_NSS Pin
+//   <i> Configure Pin if exists
+//   <i> GPIO Pxy (x = A..G, y = 0..15)
+//     <o1> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//     <i>  Selects Port Name
+//     <o2> Bit <0-15>
+//     <i>  Selects Port Bit
+//   </e>
+#define RTE_SPI3_NSS_PIN                1
+#define RTE_SPI3_NSS_PORT               GPIO_PORT(0)
+#define RTE_SPI3_NSS_BIT                15
+
+//   <o> SPI3_SCK Pin <0=>PB3
+#define RTE_SPI3_SCK_PORT_ID_DEF        0
+#if    (RTE_SPI3_SCK_PORT_ID_DEF == 0)
+#define RTE_SPI3_SCK_PORT_DEF           GPIOB
+#define RTE_SPI3_SCK_BIT_DEF            3
+#else
+#error "Invalid SPI3_SCK Pin Configuration!"
+#endif
+
+//   <o> SPI3_MISO Pin <0=>Not Used <1=>PB4
+#define RTE_SPI3_MISO_PORT_ID_DEF       0
+#if    (RTE_SPI3_MISO_PORT_ID_DEF == 0)
+#define RTE_SPI3_MISO_DEF               0
+#elif  (RTE_SPI3_MISO_PORT_ID_DEF == 1)
+#define RTE_SPI3_MISO_DEF               1
+#define RTE_SPI3_MISO_PORT_DEF          GPIOB
+#define RTE_SPI3_MISO_BIT_DEF           4
+#else
+#error "Invalid SPI3_MISO Pin Configuration!"
+#endif
+
+//   <o> SPI3_MOSI <0=>Not Used Pin <1=>PB5
+#define RTE_SPI3_MOSI_PORT_ID_DEF       0
+#if    (RTE_SPI3_MOSI_PORT_ID_DEF == 0)
+#define RTE_SPI3_MOSI_DEF               0
+#elif  (RTE_SPI3_MOSI_PORT_ID_DEF == 1)
+#define RTE_SPI3_MOSI_DEF               1
+#define RTE_SPI3_MOSI_PORT_DEF          GPIOB
+#define RTE_SPI3_MOSI_BIT_DEF           5
+#else
+#error "Invalid SPI3_MOSI Pin Configuration!"
+#endif
+
+//   <e> SPI3 Pin Remap
+//   <i> Enable SPI3 Pin Remapping.
+//   <i> SPI 3 Pin Remapping is available only in connectivity line devices!
+#define RTE_SPI3_REMAP                  0
+
+//   <o> SPI3_SCK Pin <0=>PC10
+#define RTE_SPI3_SCK_PORT_ID_FULL       0
+#if    (RTE_SPI3_SCK_PORT_ID_FULL == 0)
+#define RTE_SPI3_SCK_PORT_FULL          GPIOC
+#define RTE_SPI3_SCK_BIT_FULL           10
+#else
+#error "Invalid SPI3_SCK Pin Configuration!"
+#endif
+
+//   <o> SPI3_MISO Pin <0=>Not Used <1=>PC11
+#define RTE_SPI3_MISO_PORT_ID_FULL      0
+#if    (RTE_SPI3_MISO_PORT_ID_FULL == 0)
+#define RTE_SPI3_MISO_FULL              0
+#elif  (RTE_SPI3_MISO_PORT_ID_FULL == 1)
+#define RTE_SPI3_MISO_FULL              1
+#define RTE_SPI3_MISO_PORT_FULL         GPIOC
+#define RTE_SPI3_MISO_BIT_FULL          11
+#else
+#error "Invalid SPI3_MISO Pin Configuration!"
+#endif
+//   <o> SPI3_MOSI Pin <0=>Not Used <1=>PC12
+#define RTE_SPI3_MOSI_PORT_ID_FULL      0
+#if    (RTE_SPI3_MOSI_PORT_ID_FULL == 0)
+#define RTE_SPI3_MOSI_FULL              0
+#elif  (RTE_SPI3_MOSI_PORT_ID_FULL == 1)
+#define RTE_SPI3_MOSI_FULL              1
+#define RTE_SPI3_MOSI_PORT_FULL         GPIOC
+#define RTE_SPI3_MOSI_BIT_FULL          12
+#else
+#error "Invalid SPI3_MOSI Pin Configuration!"
+#endif
+
+//   </e>
+
+#if    (RTE_SPI3_REMAP)
+#define RTE_SPI3_AF_REMAP               AFIO_SPI3_REMAP
+#define RTE_SPI3_SCK_PORT               RTE_SPI3_SCK_PORT_FULL
+#define RTE_SPI3_SCK_BIT                RTE_SPI3_SCK_BIT_FULL
+#define RTE_SPI3_MISO                   RTE_SPI3_MISO_FULL
+#define RTE_SPI3_MISO_PORT              RTE_SPI3_MISO_PORT_FULL
+#define RTE_SPI3_MISO_BIT               RTE_SPI3_MISO_BIT_FULL
+#define RTE_SPI3_MOSI                   RTE_SPI3_MOSI_FULL
+#define RTE_SPI3_MOSI_PORT              RTE_SPI3_MOSI_PORT_FULL
+#define RTE_SPI3_MOSI_BIT               RTE_SPI3_MOSI_BIT_FULL
+#else 
+#define RTE_SPI3_AF_REMAP               AFIO_SPI3_NO_REMAP
+#define RTE_SPI3_SCK_PORT               RTE_SPI3_SCK_PORT_DEF
+#define RTE_SPI3_SCK_BIT                RTE_SPI3_SCK_BIT_DEF
+#define RTE_SPI3_MISO                   RTE_SPI3_MISO_DEF
+#define RTE_SPI3_MISO_PORT              RTE_SPI3_MISO_PORT_DEF
+#define RTE_SPI3_MISO_BIT               RTE_SPI3_MISO_BIT_DEF
+#define RTE_SPI3_MOSI                   RTE_SPI3_MOSI_DEF
+#define RTE_SPI3_MOSI_PORT              RTE_SPI3_MOSI_PORT_DEF
+#define RTE_SPI3_MOSI_BIT               RTE_SPI3_MOSI_BIT_DEF
+#endif
+
+//   <e> DMA Rx
+//     <o1> Number <2=>2
+//     <i>  Selects DMA Number (only DMA2 can be used)
+//     <o2> Channel <1=>1
+//     <i>  Selects DMA Channel (only Channel 1 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_SPI3_RX_DMA                 0
+#define RTE_SPI3_RX_DMA_NUMBER          2
+#define RTE_SPI3_RX_DMA_CHANNEL         1
+#define RTE_SPI3_RX_DMA_PRIORITY        0
+
+//   <e> DMA Tx
+//     <o1> Number <2=>2
+//     <i>  Selects DMA Number (only DMA2 can be used)
+//     <o2> Channel <2=>2
+//     <i>  Selects DMA Channel (only Channel 2 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_SPI3_TX_DMA                 0
+#define RTE_SPI3_TX_DMA_NUMBER          2
+#define RTE_SPI3_TX_DMA_CHANNEL         2
+#define RTE_SPI3_TX_DMA_PRIORITY        0
+
+// </e>
+
+
+// <e> SDIO (Secure Digital Input/Output) [Driver_MCI0]
+// <i> Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI
+#define RTE_SDIO                        0
+
+//   <h> SDIO Peripheral Bus
+//     <o> SDIO_CK Pin <0=>PC12
+#define   RTE_SDIO_CK_PORT_ID           0
+#if      (RTE_SDIO_CK_PORT_ID == 0)
+  #define RTE_SDIO_CK_PORT              GPIOC
+  #define RTE_SDIO_CK_PIN               12
+#else
+  #error "Invalid SDIO_CLK Pin Configuration!"
+#endif
+//     <o> SDIO_CMD Pin <0=>PD2
+#define   RTE_SDIO_CMD_PORT_ID          0
+#if      (RTE_SDIO_CMD_PORT_ID == 0)
+  #define RTE_SDIO_CMD_PORT             GPIOD
+  #define RTE_SDIO_CMD_PIN              2
+#else
+  #error "Invalid SDIO_CMD Pin Configuration!"
+#endif
+//     <o> SDIO_D0 Pin <0=>PC8
+#define   RTE_SDIO_D0_PORT_ID           0
+#if      (RTE_SDIO_D0_PORT_ID == 0)
+  #define RTE_SDIO_D0_PORT              GPIOC
+  #define RTE_SDIO_D0_PIN               8
+#else
+  #error "Invalid SDIO_DAT0 Pin Configuration!"
+#endif
+//     <e> SDIO_D[1 .. 3]
+#define   RTE_SDIO_BUS_WIDTH_4          1
+//       <o> SDIO_D1 Pin <0=>PC9
+#define   RTE_SDIO_D1_PORT_ID           0
+#if      (RTE_SDIO_D1_PORT_ID == 0)
+  #define RTE_SDIO_D1_PORT              GPIOC
+  #define RTE_SDIO_D1_PIN               9
+#else
+  #error "Invalid SDIO_D1 Pin Configuration!"
+#endif
+//       <o> SDIO_D2 Pin <0=>PC10
+#define   RTE_SDIO_D2_PORT_ID           0
+#if      (RTE_SDIO_D2_PORT_ID == 0)
+  #define RTE_SDIO_D2_PORT              GPIOC
+  #define RTE_SDIO_D2_PIN               10
+#else
+  #error "Invalid SDIO_D2 Pin Configuration!"
+#endif
+//       <o> SDIO_D3 Pin <0=>PC11
+#define   RTE_SDIO_D3_PORT_ID           0
+#if      (RTE_SDIO_D3_PORT_ID == 0)
+  #define RTE_SDIO_D3_PORT              GPIOC
+  #define RTE_SDIO_D3_PIN               11
+#else
+  #error "Invalid SDIO_D3 Pin Configuration!"
+#endif
+//     </e> SDIO_D[1 .. 3]
+//     <e> SDIO_D[4 .. 7]
+#define   RTE_SDIO_BUS_WIDTH_8          0
+//       <o> SDIO_D4 Pin <0=>PB8
+#define   RTE_SDIO_D4_PORT_ID           0
+#if      (RTE_SDIO_D4_PORT_ID == 0)
+  #define RTE_SDIO_D4_PORT              GPIOB
+  #define RTE_SDIO_D4_PIN               8
+#else
+  #error "Invalid SDIO_D4 Pin Configuration!"
+#endif
+//       <o> SDIO_D5 Pin <0=>PB9
+#define   RTE_SDIO_D5_PORT_ID           0
+#if      (RTE_SDIO_D5_PORT_ID == 0)
+  #define RTE_SDIO_D5_PORT              GPIOB
+  #define RTE_SDIO_D5_PIN               9
+#else
+  #error "Invalid SDIO_D5 Pin Configuration!"
+#endif
+//       <o> SDIO_D6 Pin <0=>PC6
+#define   RTE_SDIO_D6_PORT_ID           0
+#if      (RTE_SDIO_D6_PORT_ID == 0)
+  #define RTE_SDIO_D6_PORT              GPIOC
+  #define RTE_SDIO_D6_PIN               6
+#else
+  #error "Invalid SDIO_D6 Pin Configuration!"
+#endif
+//       <o> SDIO_D7 Pin <0=>PC7
+#define   RTE_SDIO_D7_PORT_ID           0
+#if      (RTE_SDIO_D7_PORT_ID == 0)
+  #define RTE_SDIO_D7_PORT              GPIOC
+  #define RTE_SDIO_D7_PIN               7
+#else
+  #error "Invalid SDIO_D7 Pin Configuration!"
+#endif
+//     </e> SDIO_D[4 .. 7]
+//   </h> SDIO Peripheral Bus
+
+//   <e> Card Detect Pin
+//   <i> Configure Pin if exists
+//   <i> GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//     <o1> Active State <0=>Low <1=>High
+//     <i>  Selects Active State Logical Level
+//     <o2> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//     <i>  Selects Port Name
+//     <o3> Bit <0-15>
+//     <i>  Selects Port Bit
+//   </e>
+#define RTE_SDIO_CD_EN                  1
+#define RTE_SDIO_CD_ACTIVE              0
+#define RTE_SDIO_CD_PORT                GPIO_PORT(5)
+#define RTE_SDIO_CD_PIN                 11
+
+//   <e> Write Protect Pin
+//   <i> Configure Pin if exists
+//   <i> GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//     <o1> Active State <0=>Low <1=>High
+//     <i>  Selects Active State Logical Level
+//     <o2> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//     <i>  Selects Port Name
+//     <o3> Bit <0-15>
+//     <i>  Selects Port Bit
+//   </e>
+#define RTE_SDIO_WP_EN                  0
+#define RTE_SDIO_WP_ACTIVE              1
+#define RTE_SDIO_WP_PORT                GPIO_PORT(0)
+#define RTE_SDIO_WP_PIN                 10
+
+//   <h> DMA
+//     <o0> Number <2=>2
+//     <i>  Selects DMA Number (only DMA2 can be used)
+//     <o1> Channel <4=>4
+//     <i>  Selects DMA Channel (only Channel 4 can be used)
+//     <o2> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </h>
+#define RTE_SDIO_DMA_NUMBER             2
+#define RTE_SDIO_DMA_CHANNEL            4
+#define RTE_SDIO_DMA_PRIORITY           0
+
+// </e>
+
+
+// <e> CAN1 (Controller Area Network 1) [Driver_CAN1]
+// <i> Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN
+#define RTE_CAN1                        0
+
+//   <o> CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0
+#define RTE_CAN1_RX_PORT_ID             0
+#if    (RTE_CAN1_RX_PORT_ID == 0)
+#define RTE_CAN1_RX_PORT                GPIOA
+#define RTE_CAN1_RX_BIT                 11
+#elif  (RTE_CAN1_RX_PORT_ID == 1)
+#define RTE_CAN1_RX_PORT                GPIOB
+#define RTE_CAN1_RX_BIT                 8
+#elif  (RTE_CAN1_RX_PORT_ID == 2)
+#define RTE_CAN1_RX_PORT                GPIOD
+#define RTE_CAN1_RX_BIT                 0
+#else
+#error "Invalid CAN1_RX Pin Configuration!"
+#endif
+
+//   <o> CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1
+#define RTE_CAN1_TX_PORT_ID             0
+#if    (RTE_CAN1_TX_PORT_ID == 0)
+#define RTE_CAN1_TX_PORT                GPIOA
+#define RTE_CAN1_TX_BIT                 12
+#elif  (RTE_CAN1_TX_PORT_ID == 1)
+#define RTE_CAN1_TX_PORT                GPIOB
+#define RTE_CAN1_TX_BIT                 9
+#elif  (RTE_CAN1_TX_PORT_ID == 2)
+#define RTE_CAN1_TX_PORT                GPIOD
+#define RTE_CAN1_TX_BIT                 1
+#else
+#error "Invalid CAN1_TX Pin Configuration!"
+#endif
+
+// </e>
+
+
+// <e> CAN2 (Controller Area Network 2) [Driver_CAN2]
+// <i> Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN
+#define RTE_CAN2                        0
+
+//   <o> CAN2_RX Pin <0=>PB5 <1=>PB12
+#define RTE_CAN2_RX_PORT_ID             0
+#if    (RTE_CAN2_RX_PORT_ID == 0)
+#define RTE_CAN2_RX_PORT                GPIOB
+#define RTE_CAN2_RX_BIT                 5
+#elif  (RTE_CAN2_RX_PORT_ID == 1)
+#define RTE_CAN2_RX_PORT                GPIOB
+#define RTE_CAN2_RX_BIT                 12
+#else
+#error "Invalid CAN2_RX Pin Configuration!"
+#endif
+
+//   <o> CAN2_TX Pin <0=>PB6 <1=>PB13
+#define RTE_CAN2_TX_PORT_ID             0
+#if    (RTE_CAN2_TX_PORT_ID == 0)
+#define RTE_CAN2_TX_PORT                GPIOB
+#define RTE_CAN2_TX_BIT                 6
+#elif  (RTE_CAN2_TX_PORT_ID == 1)
+#define RTE_CAN2_TX_PORT                GPIOB
+#define RTE_CAN2_TX_BIT                 13
+#else
+#error "Invalid CAN2_TX Pin Configuration!"
+#endif
+
+// </e>
+
+
+// <e> ETH (Ethernet Interface) [Driver_ETH_MAC0]
+// <i> Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC
+#define RTE_ETH                         0
+
+//   <e> MII (Media Independent Interface)
+//   <i> Enable Media Independent Interface pin configuration
+#define RTE_ETH_MII                     0
+
+//     <o> ETH_MII_TX_CLK Pin <0=>PC3
+#define RTE_ETH_MII_TX_CLK_PORT_ID      0
+#if    (RTE_ETH_MII_TX_CLK_PORT_ID == 0)
+#define RTE_ETH_MII_TX_CLK_PORT         GPIOC
+#define RTE_ETH_MII_TX_CLK_PIN          3
+#else
+#error "Invalid ETH_MII_TX_CLK Pin Configuration!"
+#endif
+//     <o> ETH_MII_TXD0 Pin <0=>PB12
+#define RTE_ETH_MII_TXD0_PORT_ID        0
+#if    (RTE_ETH_MII_TXD0_PORT_ID == 0)
+#define RTE_ETH_MII_TXD0_PORT           GPIOB
+#define RTE_ETH_MII_TXD0_PIN            12
+#else
+#error "Invalid ETH_MII_TXD0 Pin Configuration!"
+#endif
+//     <o> ETH_MII_TXD1 Pin <0=>PB13
+#define RTE_ETH_MII_TXD1_PORT_ID        0
+#if    (RTE_ETH_MII_TXD1_PORT_ID == 0)
+#define RTE_ETH_MII_TXD1_PORT           GPIOB
+#define RTE_ETH_MII_TXD1_PIN            13
+#else
+#error "Invalid ETH_MII_TXD1 Pin Configuration!"
+#endif
+//     <o> ETH_MII_TXD2 Pin <0=>PC2
+#define RTE_ETH_MII_TXD2_PORT_ID        0
+#if    (RTE_ETH_MII_TXD2_PORT_ID == 0)
+#define RTE_ETH_MII_TXD2_PORT           GPIOC
+#define RTE_ETH_MII_TXD2_PIN            2
+#else
+#error "Invalid ETH_MII_TXD2 Pin Configuration!"
+#endif
+//     <o> ETH_MII_TXD3 Pin <0=>PB8
+#define RTE_ETH_MII_TXD3_PORT_ID        0
+#if    (RTE_ETH_MII_TXD3_PORT_ID == 0)
+#define RTE_ETH_MII_TXD3_PORT           GPIOB
+#define RTE_ETH_MII_TXD3_PIN            8
+#else
+#error "Invalid ETH_MII_TXD3 Pin Configuration!"
+#endif
+//     <o> ETH_MII_TX_EN Pin <0=>PB11
+#define RTE_ETH_MII_TX_EN_PORT_ID       0
+#if    (RTE_ETH_MII_TX_EN_PORT_ID == 0)
+#define RTE_ETH_MII_TX_EN_PORT          GPIOB
+#define RTE_ETH_MII_TX_EN_PIN           11
+#else
+#error "Invalid ETH_MII_TX_EN Pin Configuration!"
+#endif
+//     <o> ETH_MII_RX_CLK Pin <0=>PA1
+#define RTE_ETH_MII_RX_CLK_PORT_ID        0
+#if    (RTE_ETH_MII_RX_CLK_PORT_ID == 0)
+#define RTE_ETH_MII_RX_CLK_PORT         GPIOA
+#define RTE_ETH_MII_RX_CLK_PIN          1
+#else
+#error "Invalid ETH_MII_RX_CLK Pin Configuration!"
+#endif
+//     <o> ETH_MII_RXD0 Pin <0=>PC4
+#define RTE_ETH_MII_RXD0_DEF            0
+
+//     <o> ETH_MII_RXD1 Pin <0=>PC5
+#define RTE_ETH_MII_RXD1_DEF            0
+
+//     <o> ETH_MII_RXD2 Pin <0=>PB0
+#define RTE_ETH_MII_RXD2_DEF            0
+
+//     <o> ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12
+#define RTE_ETH_MII_RXD3_DEF            0
+
+//     <o> ETH_MII_RX_DV Pin <0=>PA7
+#define RTE_ETH_MII_RX_DV_DEF           0
+
+//     <o> ETH_MII_RX_ER Pin <0=>PB10
+#define RTE_ETH_MII_RX_ER_PORT_ID       0
+#if    (RTE_ETH_MII_RX_ER_PORT_ID == 0)
+#define RTE_ETH_MII_RX_ER_PORT          GPIOB
+#define RTE_ETH_MII_RX_ER_PIN           10
+#else
+#error "Invalid ETH_MII_RX_ER Pin Configuration!"
+#endif
+//     <o> ETH_MII_CRS Pin <0=>PA0
+#define RTE_ETH_MII_CRS_PORT_ID       0
+#if    (RTE_ETH_MII_CRS_PORT_ID == 0)
+#define RTE_ETH_MII_CRS_PORT            GPIOA
+#define RTE_ETH_MII_CRS_PIN             0
+#else
+#error "Invalid ETH_MII_CRS Pin Configuration!"
+#endif
+//     <o> ETH_MII_COL Pin <0=>PA3
+#define RTE_ETH_MII_COL_PORT_ID       0
+#if    (RTE_ETH_MII_COL_PORT_ID == 0)
+#define RTE_ETH_MII_COL_PORT            GPIOA
+#define RTE_ETH_MII_COL_PIN             3
+#else
+#error "Invalid ETH_MII_COL Pin Configuration!"
+#endif
+
+//     <e> Ethernet MAC I/O remapping
+//     <i> Remap Ethernet pins
+#define RTE_ETH_MII_REMAP               0
+
+//     <o> ETH_MII_RXD0 Pin <1=>PD9
+#define RTE_ETH_MII_RXD0_REMAP          1
+
+//     <o> ETH_MII_RXD1 Pin <1=>PD10
+#define RTE_ETH_MII_RXD1_REMAP          1
+
+//     <o> ETH_MII_RXD2 Pin <1=>PD11
+#define RTE_ETH_MII_RXD2_REMAP          1
+
+//       <o> ETH_MII_RXD3 Pin <1=>PD12
+#define RTE_ETH_MII_RXD3_REMAP          1
+
+//       <o> ETH_MII_RX_DV Pin <1=>PD8
+#define RTE_ETH_MII_RX_DV_REMAP         1
+//     </e>
+
+//   </e>
+
+#if    ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0))
+#define RTE_ETH_MII_RXD0_PORT           GPIOC
+#define RTE_ETH_MII_RXD0_PIN            4
+#elif  ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1))
+#define RTE_ETH_MII_RXD0_PORT           GPIOD
+#define RTE_ETH_MII_RXD0_PIN            9
+#else
+#error "Invalid ETH_MII_RXD0 Pin Configuration!"
+#endif
+
+#if   ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0))
+#define RTE_ETH_MII_RXD1_PORT           GPIOC
+#define RTE_ETH_MII_RXD1_PIN            5
+#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1))
+#define RTE_ETH_MII_RXD1_PORT           GPIOD
+#define RTE_ETH_MII_RXD1_PIN            10
+#else
+#error "Invalid ETH_MII_RXD1 Pin Configuration!"
+#endif
+
+#if   ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0))
+#define RTE_ETH_MII_RXD2_PORT           GPIOB
+#define RTE_ETH_MII_RXD2_PIN            0
+#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1))
+#define RTE_ETH_MII_RXD2_PORT           GPIOD
+#define RTE_ETH_MII_RXD2_PIN            11
+#else
+#error "Invalid ETH_MII_RXD2 Pin Configuration!"
+#endif
+
+#if   ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0))
+#define RTE_ETH_MII_RXD3_PORT           GPIOB
+#define RTE_ETH_MII_RXD3_PIN            1
+#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1))
+#define RTE_ETH_MII_RXD3_PORT           GPIOD
+#define RTE_ETH_MII_RXD3_PIN            12
+#else
+#error "Invalid ETH_MII_RXD3 Pin Configuration!"
+#endif
+
+#if   ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0))
+#define RTE_ETH_MII_RX_DV_PORT          GPIOA
+#define RTE_ETH_MII_RX_DV_PIN           7
+#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1))
+#define RTE_ETH_MII_RX_DV_PORT          GPIOD
+#define RTE_ETH_MII_RX_DV_PIN           8
+#else
+#error "Invalid ETH_MII_RX_DV Pin Configuration!"
+#endif
+
+//   <e> RMII (Reduced Media Independent Interface)
+#define RTE_ETH_RMII                    0
+
+//     <o> ETH_RMII_TXD0 Pin <0=>PB12
+#define RTE_ETH_RMII_TXD0_PORT_ID       0
+#if    (RTE_ETH_RMII_TXD0_PORT_ID == 0)
+#define RTE_ETH_RMII_TXD0_PORT          GPIOB
+#define RTE_ETH_RMII_TXD0_PIN           12
+#else
+#error "Invalid ETH_RMII_TXD0 Pin Configuration!"
+#endif
+//     <o> ETH_RMII_TXD1 Pin <0=>PB13
+#define RTE_ETH_RMII_TXD1_PORT_ID       0
+#if    (RTE_ETH_RMII_TXD1_PORT_ID == 0)
+#define RTE_ETH_RMII_TXD1_PORT          GPIOB
+#define RTE_ETH_RMII_TXD1_PIN           13
+#else
+#error "Invalid ETH_RMII_TXD1 Pin Configuration!"
+#endif
+//     <o> ETH_RMII_TX_EN Pin <0=>PB11
+#define RTE_ETH_RMII_TX_EN_PORT_ID      0
+#if    (RTE_ETH_RMII_TX_EN_PORT_ID == 0)
+#define RTE_ETH_RMII_TX_EN_PORT         GPIOB
+#define RTE_ETH_RMII_TX_EN_PIN          11
+#else
+#error "Invalid ETH_RMII_TX_EN Pin Configuration!"
+#endif
+//     <o> ETH_RMII_RXD0 Pin <0=>PC4
+#define RTE_ETH_RMII_RXD0_DEF           0
+
+//     <o> ETH_RMII_RXD1 Pin <0=>PC5
+#define RTE_ETH_RMII_RXD1_DEF           0
+
+//     <o> ETH_RMII_REF_CLK Pin <0=>PA1
+#define RTE_ETH_RMII_REF_CLK_PORT_ID    0
+#if    (RTE_ETH_RMII_REF_CLK_PORT_ID == 0)
+#define RTE_ETH_RMII_REF_CLK_PORT       GPIOA
+#define RTE_ETH_RMII_REF_CLK_PIN        1
+#else
+#error "Invalid ETH_RMII_REF_CLK Pin Configuration!"
+#endif
+//     <o> ETH_RMII_CRS_DV Pin <0=>PA7
+#define RTE_ETH_RMII_CRS_DV_DEF     0
+
+//   <e> Ethernet MAC I/O remapping
+//   <i> Remap Ethernet pins
+#define RTE_ETH_RMII_REMAP              0
+//     <o> ETH_RMII_RXD0 Pin <1=>PD9
+#define RTE_ETH_RMII_RXD0_REMAP         1
+
+//     <o> ETH_RMII_RXD1 Pin <1=>PD10
+#define RTE_ETH_RMII_RXD1_REMAP         1
+
+//     <o> ETH_RMII_CRS_DV Pin <1=>PD8
+#define RTE_ETH_RMII_CRS_DV_REMAP       1
+//   </e>
+
+#if    ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0))
+#define RTE_ETH_RMII_RXD0_PORT          GPIOC
+#define RTE_ETH_RMII_RXD0_PIN           4
+#elif  ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1))
+#define RTE_ETH_RMII_RXD0_PORT          GPIOD
+#define RTE_ETH_RMII_RXD0_PIN           9
+#else
+#error "Invalid ETH_RMII_RXD0 Pin Configuration!"
+#endif
+
+#if    ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0))
+#define RTE_ETH_RMII_RXD1_PORT          GPIOC
+#define RTE_ETH_RMII_RXD1_PIN           5
+#elif  ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1))
+#define RTE_ETH_RMII_RXD1_PORT          GPIOD
+#define RTE_ETH_RMII_RXD1_PIN           10
+#else
+#error "Invalid ETH_RMII_RXD1 Pin Configuration!"
+#endif
+
+#if    ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0))
+#define RTE_ETH_RMII_CRS_DV_PORT        GPIOA
+#define RTE_ETH_RMII_CRS_DV_PIN         7
+#elif  ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1))
+#define RTE_ETH_RMII_CRS_DV_PORT        GPIOD
+#define RTE_ETH_RMII_CRS_DV_PIN         8
+#else
+#error "Invalid ETH_RMII_CRS_DV Pin Configuration!"
+#endif
+
+//   </e>
+
+//   <h> Management Data Interface
+//     <o> ETH_MDC Pin <0=>PC1
+#define RTE_ETH_MDI_MDC_PORT_ID         0
+#if    (RTE_ETH_MDI_MDC_PORT_ID == 0)
+#define RTE_ETH_MDI_MDC_PORT            GPIOC
+#define RTE_ETH_MDI_MDC_PIN             1
+#else
+#error "Invalid ETH_MDC Pin Configuration!"
+#endif
+//     <o> ETH_MDIO Pin <0=>PA2
+#define RTE_ETH_MDI_MDIO_PORT_ID        0
+#if    (RTE_ETH_MDI_MDIO_PORT_ID == 0)
+#define RTE_ETH_MDI_MDIO_PORT           GPIOA
+#define RTE_ETH_MDI_MDIO_PIN            2
+#else
+#error "Invalid ETH_MDIO Pin Configuration!"
+#endif
+//   </h>
+
+//   <o> Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled
+#define RTE_ETH_REF_CLOCK_ID            0
+#if    (RTE_ETH_REF_CLOCK_ID == 0)
+#define RTE_ETH_REF_CLOCK               0
+#elif  (RTE_ETH_REF_CLOCK_ID == 1)
+#define RTE_ETH_REF_CLOCK               1
+#else
+#error "Invalid MCO Ethernet Reference Clock Configuration!"
+#endif
+// </e>
+
+
+// <e> USB Device Full-speed
+// <i> Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
+#define RTE_USB_DEVICE                  0
+
+//     <e> CON On/Off Pin
+//     <i> Configure Pin for driving D+ pull-up
+//     <i> GPIO Pxy (x = A..G, y = 0..15)
+//       <o1> Active State <0=>Low <1=>High
+//       <i>  Selects Active State Logical Level
+//       <o2> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//       <i>  Selects Port Name
+//       <o3> Bit <0-15>
+//       <i>  Selects Port Bit
+//     </e>
+#define RTE_USB_DEVICE_CON_PIN          1
+#define RTE_USB_DEVICE_CON_ACTIVE       0
+#define RTE_USB_DEVICE_CON_PORT         GPIO_PORT(1)
+#define RTE_USB_DEVICE_CON_BIT          14
+
+//   </e>
+
+
+// <e> USB OTG Full-speed
+#define RTE_USB_OTG_FS                  0
+
+//   <e> Host [Driver_USBH0]
+//   <i> Configuration settings for Driver_USBH0 in component ::Drivers:USB Host
+
+#define RTE_USB_OTG_FS_HOST             0
+
+//     <e> VBUS Power On/Off Pin
+//     <i> Configure Pin for driving VBUS
+//     <i> GPIO Pxy (x = A..G, y = 0..15)
+//       <o1> Active State <0=>Low <1=>High
+//       <i>  Selects Active State Logical Level
+//       <o2> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//       <i>  Selects Port Name
+//       <o3> Bit <0-15>
+//       <i>  Selects Port Bit
+//     </e>
+#define RTE_OTG_FS_VBUS_PIN             1
+#define RTE_OTG_FS_VBUS_ACTIVE          0
+#define RTE_OTG_FS_VBUS_PORT            GPIO_PORT(2)
+#define RTE_OTG_FS_VBUS_BIT             9
+
+//     <e> Overcurrent Detection Pin
+//     <i> Configure Pin for overcurrent detection
+//     <i> GPIO Pxy (x = A..G, y = 0..15)
+//       <o1> Active State <0=>Low <1=>High
+//       <i>  Selects Active State Logical Level
+//       <o2> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//       <i>  Selects Port Name
+//       <o3> Bit <0-15>
+//       <i>  Selects Port Bit
+//     </e>
+#define RTE_OTG_FS_OC_PIN               1
+#define RTE_OTG_FS_OC_ACTIVE            0
+#define RTE_OTG_FS_OC_PORT              GPIO_PORT(4)
+#define RTE_OTG_FS_OC_BIT               1
+//   </e>
+
+// </e>
+
+
+#endif  /* __RTE_DEVICE_H */
diff --git a/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.update@1.0.1 b/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.update@1.0.1
new file mode 100644
index 0000000..1ab7096
--- /dev/null
+++ b/RTE/Device/STM32F103RB/startup_stm32f10x_md.s.update@1.0.1
@@ -0,0 +1,308 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f10x_md.s
+;* Author             : MCD Application Team
+;* Version            : V3.5.1
+;* Date               : 08-September-2021
+;* Description        : STM32F10x Medium Density Devices vector table for MDK-ARM 
+;*                      toolchain.  
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+;*
+;* Copyright (c) 2011 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler            ; Window Watchdog
+                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler          ; Tamper
+                DCD     RTC_IRQHandler             ; RTC
+                DCD     FLASH_IRQHandler           ; Flash
+                DCD     RCC_IRQHandler             ; RCC
+                DCD     EXTI0_IRQHandler           ; EXTI Line 0
+                DCD     EXTI1_IRQHandler           ; EXTI Line 1
+                DCD     EXTI2_IRQHandler           ; EXTI Line 2
+                DCD     EXTI3_IRQHandler           ; EXTI Line 3
+                DCD     EXTI4_IRQHandler           ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler          ; ADC1_2
+                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
+                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
+                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
+                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
+                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler            ; TIM2
+                DCD     TIM3_IRQHandler            ; TIM3
+                DCD     TIM4_IRQHandler            ; TIM4
+                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
+                DCD     SPI1_IRQHandler            ; SPI1
+                DCD     SPI2_IRQHandler            ; SPI2
+                DCD     USART1_IRQHandler          ; USART1
+                DCD     USART2_IRQHandler          ; USART2
+                DCD     USART3_IRQHandler          ; USART3
+                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
+                DCD     RTCAlarm_IRQHandler        ; RTC Alarm through EXTI Line
+                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+     IMPORT  __main
+     IMPORT  SystemInit
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler            [WEAK]
+                EXPORT  PVD_IRQHandler             [WEAK]
+                EXPORT  TAMPER_IRQHandler          [WEAK]
+                EXPORT  RTC_IRQHandler             [WEAK]
+                EXPORT  FLASH_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler             [WEAK]
+                EXPORT  EXTI0_IRQHandler           [WEAK]
+                EXPORT  EXTI1_IRQHandler           [WEAK]
+                EXPORT  EXTI2_IRQHandler           [WEAK]
+                EXPORT  EXTI3_IRQHandler           [WEAK]
+                EXPORT  EXTI4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
+                EXPORT  ADC1_2_IRQHandler          [WEAK]
+                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
+                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
+                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
+                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
+                EXPORT  EXTI9_5_IRQHandler         [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
+                EXPORT  TIM1_UP_IRQHandler         [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
+                EXPORT  TIM1_CC_IRQHandler         [WEAK]
+                EXPORT  TIM2_IRQHandler            [WEAK]
+                EXPORT  TIM3_IRQHandler            [WEAK]
+                EXPORT  TIM4_IRQHandler            [WEAK]
+                EXPORT  I2C1_EV_IRQHandler         [WEAK]
+                EXPORT  I2C1_ER_IRQHandler         [WEAK]
+                EXPORT  I2C2_EV_IRQHandler         [WEAK]
+                EXPORT  I2C2_ER_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler            [WEAK]
+                EXPORT  SPI2_IRQHandler            [WEAK]
+                EXPORT  USART1_IRQHandler          [WEAK]
+                EXPORT  USART2_IRQHandler          [WEAK]
+                EXPORT  USART3_IRQHandler          [WEAK]
+                EXPORT  EXTI15_10_IRQHandler       [WEAK]
+                EXPORT  RTCAlarm_IRQHandler        [WEAK]
+                EXPORT  USBWakeUp_IRQHandler       [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN1_TX_IRQHandler
+USB_LP_CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB           
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
diff --git a/RTE/Device/STM32F103RB/system_stm32f10x.c.update@1.0.1 b/RTE/Device/STM32F103RB/system_stm32f10x.c.update@1.0.1
new file mode 100644
index 0000000..9e31f67
--- /dev/null
+++ b/RTE/Device/STM32F103RB/system_stm32f10x.c.update@1.0.1
@@ -0,0 +1,1092 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V3.5.1
+  * @date    08-September-2021
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2011 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depending on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef  STM32F10X_CL
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18;
+      
+      if (pllmull != 0x0D)
+      {
+         pllmull += 2;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13 / 2; 
+      }
+            
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        
+        if (prediv1source == 0)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *         and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+    if (HSE_VALUE <= 24000000)
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+	}
+	else
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+	}
+#endif /* STM32F10X_CL */
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }   
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+
+	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+#else    
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL7); 
+#else     
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
diff --git a/RTE/Device/STM32F107VC/RTE_Device.h.base@1.1.2 b/RTE/Device/STM32F107VC/RTE_Device.h.base@1.1.2
new file mode 100644
index 0000000..0d10ed8
--- /dev/null
+++ b/RTE/Device/STM32F107VC/RTE_Device.h.base@1.1.2
@@ -0,0 +1,1828 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013-2016 Arm Limited (or its affiliates). All 
+ * rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * $Date:        09. September 2016
+ * $Revision:    V1.1.2
+ *
+ * Project:      RTE Device Configuration for STMicroelectronics STM32F1xx
+ *
+ * -------------------------------------------------------------------------- */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+
+#define GPIO_PORT(num) \
+ ((num == 0) ? GPIOA : \
+  (num == 1) ? GPIOB : \
+  (num == 2) ? GPIOC : \
+  (num == 3) ? GPIOD : \
+  (num == 4) ? GPIOE : \
+  (num == 5) ? GPIOF : \
+  (num == 6) ? GPIOG : \
+  NULL)
+
+
+// <h> Clock Configuration
+//   <o> High-speed Internal Clock <1-999999999>
+#define RTE_HSI                         8000000
+//   <o> High-speed External Clock <1-999999999>
+#define RTE_HSE                         25000000
+//   <o> System Clock <1-999999999>
+#define RTE_SYSCLK                      72000000
+//   <o> HCLK Clock   <1-999999999>
+#define RTE_HCLK                        72000000
+//   <o> APB1 Clock   <1-999999999>
+#define RTE_PCLK1                       36000000
+//   <o> APB2 Clock   <1-999999999>
+#define RTE_PCLK2                       72000000
+//   <o> ADC Clock    <1-999999999>
+#define RTE_ADCCLK                      36000000
+//       USB Clock
+#define RTE_USBCLK                      48000000
+// </h>
+
+
+// <e> USART1 (Universal synchronous asynchronous receiver transmitter)
+// <i> Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART
+#define RTE_USART1                       0
+
+//   <o> USART1_TX Pin <0=>Not Used <1=>PA9
+#define RTE_USART1_TX_PORT_ID_DEF       0
+#if    (RTE_USART1_TX_PORT_ID_DEF == 0)
+#define RTE_USART1_TX_DEF               0
+#elif  (RTE_USART1_TX_PORT_ID_DEF == 1)
+#define RTE_USART1_TX_DEF               1
+#define RTE_USART1_TX_PORT_DEF          GPIOA
+#define RTE_USART1_TX_BIT_DEF           9
+#else
+#error "Invalid USART1_TX Pin Configuration!"
+#endif
+
+//   <o> USART1_RX Pin <0=>Not Used <1=>PA10
+#define RTE_USART1_RX_PORT_ID_DEF       0
+#if    (RTE_USART1_RX_PORT_ID_DEF == 0)
+#define RTE_USART1_RX_DEF               0
+#elif  (RTE_USART1_RX_PORT_ID_DEF == 1)
+#define RTE_USART1_RX_DEF               1
+#define RTE_USART1_RX_PORT_DEF          GPIOA
+#define RTE_USART1_RX_BIT_DEF           10
+#else
+#error "Invalid USART1_RX Pin Configuration!"
+#endif
+
+//   <o> USART1_CK Pin <0=>Not Used <1=>PA8
+#define RTE_USART1_CK_PORT_ID_DEF       0
+#if    (RTE_USART1_CK_PORT_ID_DEF == 0)
+#define RTE_USART1_CK                   0
+#elif  (RTE_USART1_CK_PORT_ID_DEF == 1)
+#define RTE_USART1_CK                   1
+#define RTE_USART1_CK_PORT_DEF          GPIOA
+#define RTE_USART1_CK_BIT_DEF           8
+#else
+#error "Invalid USART1_CK Pin Configuration!"
+#endif
+
+//   <o> USART1_CTS Pin <0=>Not Used <1=>PA11
+#define RTE_USART1_CTS_PORT_ID_DEF      0
+#if    (RTE_USART1_CTS_PORT_ID_DEF == 0)
+#define RTE_USART1_CTS                  0
+#elif  (RTE_USART1_CTS_PORT_ID_DEF == 1)
+#define RTE_USART1_CTS                  1
+#define RTE_USART1_CTS_PORT_DEF         GPIOA
+#define RTE_USART1_CTS_BIT_DEF          11
+#else
+#error "Invalid USART1_CTS Pin Configuration!"
+#endif
+
+//   <o> USART1_RTS Pin <0=>Not Used <1=>PA12
+#define RTE_USART1_RTS_PORT_ID_DEF      0
+#if    (RTE_USART1_RTS_PORT_ID_DEF == 0)
+#define RTE_USART1_RTS                  0
+#elif  (RTE_USART1_RTS_PORT_ID_DEF == 1)
+#define RTE_USART1_RTS                  1
+#define RTE_USART1_RTS_PORT_DEF         GPIOA
+#define RTE_USART1_RTS_BIT_DEF          12
+#else
+#error "Invalid USART1_RTS Pin Configuration!"
+#endif
+
+//   <e> USART1 Pin Remap
+//   <i> Enable USART1 Pin Remapping
+#define RTE_USART1_REMAP_FULL           0
+
+//     <o> USART1_TX Pin <0=>Not Used <1=>PB6
+#define RTE_USART1_TX_PORT_ID_FULL      0
+#if    (RTE_USART1_TX_PORT_ID_FULL == 0)
+#define RTE_USART1_TX_FULL              0
+#elif  (RTE_USART1_TX_PORT_ID_FULL == 1)
+#define RTE_USART1_TX_FULL              1
+#define RTE_USART1_TX_PORT_FULL         GPIOB
+#define RTE_USART1_TX_BIT_FULL          6
+#else
+#error "Invalid USART1_TX Pin Configuration!"
+#endif
+
+//     <o> USART1_RX Pin <0=>Not Used <1=>PB7
+#define RTE_USART1_RX_PORT_ID_FULL      0
+#if    (RTE_USART1_RX_PORT_ID_FULL == 0)
+#define RTE_USART1_RX_FULL              0
+#elif  (RTE_USART1_RX_PORT_ID_FULL == 1)
+#define RTE_USART1_RX_FULL              1
+#define RTE_USART1_RX_PORT_FULL         GPIOB
+#define RTE_USART1_RX_BIT_FULL          7
+#else
+#error "Invalid USART1_RX Pin Configuration!"
+#endif
+//   </e>
+
+#if    (RTE_USART1_REMAP_FULL)
+#define RTE_USART1_AF_REMAP              AFIO_USART1_REMAP
+#define RTE_USART1_TX                    RTE_USART1_TX_FULL
+#define RTE_USART1_TX_PORT               RTE_USART1_TX_PORT_FULL
+#define RTE_USART1_TX_BIT                RTE_USART1_TX_BIT_FULL
+#define RTE_USART1_RX                    RTE_USART1_RX_FULL
+#define RTE_USART1_RX_PORT               RTE_USART1_RX_PORT_FULL
+#define RTE_USART1_RX_BIT                RTE_USART1_RX_BIT_FULL
+#define RTE_USART1_CK_PORT               RTE_USART1_CK_PORT_DEF
+#define RTE_USART1_CK_BIT                RTE_USART1_CK_BIT_DEF
+#define RTE_USART1_CTS_PORT              RTE_USART1_CTS_PORT_DEF
+#define RTE_USART1_CTS_BIT               RTE_USART1_CTS_BIT_DEF
+#define RTE_USART1_RTS_PORT              RTE_USART1_RTS_PORT_DEF
+#define RTE_USART1_RTS_BIT               RTE_USART1_RTS_BIT_DEF
+#else 
+#define RTE_USART1_AF_REMAP              AFIO_USART1_NO_REMAP
+#define RTE_USART1_TX                    RTE_USART1_TX_DEF
+#define RTE_USART1_TX_PORT               RTE_USART1_TX_PORT_DEF
+#define RTE_USART1_TX_BIT                RTE_USART1_TX_BIT_DEF
+#define RTE_USART1_RX                    RTE_USART1_RX_DEF
+#define RTE_USART1_RX_PORT               RTE_USART1_RX_PORT_DEF
+#define RTE_USART1_RX_BIT                RTE_USART1_RX_BIT_DEF
+#define RTE_USART1_CK_PORT               RTE_USART1_CK_PORT_DEF
+#define RTE_USART1_CK_BIT                RTE_USART1_CK_BIT_DEF
+#define RTE_USART1_CTS_PORT              RTE_USART1_CTS_PORT_DEF
+#define RTE_USART1_CTS_BIT               RTE_USART1_CTS_BIT_DEF
+#define RTE_USART1_RTS_PORT              RTE_USART1_RTS_PORT_DEF
+#define RTE_USART1_RTS_BIT               RTE_USART1_RTS_BIT_DEF
+#endif
+
+//   <e> DMA Rx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <5=>5
+//     <i>  Selects DMA Channel (only Channel 5 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Set DMA Channel priority
+//   </e>
+#define RTE_USART1_RX_DMA               0
+#define RTE_USART1_RX_DMA_NUMBER        1
+#define RTE_USART1_RX_DMA_CHANNEL       5
+#define RTE_USART1_RX_DMA_PRIORITY      0
+//   <e> DMA Tx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <4=>4
+//     <i>  Selects DMA Channel (only Channel 4 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Set DMA Channel priority
+//   </e>
+#define RTE_USART1_TX_DMA               0
+#define RTE_USART1_TX_DMA_NUMBER        1
+#define RTE_USART1_TX_DMA_CHANNEL       4
+#define RTE_USART1_TX_DMA_PRIORITY      0
+// </e>
+
+
+// <e> USART2 (Universal synchronous asynchronous receiver transmitter)
+// <i> Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART
+#define RTE_USART2                      0
+
+//   <o> USART2_TX Pin <0=>Not Used <1=>PA2
+#define RTE_USART2_TX_PORT_ID_DEF       0
+#if    (RTE_USART2_TX_PORT_ID_DEF == 0)
+#define RTE_USART2_TX_DEF               0
+#elif  (RTE_USART2_TX_PORT_ID_DEF == 1)
+#define RTE_USART2_TX_DEF               1
+#define RTE_USART2_TX_PORT_DEF          GPIOA
+#define RTE_USART2_TX_BIT_DEF           2
+#else
+#error "Invalid USART2_TX Pin Configuration!"
+#endif
+
+//   <o> USART2_RX Pin <0=>Not Used <1=>PA3
+#define RTE_USART2_RX_PORT_ID_DEF       0
+#if    (RTE_USART2_RX_PORT_ID_DEF == 0)
+#define RTE_USART2_RX_DEF               0
+#elif  (RTE_USART2_RX_PORT_ID_DEF == 1)
+#define RTE_USART2_RX_DEF               1
+#define RTE_USART2_RX_PORT_DEF          GPIOA
+#define RTE_USART2_RX_BIT_DEF           3
+#else
+#error "Invalid USART2_RX Pin Configuration!"
+#endif
+
+//   <o> USART2_CK Pin <0=>Not Used <1=>PA4
+#define RTE_USART2_CK_PORT_ID_DEF       0
+#if    (RTE_USART2_CK_PORT_ID_DEF == 0)
+#define RTE_USART2_CK_DEF               0
+#elif  (RTE_USART2_CK_PORT_ID_DEF == 1)
+#define RTE_USART2_CK_DEF               1
+#define RTE_USART2_CK_PORT_DEF          GPIOA
+#define RTE_USART2_CK_BIT_DEF           4
+#else
+#error "Invalid USART2_CK Pin Configuration!"
+#endif
+
+//   <o> USART2_CTS Pin <0=>Not Used <1=>PA0
+#define RTE_USART2_CTS_PORT_ID_DEF      0
+#if    (RTE_USART2_CTS_PORT_ID_DEF == 0)
+#define RTE_USART2_CTS_DEF              0
+#elif  (RTE_USART2_CTS_PORT_ID_DEF == 1)
+#define RTE_USART2_CTS_DEF              1
+#define RTE_USART2_CTS_PORT_DEF         GPIOA
+#define RTE_USART2_CTS_BIT_DEF          0
+#else
+#error "Invalid USART2_CTS Pin Configuration!"
+#endif
+
+//   <o> USART2_RTS Pin <0=>Not Used <1=>PA1
+#define RTE_USART2_RTS_PORT_ID_DEF      0
+#if    (RTE_USART2_RTS_PORT_ID_DEF == 0)
+#define RTE_USART2_RTS_DEF              0
+#elif  (RTE_USART2_RTS_PORT_ID_DEF == 1)
+#define RTE_USART2_RTS_DEF              1
+#define RTE_USART2_RTS_PORT_DEF         GPIOA
+#define RTE_USART2_RTS_BIT_DEF          1
+#else
+#error "Invalid USART2_RTS Pin Configuration!"
+#endif
+
+//   <e> USART2 Pin Remap
+//   <i> Enable USART2 Pin Remapping
+#define RTE_USART2_REMAP_FULL           0
+
+//     <o> USART2_TX Pin <0=>Not Used <1=>PD5
+#define RTE_USART2_TX_PORT_ID_FULL      0
+#if    (RTE_USART2_TX_PORT_ID_FULL == 0)
+#define RTE_USART2_TX_FULL              0
+#elif  (RTE_USART2_TX_PORT_ID_FULL == 1)
+#define RTE_USART2_TX_FULL              1
+#define RTE_USART2_TX_PORT_FULL         GPIOD
+#define RTE_USART2_TX_BIT_FULL          5
+#else
+#error "Invalid USART2_TX Pin Configuration!"
+#endif
+
+//     <o> USART2_RX Pin <0=>Not Used <1=>PD6
+#define RTE_USART2_RX_PORT_ID_FULL      0
+#if    (RTE_USART2_RX_PORT_ID_FULL == 0)
+#define RTE_USART2_RX_FULL              0
+#elif  (RTE_USART2_RX_PORT_ID_FULL == 1)
+#define RTE_USART2_RX_FULL              1
+#define RTE_USART2_RX_PORT_FULL         GPIOD
+#define RTE_USART2_RX_BIT_FULL          6
+#else
+#error "Invalid USART2_RX Pin Configuration!"
+#endif
+
+//     <o> USART2_CK Pin <0=>Not Used <1=>PD7
+#define RTE_USART2_CK_PORT_ID_FULL      0
+#if    (RTE_USART2_CK_PORT_ID_FULL == 0)
+#define RTE_USART2_CK_FULL              0
+#elif  (RTE_USART2_CK_PORT_ID_FULL == 1)
+#define RTE_USART2_CK_FULL              1
+#define RTE_USART2_CK_PORT_FULL         GPIOD
+#define RTE_USART2_CK_BIT_FULL          7
+#else
+#error "Invalid USART2_CK Pin Configuration!"
+#endif
+
+//     <o> USART2_CTS Pin <0=>Not Used <1=>PD3
+#define RTE_USART2_CTS_PORT_ID_FULL     0
+#if    (RTE_USART2_CTS_PORT_ID_FULL == 0)
+#define RTE_USART2_CTS_FULL             0
+#elif  (RTE_USART2_CTS_PORT_ID_FULL == 1)
+#define RTE_USART2_CTS_FULL             1
+#define RTE_USART2_CTS_PORT_FULL        GPIOD
+#define RTE_USART2_CTS_BIT_FULL         3
+#else
+#error "Invalid USART2_CTS Pin Configuration!"
+#endif
+
+//     <o> USART2_RTS Pin <0=>Not Used <1=>PD4
+#define RTE_USART2_RTS_PORT_ID_FULL     0
+#if    (RTE_USART2_RTS_PORT_ID_FULL == 0)
+#define RTE_USART2_RTS_FULL             0
+#elif  (RTE_USART2_RTS_PORT_ID_FULL == 1)
+#define RTE_USART2_RTS_FULL             1
+#define RTE_USART2_RTS_PORT_FULL        GPIOD
+#define RTE_USART2_RTS_BIT_FULL         4
+#else
+#error "Invalid USART2_RTS Pin Configuration!"
+#endif
+//   </e>
+
+#if    (RTE_USART2_REMAP_FULL)
+#define RTE_USART2_AF_REMAP              AFIO_USART2_REMAP
+#define RTE_USART2_TX                    RTE_USART2_TX_FULL
+#define RTE_USART2_TX_PORT               RTE_USART2_TX_PORT_FULL
+#define RTE_USART2_TX_BIT                RTE_USART2_TX_BIT_FULL
+#define RTE_USART2_RX                    RTE_USART2_RX_FULL
+#define RTE_USART2_RX_PORT               RTE_USART2_RX_PORT_FULL
+#define RTE_USART2_RX_BIT                RTE_USART2_RX_BIT_FULL
+#define RTE_USART2_CK                    RTE_USART2_CK_FULL
+#define RTE_USART2_CK_PORT               RTE_USART2_CK_PORT_FULL
+#define RTE_USART2_CK_BIT                RTE_USART2_CK_BIT_FULL
+#define RTE_USART2_CTS                   RTE_USART2_CTS_FULL
+#define RTE_USART2_CTS_PORT              RTE_USART2_CTS_PORT_FULL
+#define RTE_USART2_CTS_BIT               RTE_USART2_CTS_BIT_FULL
+#define RTE_USART2_RTS                   RTE_USART2_RTS_FULL
+#define RTE_USART2_RTS_PORT              RTE_USART2_RTS_PORT_FULL
+#define RTE_USART2_RTS_BIT               RTE_USART2_RTS_BIT_FULL
+#else 
+#define RTE_USART2_AF_REMAP              AFIO_USART2_NO_REMAP
+#define RTE_USART2_TX                    RTE_USART2_TX_DEF
+#define RTE_USART2_TX_PORT               RTE_USART2_TX_PORT_DEF
+#define RTE_USART2_TX_BIT                RTE_USART2_TX_BIT_DEF
+#define RTE_USART2_RX                    RTE_USART2_RX_DEF
+#define RTE_USART2_RX_PORT               RTE_USART2_RX_PORT_DEF
+#define RTE_USART2_RX_BIT                RTE_USART2_RX_BIT_DEF
+#define RTE_USART2_CK                    RTE_USART2_CK_DEF
+#define RTE_USART2_CK_PORT               RTE_USART2_CK_PORT_DEF
+#define RTE_USART2_CK_BIT                RTE_USART2_CK_BIT_DEF
+#define RTE_USART2_CTS                   RTE_USART2_CTS_DEF
+#define RTE_USART2_CTS_PORT              RTE_USART2_CTS_PORT_DEF
+#define RTE_USART2_CTS_BIT               RTE_USART2_CTS_BIT_DEF
+#define RTE_USART2_RTS                   RTE_USART2_RTS_DEF
+#define RTE_USART2_RTS_PORT              RTE_USART2_RTS_PORT_DEF
+#define RTE_USART2_RTS_BIT               RTE_USART2_RTS_BIT_DEF
+#endif
+
+//   <e> DMA Rx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <6=>6
+//     <i>  Selects DMA Channel (only Channel 6 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Set DMA Channel priority
+//   </e>
+#define RTE_USART2_RX_DMA               0
+#define RTE_USART2_RX_DMA_NUMBER        1
+#define RTE_USART2_RX_DMA_CHANNEL       6
+#define RTE_USART2_RX_DMA_PRIORITY      0
+
+//   <e> DMA Tx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <7=>7
+//     <i>  Selects DMA Channel (only Channel 7 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Set DMA Channel priority
+//   </e>
+#define RTE_USART2_TX_DMA               0
+#define RTE_USART2_TX_DMA_NUMBER        1
+#define RTE_USART2_TX_DMA_CHANNEL       7
+#define RTE_USART2_TX_DMA_PRIORITY      0
+
+// </e>
+
+
+// <e> USART3 (Universal synchronous asynchronous receiver transmitter)
+// <i> Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART
+#define RTE_USART3                      0
+
+//   <o> USART3_TX Pin <0=>Not Used <1=>PB10
+#define RTE_USART3_TX_PORT_ID_DEF       0
+#if    (RTE_USART3_TX_PORT_ID_DEF == 0)
+#define RTE_USART3_TX_DEF               0
+#elif  (RTE_USART3_TX_PORT_ID_DEF == 1)
+#define RTE_USART3_TX_DEF               1
+#define RTE_USART3_TX_PORT_DEF          GPIOB
+#define RTE_USART3_TX_BIT_DEF           10
+#else
+#error "Invalid USART3_TX Pin Configuration!"
+#endif
+
+//   <o> USART3_RX Pin <0=>Not Used <1=>PB11
+#define RTE_USART3_RX_PORT_ID_DEF       0
+#if    (RTE_USART3_RX_PORT_ID_DEF == 0)
+#define RTE_USART3_RX_DEF               0
+#elif  (RTE_USART3_RX_PORT_ID_DEF == 1)
+#define RTE_USART3_RX_DEF               1
+#define RTE_USART3_RX_PORT_DEF          GPIOB
+#define RTE_USART3_RX_BIT_DEF           11
+#else
+#error "Invalid USART3_RX Pin Configuration!"
+#endif
+
+//   <o> USART3_CK Pin <0=>Not Used <1=>PB12
+#define RTE_USART3_CK_PORT_ID_DEF       0
+#if    (RTE_USART3_CK_PORT_ID_DEF == 0)
+#define RTE_USART3_CK_DEF               0
+#elif  (RTE_USART3_CK_PORT_ID_DEF == 1)
+#define RTE_USART3_CK_DEF               1
+#define RTE_USART3_CK_PORT_DEF          GPIOB
+#define RTE_USART3_CK_BIT_DEF           12
+#else
+#error "Invalid USART3_CK Pin Configuration!"
+#endif
+
+//   <o> USART3_CTS Pin <0=>Not Used <1=>PB13
+#define RTE_USART3_CTS_PORT_ID_DEF      0
+#if    (RTE_USART3_CTS_PORT_ID_DEF == 0)
+#define RTE_USART3_CTS_DEF              0
+#elif  (RTE_USART3_CTS_PORT_ID_DEF == 1)
+#define RTE_USART3_CTS_DEF              1
+#define RTE_USART3_CTS_PORT_DEF         GPIOB
+#define RTE_USART3_CTS_BIT_DEF          13
+#else
+#error "Invalid USART3_CTS Pin Configuration!"
+#endif
+
+//   <o> USART3_RTS Pin <0=>Not Used <1=>PB14
+#define RTE_USART3_RTS_PORT_ID_DEF      0
+#if    (RTE_USART3_RTS_PORT_ID_DEF == 0)
+#define RTE_USART3_RTS_DEF              0
+#elif  (RTE_USART3_RTS_PORT_ID_DEF == 1)
+#define RTE_USART3_RTS_DEF              1
+#define RTE_USART3_RTS_PORT_DEF         GPIOB
+#define RTE_USART3_RTS_BIT_DEF          14
+#else
+#error "Invalid USART3_RTS Pin Configuration!"
+#endif
+
+//   <e> USART3 Partial Pin Remap
+//   <i> Enable USART3 Partial Pin Remapping
+#define RTE_USART3_REMAP_PARTIAL        0
+
+//     <o> USART3_TX Pin <0=>Not Used <1=>PC10
+#define RTE_USART3_TX_PORT_ID_PARTIAL   0
+#if    (RTE_USART3_TX_PORT_ID_PARTIAL == 0)
+#define RTE_USART3_TX_PARTIAL           0
+#elif  (RTE_USART3_TX_PORT_ID_PARTIAL == 1)
+#define RTE_USART3_TX_PARTIAL           1
+#define RTE_USART3_TX_PORT_PARTIAL      GPIOC
+#define RTE_USART3_TX_BIT_PARTIAL       10
+#else
+#error "Invalid USART3_TX Pin Configuration!"
+#endif
+
+//     <o> USART3_RX Pin <0=>Not Used <1=>PC11
+#define RTE_USART3_RX_PORT_ID_PARTIAL   0
+#if    (RTE_USART3_RX_PORT_ID_PARTIAL == 0)
+#define RTE_USART3_RX_PARTIAL           0
+#elif  (RTE_USART3_RX_PORT_ID_PARTIAL == 1)
+#define RTE_USART3_RX_PARTIAL           1
+#define RTE_USART3_RX_PORT_PARTIAL      GPIOC
+#define RTE_USART3_RX_BIT_PARTIAL       11
+#else
+#error "Invalid USART3_RX Pin Configuration!"
+#endif
+
+//     <o> USART3_CK Pin <0=>Not Used <1=>PC12
+#define RTE_USART3_CK_PORT_ID_PARTIAL   0
+#if    (RTE_USART3_CK_PORT_ID_PARTIAL == 0)
+#define RTE_USART3_CK_PARTIAL           0
+#elif  (RTE_USART3_CK_PORT_ID_PARTIAL == 1)
+#define RTE_USART3_CK_PARTIAL           1
+#define RTE_USART3_CK_PORT_PARTIAL      GPIOC
+#define RTE_USART3_CK_BIT_PARTIAL       12
+#else
+#error "Invalid USART3_CK Pin Configuration!"
+#endif
+//   </e>
+
+//   <e> USART3 Full Pin Remap
+//   <i> Enable USART3 Full Pin Remapping
+#define RTE_USART3_REMAP_FULL           0
+
+//     <o> USART3_TX Pin <0=>Not Used <1=>PD8
+#define RTE_USART3_TX_PORT_ID_FULL      0
+#if    (RTE_USART3_TX_PORT_ID_FULL == 0)
+#define RTE_USART3_TX_FULL              0
+#elif  (RTE_USART3_TX_PORT_ID_FULL == 1)
+#define RTE_USART3_TX_FULL              1
+#define RTE_USART3_TX_PORT_FULL         GPIOD
+#define RTE_USART3_TX_BIT_FULL          8
+#else
+#error "Invalid USART3_TX Pin Configuration!"
+#endif
+
+//     <o> USART3_RX Pin <0=>Not Used <1=>PD9
+#define RTE_USART3_RX_PORT_ID_FULL      0
+#if    (RTE_USART3_RX_PORT_ID_FULL == 0)
+#define RTE_USART3_RX_FULL              0
+#elif  (RTE_USART3_RX_PORT_ID_FULL == 1)
+#define RTE_USART3_RX_FULL              1
+#define RTE_USART3_RX_PORT_FULL         GPIOD
+#define RTE_USART3_RX_BIT_FULL          9
+#else
+#error "Invalid USART3_RX Pin Configuration!"
+#endif
+
+//     <o> USART3_CK Pin <0=>Not Used <1=>PD10
+#define RTE_USART3_CK_PORT_ID_FULL      0
+#if    (RTE_USART3_CK_PORT_ID_FULL == 0)
+#define RTE_USART3_CK_FULL              0
+#elif  (RTE_USART3_CK_PORT_ID_FULL == 1)
+#define RTE_USART3_CK_FULL              1
+#define RTE_USART3_CK_PORT_FULL         GPIOD
+#define RTE_USART3_CK_BIT_FULL          10
+#else
+#error "Invalid USART3_CK Pin Configuration!"
+#endif
+
+//     <o> USART3_CTS Pin <0=>Not Used <1=>PD11
+#define RTE_USART3_CTS_PORT_ID_FULL     0
+#if    (RTE_USART3_CTS_PORT_ID_FULL == 0)
+#define RTE_USART3_CTS_FULL             0
+#elif  (RTE_USART3_CTS_PORT_ID_FULL == 1)
+#define RTE_USART3_CTS_FULL             1
+#define RTE_USART3_CTS_PORT_FULL        GPIOD
+#define RTE_USART3_CTS_BIT_FULL         11
+#else
+#error "Invalid USART3_CTS Pin Configuration!"
+#endif
+
+//     <o> USART3_RTS Pin <0=>Not Used <1=>PD12
+#define RTE_USART3_RTS_PORT_ID_FULL     0
+#if    (RTE_USART3_RTS_PORT_ID_FULL == 0)
+#define RTE_USART3_RTS_FULL             0
+#elif  (RTE_USART3_RTS_PORT_ID_FULL == 1)
+#define RTE_USART3_RTS_FULL             1
+#define RTE_USART3_RTS_PORT_FULL        GPIOD
+#define RTE_USART3_RTS_BIT_FULL         12
+#else
+#error "Invalid USART3_RTS Pin Configuration!"
+#endif
+//   </e>
+
+#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1))
+#error "Invalid USART3 Pin Remap Configuration!"
+#endif
+
+#if    (RTE_USART3_REMAP_FULL)
+#define RTE_USART3_AF_REMAP              AFIO_USART3_REMAP_FULL
+#define RTE_USART3_TX                    RTE_USART3_TX_FULL
+#define RTE_USART3_TX_PORT               RTE_USART3_TX_PORT_FULL
+#define RTE_USART3_TX_BIT                RTE_USART3_TX_BIT_FULL
+#define RTE_USART3_RX                    RTE_USART3_RX_FULL
+#define RTE_USART3_RX_PORT               RTE_USART3_RX_PORT_FULL
+#define RTE_USART3_RX_BIT                RTE_USART3_RX_BIT_FULL
+#define RTE_USART3_CK                    RTE_USART3_CK_FULL
+#define RTE_USART3_CK_PORT               RTE_USART3_CK_PORT_FULL
+#define RTE_USART3_CK_BIT                RTE_USART3_CK_BIT_FULL
+#define RTE_USART3_CTS                   RTE_USART3_CTS_FULL
+#define RTE_USART3_CTS_PORT              RTE_USART3_CTS_PORT_FULL
+#define RTE_USART3_CTS_BIT               RTE_USART3_CTS_BIT_FULL
+#define RTE_USART3_RTS                   RTE_USART3_RTS_FULL
+#define RTE_USART3_RTS_PORT              RTE_USART3_RTS_PORT_FULL
+#define RTE_USART3_RTS_BIT               RTE_USART3_RTS_BIT_FULL
+#elif  (RTE_USART3_REMAP_PARTIAL)
+#define RTE_USART3_AF_REMAP              AFIO_USART3_REMAP_PARTIAL
+#define RTE_USART3_TX                    RTE_USART3_TX_PARTIAL
+#define RTE_USART3_TX_PORT               RTE_USART3_TX_PORT_PARTIAL
+#define RTE_USART3_TX_BIT                RTE_USART3_TX_BIT_PARTIAL
+#define RTE_USART3_RX                    RTE_USART3_RX_PARTIAL
+#define RTE_USART3_RX_PORT               RTE_USART3_RX_PORT_PARTIAL
+#define RTE_USART3_RX_BIT                RTE_USART3_RX_BIT_PARTIAL
+#define RTE_USART3_CK                    RTE_USART3_CK_PARTIAL
+#define RTE_USART3_CK_PORT               RTE_USART3_CK_PORT_PARTIAL
+#define RTE_USART3_CK_BIT                RTE_USART3_CK_BIT_PARTIAL
+#define RTE_USART3_CTS                   RTE_USART3_CTS_DEF
+#define RTE_USART3_CTS_PORT              RTE_USART3_CTS_PORT_DEF
+#define RTE_USART3_CTS_BIT               RTE_USART3_CTS_BIT_DEF
+#define RTE_USART3_RTS                   RTE_USART3_RTS_DEF
+#define RTE_USART3_RTS_PORT              RTE_USART3_RTS_PORT_DEF
+#define RTE_USART3_RTS_BIT               RTE_USART3_RTS_BIT_DEF
+#else
+#define RTE_USART3_AF_REMAP              AFIO_USART3_NO_REMAP
+#define RTE_USART3_TX                    RTE_USART3_TX_DEF
+#define RTE_USART3_TX_PORT               RTE_USART3_TX_PORT_DEF
+#define RTE_USART3_TX_BIT                RTE_USART3_TX_BIT_DEF
+#define RTE_USART3_RX                    RTE_USART3_RX_DEF
+#define RTE_USART3_RX_PORT               RTE_USART3_RX_PORT_DEF
+#define RTE_USART3_RX_BIT                RTE_USART3_RX_BIT_DEF
+#define RTE_USART3_CK                    RTE_USART3_CK_DEF
+#define RTE_USART3_CK_PORT               RTE_USART3_CK_PORT_DEF
+#define RTE_USART3_CK_BIT                RTE_USART3_CK_BIT_DEF
+#define RTE_USART3_CTS                   RTE_USART3_CTS_DEF
+#define RTE_USART3_CTS_PORT              RTE_USART3_CTS_PORT_DEF
+#define RTE_USART3_CTS_BIT               RTE_USART3_CTS_BIT_DEF
+#define RTE_USART3_RTS                   RTE_USART3_RTS_DEF
+#define RTE_USART3_RTS_PORT              RTE_USART3_RTS_PORT_DEF
+#define RTE_USART3_RTS_BIT               RTE_USART3_RTS_BIT_DEF
+#endif
+
+//   <e> DMA Rx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <3=>3
+//     <i>  Selects DMA Channel (only Channel 3 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Sets DMA Channel priority
+//   </e>
+#define RTE_USART3_RX_DMA               0
+#define RTE_USART3_RX_DMA_NUMBER        1
+#define RTE_USART3_RX_DMA_CHANNEL       3
+#define RTE_USART3_RX_DMA_PRIORITY      0
+
+//   <e> DMA Tx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <2=>2
+//     <i>  Selects DMA Channel (only Channel 2 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Sets DMA Channel priority
+//   </e>
+#define RTE_USART3_TX_DMA               0
+#define RTE_USART3_TX_DMA_NUMBER        1
+#define RTE_USART3_TX_DMA_CHANNEL       2
+#define RTE_USART3_TX_DMA_PRIORITY      0
+
+// </e>
+
+
+// <e> UART4 (Universal asynchronous receiver transmitter)
+// <i> Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART
+#define RTE_UART4                       0
+#define RTE_UART4_AF_REMAP              AFIO_UNAVAILABLE_REMAP
+
+//   <o> UART4_TX Pin <0=>Not Used <1=>PC10
+#define RTE_UART4_TX_ID                 0
+#if    (RTE_UART4_TX_ID == 0)
+#define RTE_UART4_TX                    0
+#elif  (RTE_UART4_TX_ID == 1)
+#define RTE_UART4_TX                    1
+#define RTE_UART4_TX_PORT               GPIOC
+#define RTE_UART4_TX_BIT                10
+#else
+#error "Invalid UART4_TX Pin Configuration!"
+#endif
+
+//   <o> UART4_RX Pin <0=>Not Used <1=>PC11
+#define RTE_UART4_RX_ID                 0
+#if    (RTE_UART4_RX_ID == 0)
+#define RTE_UART4_RX                    0
+#elif  (RTE_UART4_RX_ID == 1)
+#define RTE_UART4_RX                    1
+#define RTE_UART4_RX_PORT               GPIOC
+#define RTE_UART4_RX_BIT                11
+#else
+#error "Invalid UART4_RX Pin Configuration!"
+#endif
+
+
+//   <e> DMA Rx
+//     <o1> Number <2=>2
+//     <i>  Selects DMA Number (only DMA2 can be used)
+//     <o2> Channel <3=>3
+//     <i>  Selects DMA Channel (only Channel 3 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Sets DMA Channel priority
+//   </e>
+#define RTE_UART4_RX_DMA                0
+#define RTE_UART4_RX_DMA_NUMBER         2
+#define RTE_UART4_RX_DMA_CHANNEL        3
+#define RTE_UART4_RX_DMA_PRIORITY       0
+
+//   <e> DMA Tx
+//     <o1> Number <2=>2
+//     <i>  Selects DMA Number (only DMA2 can be used)
+//     <o2> Channel <5=>5
+//     <i>  Selects DMA Channel (only Channel 5 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
+//     <i>  Sets DMA Channel priority
+//   </e>
+#define RTE_UART4_TX_DMA                0
+#define RTE_UART4_TX_DMA_NUMBER         2
+#define RTE_UART4_TX_DMA_CHANNEL        5
+#define RTE_UART4_TX_DMA_PRIORITY       0
+
+// </e>
+
+
+// <e> UART5 (Universal asynchronous receiver transmitter)
+// <i> Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART
+#define RTE_UART5                       0
+#define RTE_UART5_AF_REMAP              AFIO_UNAVAILABLE_REMAP
+
+//   <o> UART5_TX Pin <0=>Not Used <1=>PC12
+#define RTE_UART5_TX_ID                 0
+#if    (RTE_UART5_TX_ID == 0)
+#define RTE_UART5_TX                    0
+#elif  (RTE_UART5_TX_ID == 1)
+#define RTE_UART5_TX                    1
+#define RTE_UART5_TX_PORT               GPIOC
+#define RTE_UART5_TX_BIT                12
+#else
+#error "Invalid UART5_TX Pin Configuration!"
+#endif
+
+//   <o> UART5_RX Pin <0=>Not Used <1=>PD2
+#define RTE_UART5_RX_ID                 0
+#if    (RTE_UART5_RX_ID == 0)
+#define RTE_UART5_RX                    0
+#elif  (RTE_UART5_RX_ID == 1)
+#define RTE_UART5_RX                    1
+#define RTE_UART5_RX_PORT               GPIOD
+#define RTE_UART5_RX_BIT                2
+#else
+#error "Invalid UART5_RX Pin Configuration!"
+#endif
+// </e>
+
+
+// <e> I2C1 (Inter-integrated Circuit Interface 1)
+// <i> Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C
+#define RTE_I2C1                        0
+
+//   <o> I2C1_SCL Pin <0=>PB6
+#define RTE_I2C1_SCL_PORT_ID_DEF        0
+#if    (RTE_I2C1_SCL_PORT_ID_DEF == 0)
+#define RTE_I2C1_SCL_PORT_DEF           GPIOB
+#define RTE_I2C1_SCL_BIT_DEF            6
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+//   <o> I2C1_SDA Pin <0=>PB7
+#define RTE_I2C1_SDA_PORT_ID_DEF        0
+#if    (RTE_I2C1_SDA_PORT_ID_DEF == 0)
+#define RTE_I2C1_SDA_PORT_DEF           GPIOB
+#define RTE_I2C1_SDA_BIT_DEF            7
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+//   <e> I2C1 Pin Remap
+//   <i> Enable I2C1 Pin Remapping
+#define RTE_I2C1_REMAP_FULL             0
+
+//   <o> I2C1_SCL Pin <0=>PB8
+#define RTE_I2C1_SCL_PORT_ID_FULL       0
+#if    (RTE_I2C1_SCL_PORT_ID_FULL == 0)
+#define RTE_I2C1_SCL_PORT_FULL          GPIOB
+#define RTE_I2C1_SCL_BIT_FULL           8
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+//   <o> I2C1_SDA Pin <0=>PB9
+#define RTE_I2C1_SDA_PORT_ID_FULL       0
+#if    (RTE_I2C1_SDA_PORT_ID_FULL == 0)
+#define RTE_I2C1_SDA_PORT_FULL          GPIOB
+#define RTE_I2C1_SDA_BIT_FULL           9
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+//   </e>
+
+#if    (RTE_I2C1_REMAP_FULL)
+#define RTE_I2C1_AF_REMAP               AFIO_I2C1_REMAP
+#define RTE_I2C1_SCL_PORT               RTE_I2C1_SCL_PORT_FULL
+#define RTE_I2C1_SCL_BIT                RTE_I2C1_SCL_BIT_FULL
+#define RTE_I2C1_SDA_PORT               RTE_I2C1_SDA_PORT_FULL
+#define RTE_I2C1_SDA_BIT                RTE_I2C1_SDA_BIT_FULL
+#else
+#define RTE_I2C1_AF_REMAP               AFIO_I2C1_NO_REMAP
+#define RTE_I2C1_SCL_PORT               RTE_I2C1_SCL_PORT_DEF
+#define RTE_I2C1_SCL_BIT                RTE_I2C1_SCL_BIT_DEF
+#define RTE_I2C1_SDA_PORT               RTE_I2C1_SDA_PORT_DEF
+#define RTE_I2C1_SDA_BIT                RTE_I2C1_SDA_BIT_DEF
+#endif
+
+
+//   <e> DMA Rx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <7=>7
+//     <i>  Selects DMA Channel (only Channel 7 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_I2C1_RX_DMA                 0
+#define RTE_I2C1_RX_DMA_NUMBER          1
+#define RTE_I2C1_RX_DMA_CHANNEL         7
+#define RTE_I2C1_RX_DMA_PRIORITY        0
+
+//   <e> DMA Tx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <6=>6
+//     <i>  Selects DMA Channel (only Channel 6 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_I2C1_TX_DMA                 0
+#define RTE_I2C1_TX_DMA_NUMBER          1
+#define RTE_I2C1_TX_DMA_CHANNEL         6
+#define RTE_I2C1_TX_DMA_PRIORITY        0
+
+// </e>
+
+
+// <e> I2C2 (Inter-integrated Circuit Interface 2)
+// <i> Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C
+#define RTE_I2C2                        0
+#define RTE_I2C2_AF_REMAP              AFIO_UNAVAILABLE_REMAP
+
+//   <o> I2C2_SCL Pin <0=>PB10
+#define RTE_I2C2_SCL_PORT_ID            0
+#if    (RTE_I2C2_SCL_PORT_ID == 0)
+#define RTE_I2C2_SCL_PORT               GPIOB
+#define RTE_I2C2_SCL_BIT                10
+#else
+#error "Invalid I2C2_SCL Pin Configuration!"
+#endif
+
+//   <o> I2C2_SDA Pin <0=>PB11
+#define RTE_I2C2_SDA_PORT_ID            0
+#if    (RTE_I2C2_SDA_PORT_ID == 0)
+#define RTE_I2C2_SDA_PORT               GPIOB
+#define RTE_I2C2_SDA_BIT                11
+#else
+#error "Invalid I2C2_SCL Pin Configuration!"
+#endif
+
+//   <e> DMA Rx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <5=>5
+//     <i>  Selects DMA Channel (only Channel 5 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_I2C2_RX_DMA                 1
+#define RTE_I2C2_RX_DMA_NUMBER          1
+#define RTE_I2C2_RX_DMA_CHANNEL         5
+#define RTE_I2C2_RX_DMA_PRIORITY        0
+
+//   <e> DMA Tx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <4=>4
+//     <i>  Selects DMA Channel (only Channel 4 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_I2C2_TX_DMA                 1
+#define RTE_I2C2_TX_DMA_NUMBER          1
+#define RTE_I2C2_TX_DMA_CHANNEL         4
+#define RTE_I2C2_TX_DMA_PRIORITY        0
+
+// </e>
+
+
+// <e> SPI1 (Serial Peripheral Interface 1) [Driver_SPI1]
+// <i> Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI
+#define RTE_SPI1                        0
+
+//   <e> SPI1_NSS Pin
+//   <i> Configure Pin if exists
+//   <i> GPIO Pxy (x = A..G, y = 0..15)
+//     <o1> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//     <i>  Selects Port Name
+//     <o2> Bit <0-15>
+//     <i>  Selects Port Bit
+//   </e>
+#define RTE_SPI1_NSS_PIN                1
+#define RTE_SPI1_NSS_PORT               GPIO_PORT(0)
+#define RTE_SPI1_NSS_BIT                4
+
+//   <o> SPI1_SCK Pin <0=>PA5
+#define RTE_SPI1_SCK_PORT_ID_DEF        0
+#if    (RTE_SPI1_SCK_PORT_ID_DEF == 0)
+#define RTE_SPI1_SCK_PORT_DEF           GPIOA
+#define RTE_SPI1_SCK_BIT_DEF            5
+#else
+#error "Invalid SPI1_SCK Pin Configuration!"
+#endif
+
+//   <o> SPI1_MISO Pin <0=>Not Used <1=>PA6
+#define RTE_SPI1_MISO_PORT_ID_DEF       0
+#if    (RTE_SPI1_MISO_PORT_ID_DEF == 0)
+#define RTE_SPI1_MISO_DEF               0
+#elif   (RTE_SPI1_MISO_PORT_ID_DEF == 1)
+#define RTE_SPI1_MISO_DEF               1
+#define RTE_SPI1_MISO_PORT_DEF          GPIOA
+#define RTE_SPI1_MISO_BIT_DEF           6
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+
+//   <o> SPI1_MOSI Pin <0=>Not Used <1=>PA7
+#define RTE_SPI1_MOSI_PORT_ID_DEF       0
+#if    (RTE_SPI1_MOSI_PORT_ID_DEF == 0)
+#define RTE_SPI1_MOSI_DEF               0
+#elif  (RTE_SPI1_MOSI_PORT_ID_DEF == 1)
+#define RTE_SPI1_MOSI_DEF               1
+#define RTE_SPI1_MOSI_PORT_DEF          GPIOA
+#define RTE_SPI1_MOSI_BIT_DEF           7
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+
+//   <e> SPI1 Pin Remap
+//   <i> Enable SPI1 Pin Remapping.
+#define RTE_SPI1_REMAP                  0
+
+//   <o> SPI1_SCK Pin <0=>PB3
+#define RTE_SPI1_SCK_PORT_ID_FULL       0
+#if    (RTE_SPI1_SCK_PORT_ID_FULL == 0)
+#define RTE_SPI1_SCK_PORT_FULL          GPIOB
+#define RTE_SPI1_SCK_BIT_FULL           3
+#else
+#error "Invalid SPI1_SCK Pin Configuration!"
+#endif
+
+//   <o> SPI1_MISO Pin <0=>Not Used <1=>PB4
+#define RTE_SPI1_MISO_PORT_ID_FULL      0
+#if    (RTE_SPI1_MISO_PORT_ID_FULL == 0)
+#define RTE_SPI1_MISO_FULL              0
+#elif  (RTE_SPI1_MISO_PORT_ID_FULL == 1)
+#define RTE_SPI1_MISO_FULL              1
+#define RTE_SPI1_MISO_PORT_FULL         GPIOB
+#define RTE_SPI1_MISO_BIT_FULL          4
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+//   <o> SPI1_MOSI Pin <0=>Not Used <1=>PB5
+#define RTE_SPI1_MOSI_PORT_ID_FULL      0
+#if    (RTE_SPI1_MOSI_PORT_ID_FULL == 0)
+#define RTE_SPI1_MOSI_FULL              0
+#elif  (RTE_SPI1_MOSI_PORT_ID_FULL == 1)
+#define RTE_SPI1_MOSI_FULL              1
+#define RTE_SPI1_MOSI_PORT_FULL         GPIOB
+#define RTE_SPI1_MOSI_BIT_FULL          5
+#else
+#error "Invalid SPI1_MOSI Pin Configuration!"
+#endif
+
+//   </e>
+
+#if    (RTE_SPI1_REMAP)
+#define RTE_SPI1_AF_REMAP               AFIO_SPI1_REMAP
+#define RTE_SPI1_SCK_PORT               RTE_SPI1_SCK_PORT_FULL
+#define RTE_SPI1_SCK_BIT                RTE_SPI1_SCK_BIT_FULL
+#define RTE_SPI1_MISO                   RTE_SPI1_MISO_FULL
+#define RTE_SPI1_MISO_PORT              RTE_SPI1_MISO_PORT_FULL
+#define RTE_SPI1_MISO_BIT               RTE_SPI1_MISO_BIT_FULL
+#define RTE_SPI1_MOSI                   RTE_SPI1_MOSI_FULL
+#define RTE_SPI1_MOSI_PORT              RTE_SPI1_MOSI_PORT_FULL
+#define RTE_SPI1_MOSI_BIT               RTE_SPI1_MOSI_BIT_FULL
+#else 
+#define RTE_SPI1_AF_REMAP               AFIO_SPI1_NO_REMAP
+#define RTE_SPI1_SCK_PORT               RTE_SPI1_SCK_PORT_DEF
+#define RTE_SPI1_SCK_BIT                RTE_SPI1_SCK_BIT_DEF
+#define RTE_SPI1_MISO                   RTE_SPI1_MISO_DEF
+#define RTE_SPI1_MISO_PORT              RTE_SPI1_MISO_PORT_DEF
+#define RTE_SPI1_MISO_BIT               RTE_SPI1_MISO_BIT_DEF
+#define RTE_SPI1_MOSI                   RTE_SPI1_MOSI_DEF
+#define RTE_SPI1_MOSI_PORT              RTE_SPI1_MOSI_PORT_DEF
+#define RTE_SPI1_MOSI_BIT               RTE_SPI1_MOSI_BIT_DEF
+#endif
+
+//   <e> DMA Rx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <2=>2
+//     <i>  Selects DMA Channel (only Channel 2 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_SPI1_RX_DMA                 0
+#define RTE_SPI1_RX_DMA_NUMBER          1
+#define RTE_SPI1_RX_DMA_CHANNEL         2
+#define RTE_SPI1_RX_DMA_PRIORITY        0
+
+//   <e> DMA Tx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <3=>3
+//     <i>  Selects DMA Channel (only Channel 3 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_SPI1_TX_DMA                 0
+#define RTE_SPI1_TX_DMA_NUMBER          1
+#define RTE_SPI1_TX_DMA_CHANNEL         3
+#define RTE_SPI1_TX_DMA_PRIORITY        0
+
+// </e>
+
+
+// <e> SPI2 (Serial Peripheral Interface 2) [Driver_SPI2]
+// <i> Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI
+#define RTE_SPI2                        0
+
+//   <e> SPI2_NSS Pin
+//   <i> Configure Pin if exists
+//   <i> GPIO Pxy (x = A..G, y = 0..15)
+//     <o1> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//     <i>  Selects Port Name
+//     <o2> Bit <0-15>
+//     <i>  Selects Port Bit
+//   </e>
+#define RTE_SPI2_NSS_PIN                1
+#define RTE_SPI2_NSS_PORT               GPIO_PORT(1)
+#define RTE_SPI2_NSS_BIT                12
+
+//   <o> SPI2_SCK Pin <0=>PB13
+#define RTE_SPI2_SCK_PORT_ID            0
+#if    (RTE_SPI2_SCK_PORT_ID == 0)
+#define RTE_SPI2_SCK_PORT               GPIOB
+#define RTE_SPI2_SCK_BIT                13
+#define RTE_SPI2_SCK_REMAP              0
+#else
+#error "Invalid SPI2_SCK Pin Configuration!"
+#endif
+
+//   <o> SPI2_MISO Pin <0=>Not Used <1=>PB14
+#define RTE_SPI2_MISO_PORT_ID           0
+#if    (RTE_SPI2_MISO_PORT_ID == 0)
+#define RTE_SPI2_MISO                   0
+#elif  (RTE_SPI2_MISO_PORT_ID == 1)
+#define RTE_SPI2_MISO                   1
+#define RTE_SPI2_MISO_PORT              GPIOB
+#define RTE_SPI2_MISO_BIT               14
+#define RTE_SPI2_MISO_REMAP             0
+#else
+#error "Invalid SPI2_MISO Pin Configuration!"
+#endif
+
+//   <o> SPI2_MOSI Pin <0=>Not Used <1=>PB15
+#define RTE_SPI2_MOSI_PORT_ID           0
+#if    (RTE_SPI2_MOSI_PORT_ID == 0)
+#define RTE_SPI2_MOSI                   0
+#elif  (RTE_SPI2_MOSI_PORT_ID == 1)
+#define RTE_SPI2_MOSI                   1
+#define RTE_SPI2_MOSI_PORT              GPIOB
+#define RTE_SPI2_MOSI_BIT               15
+#define RTE_SPI2_MOSI_REMAP             0
+#else
+#error "Invalid SPI2_MISO Pin Configuration!"
+#endif
+
+//   <e> DMA Rx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <4=>4
+//     <i>  Selects DMA Channel (only Channel 4 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_SPI2_RX_DMA                 0
+#define RTE_SPI2_RX_DMA_NUMBER          1
+#define RTE_SPI2_RX_DMA_CHANNEL         4
+#define RTE_SPI2_RX_DMA_PRIORITY        0
+
+//   <e> DMA Tx
+//     <o1> Number <1=>1
+//     <i>  Selects DMA Number (only DMA1 can be used)
+//     <o2> Channel <5=>5
+//     <i>  Selects DMA Channel (only Channel 5 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_SPI2_TX_DMA                 0
+#define RTE_SPI2_TX_DMA_NUMBER          1
+#define RTE_SPI2_TX_DMA_CHANNEL         5
+#define RTE_SPI2_TX_DMA_PRIORITY        0
+
+// </e>
+
+
+// <e> SPI3 (Serial Peripheral Interface 3) [Driver_SPI3]
+// <i> Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI
+#define RTE_SPI3                        0
+
+//   <e> SPI3_NSS Pin
+//   <i> Configure Pin if exists
+//   <i> GPIO Pxy (x = A..G, y = 0..15)
+//     <o1> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//     <i>  Selects Port Name
+//     <o2> Bit <0-15>
+//     <i>  Selects Port Bit
+//   </e>
+#define RTE_SPI3_NSS_PIN                1
+#define RTE_SPI3_NSS_PORT               GPIO_PORT(0)
+#define RTE_SPI3_NSS_BIT                15
+
+//   <o> SPI3_SCK Pin <0=>PB3
+#define RTE_SPI3_SCK_PORT_ID_DEF        0
+#if    (RTE_SPI3_SCK_PORT_ID_DEF == 0)
+#define RTE_SPI3_SCK_PORT_DEF           GPIOB
+#define RTE_SPI3_SCK_BIT_DEF            3
+#else
+#error "Invalid SPI3_SCK Pin Configuration!"
+#endif
+
+//   <o> SPI3_MISO Pin <0=>Not Used <1=>PB4
+#define RTE_SPI3_MISO_PORT_ID_DEF       0
+#if    (RTE_SPI3_MISO_PORT_ID_DEF == 0)
+#define RTE_SPI3_MISO_DEF               0
+#elif  (RTE_SPI3_MISO_PORT_ID_DEF == 1)
+#define RTE_SPI3_MISO_DEF               1
+#define RTE_SPI3_MISO_PORT_DEF          GPIOB
+#define RTE_SPI3_MISO_BIT_DEF           4
+#else
+#error "Invalid SPI3_MISO Pin Configuration!"
+#endif
+
+//   <o> SPI3_MOSI <0=>Not Used Pin <1=>PB5
+#define RTE_SPI3_MOSI_PORT_ID_DEF       0
+#if    (RTE_SPI3_MOSI_PORT_ID_DEF == 0)
+#define RTE_SPI3_MOSI_DEF               0
+#elif  (RTE_SPI3_MOSI_PORT_ID_DEF == 1)
+#define RTE_SPI3_MOSI_DEF               1
+#define RTE_SPI3_MOSI_PORT_DEF          GPIOB
+#define RTE_SPI3_MOSI_BIT_DEF           5
+#else
+#error "Invalid SPI3_MOSI Pin Configuration!"
+#endif
+
+//   <e> SPI3 Pin Remap
+//   <i> Enable SPI3 Pin Remapping.
+//   <i> SPI 3 Pin Remapping is available only in connectivity line devices!
+#define RTE_SPI3_REMAP                  0
+
+//   <o> SPI3_SCK Pin <0=>PC10
+#define RTE_SPI3_SCK_PORT_ID_FULL       0
+#if    (RTE_SPI3_SCK_PORT_ID_FULL == 0)
+#define RTE_SPI3_SCK_PORT_FULL          GPIOC
+#define RTE_SPI3_SCK_BIT_FULL           10
+#else
+#error "Invalid SPI3_SCK Pin Configuration!"
+#endif
+
+//   <o> SPI3_MISO Pin <0=>Not Used <1=>PC11
+#define RTE_SPI3_MISO_PORT_ID_FULL      0
+#if    (RTE_SPI3_MISO_PORT_ID_FULL == 0)
+#define RTE_SPI3_MISO_FULL              0
+#elif  (RTE_SPI3_MISO_PORT_ID_FULL == 1)
+#define RTE_SPI3_MISO_FULL              1
+#define RTE_SPI3_MISO_PORT_FULL         GPIOC
+#define RTE_SPI3_MISO_BIT_FULL          11
+#else
+#error "Invalid SPI3_MISO Pin Configuration!"
+#endif
+//   <o> SPI3_MOSI Pin <0=>Not Used <1=>PC12
+#define RTE_SPI3_MOSI_PORT_ID_FULL      0
+#if    (RTE_SPI3_MOSI_PORT_ID_FULL == 0)
+#define RTE_SPI3_MOSI_FULL              0
+#elif  (RTE_SPI3_MOSI_PORT_ID_FULL == 1)
+#define RTE_SPI3_MOSI_FULL              1
+#define RTE_SPI3_MOSI_PORT_FULL         GPIOC
+#define RTE_SPI3_MOSI_BIT_FULL          12
+#else
+#error "Invalid SPI3_MOSI Pin Configuration!"
+#endif
+
+//   </e>
+
+#if    (RTE_SPI3_REMAP)
+#define RTE_SPI3_AF_REMAP               AFIO_SPI3_REMAP
+#define RTE_SPI3_SCK_PORT               RTE_SPI3_SCK_PORT_FULL
+#define RTE_SPI3_SCK_BIT                RTE_SPI3_SCK_BIT_FULL
+#define RTE_SPI3_MISO                   RTE_SPI3_MISO_FULL
+#define RTE_SPI3_MISO_PORT              RTE_SPI3_MISO_PORT_FULL
+#define RTE_SPI3_MISO_BIT               RTE_SPI3_MISO_BIT_FULL
+#define RTE_SPI3_MOSI                   RTE_SPI3_MOSI_FULL
+#define RTE_SPI3_MOSI_PORT              RTE_SPI3_MOSI_PORT_FULL
+#define RTE_SPI3_MOSI_BIT               RTE_SPI3_MOSI_BIT_FULL
+#else 
+#define RTE_SPI3_AF_REMAP               AFIO_SPI3_NO_REMAP
+#define RTE_SPI3_SCK_PORT               RTE_SPI3_SCK_PORT_DEF
+#define RTE_SPI3_SCK_BIT                RTE_SPI3_SCK_BIT_DEF
+#define RTE_SPI3_MISO                   RTE_SPI3_MISO_DEF
+#define RTE_SPI3_MISO_PORT              RTE_SPI3_MISO_PORT_DEF
+#define RTE_SPI3_MISO_BIT               RTE_SPI3_MISO_BIT_DEF
+#define RTE_SPI3_MOSI                   RTE_SPI3_MOSI_DEF
+#define RTE_SPI3_MOSI_PORT              RTE_SPI3_MOSI_PORT_DEF
+#define RTE_SPI3_MOSI_BIT               RTE_SPI3_MOSI_BIT_DEF
+#endif
+
+//   <e> DMA Rx
+//     <o1> Number <2=>2
+//     <i>  Selects DMA Number (only DMA2 can be used)
+//     <o2> Channel <1=>1
+//     <i>  Selects DMA Channel (only Channel 1 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_SPI3_RX_DMA                 0
+#define RTE_SPI3_RX_DMA_NUMBER          2
+#define RTE_SPI3_RX_DMA_CHANNEL         1
+#define RTE_SPI3_RX_DMA_PRIORITY        0
+
+//   <e> DMA Tx
+//     <o1> Number <2=>2
+//     <i>  Selects DMA Number (only DMA2 can be used)
+//     <o2> Channel <2=>2
+//     <i>  Selects DMA Channel (only Channel 2 can be used)
+//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </e>
+#define RTE_SPI3_TX_DMA                 0
+#define RTE_SPI3_TX_DMA_NUMBER          2
+#define RTE_SPI3_TX_DMA_CHANNEL         2
+#define RTE_SPI3_TX_DMA_PRIORITY        0
+
+// </e>
+
+
+// <e> SDIO (Secure Digital Input/Output) [Driver_MCI0]
+// <i> Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI
+#define RTE_SDIO                        0
+
+//   <h> SDIO Peripheral Bus
+//     <o> SDIO_CK Pin <0=>PC12
+#define   RTE_SDIO_CK_PORT_ID           0
+#if      (RTE_SDIO_CK_PORT_ID == 0)
+  #define RTE_SDIO_CK_PORT              GPIOC
+  #define RTE_SDIO_CK_PIN               12
+#else
+  #error "Invalid SDIO_CLK Pin Configuration!"
+#endif
+//     <o> SDIO_CMD Pin <0=>PD2
+#define   RTE_SDIO_CMD_PORT_ID          0
+#if      (RTE_SDIO_CMD_PORT_ID == 0)
+  #define RTE_SDIO_CMD_PORT             GPIOD
+  #define RTE_SDIO_CMD_PIN              2
+#else
+  #error "Invalid SDIO_CMD Pin Configuration!"
+#endif
+//     <o> SDIO_D0 Pin <0=>PC8
+#define   RTE_SDIO_D0_PORT_ID           0
+#if      (RTE_SDIO_D0_PORT_ID == 0)
+  #define RTE_SDIO_D0_PORT              GPIOC
+  #define RTE_SDIO_D0_PIN               8
+#else
+  #error "Invalid SDIO_DAT0 Pin Configuration!"
+#endif
+//     <e> SDIO_D[1 .. 3]
+#define   RTE_SDIO_BUS_WIDTH_4          1
+//       <o> SDIO_D1 Pin <0=>PC9
+#define   RTE_SDIO_D1_PORT_ID           0
+#if      (RTE_SDIO_D1_PORT_ID == 0)
+  #define RTE_SDIO_D1_PORT              GPIOC
+  #define RTE_SDIO_D1_PIN               9
+#else
+  #error "Invalid SDIO_D1 Pin Configuration!"
+#endif
+//       <o> SDIO_D2 Pin <0=>PC10
+#define   RTE_SDIO_D2_PORT_ID           0
+#if      (RTE_SDIO_D2_PORT_ID == 0)
+  #define RTE_SDIO_D2_PORT              GPIOC
+  #define RTE_SDIO_D2_PIN               10
+#else
+  #error "Invalid SDIO_D2 Pin Configuration!"
+#endif
+//       <o> SDIO_D3 Pin <0=>PC11
+#define   RTE_SDIO_D3_PORT_ID           0
+#if      (RTE_SDIO_D3_PORT_ID == 0)
+  #define RTE_SDIO_D3_PORT              GPIOC
+  #define RTE_SDIO_D3_PIN               11
+#else
+  #error "Invalid SDIO_D3 Pin Configuration!"
+#endif
+//     </e> SDIO_D[1 .. 3]
+//     <e> SDIO_D[4 .. 7]
+#define   RTE_SDIO_BUS_WIDTH_8          0
+//       <o> SDIO_D4 Pin <0=>PB8
+#define   RTE_SDIO_D4_PORT_ID           0
+#if      (RTE_SDIO_D4_PORT_ID == 0)
+  #define RTE_SDIO_D4_PORT              GPIOB
+  #define RTE_SDIO_D4_PIN               8
+#else
+  #error "Invalid SDIO_D4 Pin Configuration!"
+#endif
+//       <o> SDIO_D5 Pin <0=>PB9
+#define   RTE_SDIO_D5_PORT_ID           0
+#if      (RTE_SDIO_D5_PORT_ID == 0)
+  #define RTE_SDIO_D5_PORT              GPIOB
+  #define RTE_SDIO_D5_PIN               9
+#else
+  #error "Invalid SDIO_D5 Pin Configuration!"
+#endif
+//       <o> SDIO_D6 Pin <0=>PC6
+#define   RTE_SDIO_D6_PORT_ID           0
+#if      (RTE_SDIO_D6_PORT_ID == 0)
+  #define RTE_SDIO_D6_PORT              GPIOC
+  #define RTE_SDIO_D6_PIN               6
+#else
+  #error "Invalid SDIO_D6 Pin Configuration!"
+#endif
+//       <o> SDIO_D7 Pin <0=>PC7
+#define   RTE_SDIO_D7_PORT_ID           0
+#if      (RTE_SDIO_D7_PORT_ID == 0)
+  #define RTE_SDIO_D7_PORT              GPIOC
+  #define RTE_SDIO_D7_PIN               7
+#else
+  #error "Invalid SDIO_D7 Pin Configuration!"
+#endif
+//     </e> SDIO_D[4 .. 7]
+//   </h> SDIO Peripheral Bus
+
+//   <e> Card Detect Pin
+//   <i> Configure Pin if exists
+//   <i> GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//     <o1> Active State <0=>Low <1=>High
+//     <i>  Selects Active State Logical Level
+//     <o2> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//     <i>  Selects Port Name
+//     <o3> Bit <0-15>
+//     <i>  Selects Port Bit
+//   </e>
+#define RTE_SDIO_CD_EN                  1
+#define RTE_SDIO_CD_ACTIVE              0
+#define RTE_SDIO_CD_PORT                GPIO_PORT(5)
+#define RTE_SDIO_CD_PIN                 11
+
+//   <e> Write Protect Pin
+//   <i> Configure Pin if exists
+//   <i> GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//     <o1> Active State <0=>Low <1=>High
+//     <i>  Selects Active State Logical Level
+//     <o2> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//     <i>  Selects Port Name
+//     <o3> Bit <0-15>
+//     <i>  Selects Port Bit
+//   </e>
+#define RTE_SDIO_WP_EN                  0
+#define RTE_SDIO_WP_ACTIVE              1
+#define RTE_SDIO_WP_PORT                GPIO_PORT(0)
+#define RTE_SDIO_WP_PIN                 10
+
+//   <h> DMA
+//     <o0> Number <2=>2
+//     <i>  Selects DMA Number (only DMA2 can be used)
+//     <o1> Channel <4=>4
+//     <i>  Selects DMA Channel (only Channel 4 can be used)
+//     <o2> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//     <i>  Selects DMA Priority
+//   </h>
+#define RTE_SDIO_DMA_NUMBER             2
+#define RTE_SDIO_DMA_CHANNEL            4
+#define RTE_SDIO_DMA_PRIORITY           0
+
+// </e>
+
+
+// <e> CAN1 (Controller Area Network 1) [Driver_CAN1]
+// <i> Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN
+#define RTE_CAN1                        0
+
+//   <o> CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0
+#define RTE_CAN1_RX_PORT_ID             0
+#if    (RTE_CAN1_RX_PORT_ID == 0)
+#define RTE_CAN1_RX_PORT                GPIOA
+#define RTE_CAN1_RX_BIT                 11
+#elif  (RTE_CAN1_RX_PORT_ID == 1)
+#define RTE_CAN1_RX_PORT                GPIOB
+#define RTE_CAN1_RX_BIT                 8
+#elif  (RTE_CAN1_RX_PORT_ID == 2)
+#define RTE_CAN1_RX_PORT                GPIOD
+#define RTE_CAN1_RX_BIT                 0
+#else
+#error "Invalid CAN1_RX Pin Configuration!"
+#endif
+
+//   <o> CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1
+#define RTE_CAN1_TX_PORT_ID             0
+#if    (RTE_CAN1_TX_PORT_ID == 0)
+#define RTE_CAN1_TX_PORT                GPIOA
+#define RTE_CAN1_TX_BIT                 12
+#elif  (RTE_CAN1_TX_PORT_ID == 1)
+#define RTE_CAN1_TX_PORT                GPIOB
+#define RTE_CAN1_TX_BIT                 9
+#elif  (RTE_CAN1_TX_PORT_ID == 2)
+#define RTE_CAN1_TX_PORT                GPIOD
+#define RTE_CAN1_TX_BIT                 1
+#else
+#error "Invalid CAN1_TX Pin Configuration!"
+#endif
+
+// </e>
+
+
+// <e> CAN2 (Controller Area Network 2) [Driver_CAN2]
+// <i> Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN
+#define RTE_CAN2                        0
+
+//   <o> CAN2_RX Pin <0=>PB5 <1=>PB12
+#define RTE_CAN2_RX_PORT_ID             0
+#if    (RTE_CAN2_RX_PORT_ID == 0)
+#define RTE_CAN2_RX_PORT                GPIOB
+#define RTE_CAN2_RX_BIT                 5
+#elif  (RTE_CAN2_RX_PORT_ID == 1)
+#define RTE_CAN2_RX_PORT                GPIOB
+#define RTE_CAN2_RX_BIT                 12
+#else
+#error "Invalid CAN2_RX Pin Configuration!"
+#endif
+
+//   <o> CAN2_TX Pin <0=>PB6 <1=>PB13
+#define RTE_CAN2_TX_PORT_ID             0
+#if    (RTE_CAN2_TX_PORT_ID == 0)
+#define RTE_CAN2_TX_PORT                GPIOB
+#define RTE_CAN2_TX_BIT                 6
+#elif  (RTE_CAN2_TX_PORT_ID == 1)
+#define RTE_CAN2_TX_PORT                GPIOB
+#define RTE_CAN2_TX_BIT                 13
+#else
+#error "Invalid CAN2_TX Pin Configuration!"
+#endif
+
+// </e>
+
+
+// <e> ETH (Ethernet Interface) [Driver_ETH_MAC0]
+// <i> Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC
+#define RTE_ETH                         0
+
+//   <e> MII (Media Independent Interface)
+//   <i> Enable Media Independent Interface pin configuration
+#define RTE_ETH_MII                     0
+
+//     <o> ETH_MII_TX_CLK Pin <0=>PC3
+#define RTE_ETH_MII_TX_CLK_PORT_ID      0
+#if    (RTE_ETH_MII_TX_CLK_PORT_ID == 0)
+#define RTE_ETH_MII_TX_CLK_PORT         GPIOC
+#define RTE_ETH_MII_TX_CLK_PIN          3
+#else
+#error "Invalid ETH_MII_TX_CLK Pin Configuration!"
+#endif
+//     <o> ETH_MII_TXD0 Pin <0=>PB12
+#define RTE_ETH_MII_TXD0_PORT_ID        0
+#if    (RTE_ETH_MII_TXD0_PORT_ID == 0)
+#define RTE_ETH_MII_TXD0_PORT           GPIOB
+#define RTE_ETH_MII_TXD0_PIN            12
+#else
+#error "Invalid ETH_MII_TXD0 Pin Configuration!"
+#endif
+//     <o> ETH_MII_TXD1 Pin <0=>PB13
+#define RTE_ETH_MII_TXD1_PORT_ID        0
+#if    (RTE_ETH_MII_TXD1_PORT_ID == 0)
+#define RTE_ETH_MII_TXD1_PORT           GPIOB
+#define RTE_ETH_MII_TXD1_PIN            13
+#else
+#error "Invalid ETH_MII_TXD1 Pin Configuration!"
+#endif
+//     <o> ETH_MII_TXD2 Pin <0=>PC2
+#define RTE_ETH_MII_TXD2_PORT_ID        0
+#if    (RTE_ETH_MII_TXD2_PORT_ID == 0)
+#define RTE_ETH_MII_TXD2_PORT           GPIOC
+#define RTE_ETH_MII_TXD2_PIN            2
+#else
+#error "Invalid ETH_MII_TXD2 Pin Configuration!"
+#endif
+//     <o> ETH_MII_TXD3 Pin <0=>PB8
+#define RTE_ETH_MII_TXD3_PORT_ID        0
+#if    (RTE_ETH_MII_TXD3_PORT_ID == 0)
+#define RTE_ETH_MII_TXD3_PORT           GPIOB
+#define RTE_ETH_MII_TXD3_PIN            8
+#else
+#error "Invalid ETH_MII_TXD3 Pin Configuration!"
+#endif
+//     <o> ETH_MII_TX_EN Pin <0=>PB11
+#define RTE_ETH_MII_TX_EN_PORT_ID       0
+#if    (RTE_ETH_MII_TX_EN_PORT_ID == 0)
+#define RTE_ETH_MII_TX_EN_PORT          GPIOB
+#define RTE_ETH_MII_TX_EN_PIN           11
+#else
+#error "Invalid ETH_MII_TX_EN Pin Configuration!"
+#endif
+//     <o> ETH_MII_RX_CLK Pin <0=>PA1
+#define RTE_ETH_MII_RX_CLK_PORT_ID        0
+#if    (RTE_ETH_MII_RX_CLK_PORT_ID == 0)
+#define RTE_ETH_MII_RX_CLK_PORT         GPIOA
+#define RTE_ETH_MII_RX_CLK_PIN          1
+#else
+#error "Invalid ETH_MII_RX_CLK Pin Configuration!"
+#endif
+//     <o> ETH_MII_RXD0 Pin <0=>PC4
+#define RTE_ETH_MII_RXD0_DEF            0
+
+//     <o> ETH_MII_RXD1 Pin <0=>PC5
+#define RTE_ETH_MII_RXD1_DEF            0
+
+//     <o> ETH_MII_RXD2 Pin <0=>PB0
+#define RTE_ETH_MII_RXD2_DEF            0
+
+//     <o> ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12
+#define RTE_ETH_MII_RXD3_DEF            0
+
+//     <o> ETH_MII_RX_DV Pin <0=>PA7
+#define RTE_ETH_MII_RX_DV_DEF           0
+
+//     <o> ETH_MII_RX_ER Pin <0=>PB10
+#define RTE_ETH_MII_RX_ER_PORT_ID       0
+#if    (RTE_ETH_MII_RX_ER_PORT_ID == 0)
+#define RTE_ETH_MII_RX_ER_PORT          GPIOB
+#define RTE_ETH_MII_RX_ER_PIN           10
+#else
+#error "Invalid ETH_MII_RX_ER Pin Configuration!"
+#endif
+//     <o> ETH_MII_CRS Pin <0=>PA0
+#define RTE_ETH_MII_CRS_PORT_ID       0
+#if    (RTE_ETH_MII_CRS_PORT_ID == 0)
+#define RTE_ETH_MII_CRS_PORT            GPIOA
+#define RTE_ETH_MII_CRS_PIN             0
+#else
+#error "Invalid ETH_MII_CRS Pin Configuration!"
+#endif
+//     <o> ETH_MII_COL Pin <0=>PA3
+#define RTE_ETH_MII_COL_PORT_ID       0
+#if    (RTE_ETH_MII_COL_PORT_ID == 0)
+#define RTE_ETH_MII_COL_PORT            GPIOA
+#define RTE_ETH_MII_COL_PIN             3
+#else
+#error "Invalid ETH_MII_COL Pin Configuration!"
+#endif
+
+//     <e> Ethernet MAC I/O remapping
+//     <i> Remap Ethernet pins
+#define RTE_ETH_MII_REMAP               0
+
+//     <o> ETH_MII_RXD0 Pin <1=>PD9
+#define RTE_ETH_MII_RXD0_REMAP          1
+
+//     <o> ETH_MII_RXD1 Pin <1=>PD10
+#define RTE_ETH_MII_RXD1_REMAP          1
+
+//     <o> ETH_MII_RXD2 Pin <1=>PD11
+#define RTE_ETH_MII_RXD2_REMAP          1
+
+//       <o> ETH_MII_RXD3 Pin <1=>PD12
+#define RTE_ETH_MII_RXD3_REMAP          1
+
+//       <o> ETH_MII_RX_DV Pin <1=>PD8
+#define RTE_ETH_MII_RX_DV_REMAP         1
+//     </e>
+
+//   </e>
+
+#if    ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0))
+#define RTE_ETH_MII_RXD0_PORT           GPIOC
+#define RTE_ETH_MII_RXD0_PIN            4
+#elif  ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1))
+#define RTE_ETH_MII_RXD0_PORT           GPIOD
+#define RTE_ETH_MII_RXD0_PIN            9
+#else
+#error "Invalid ETH_MII_RXD0 Pin Configuration!"
+#endif
+
+#if   ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0))
+#define RTE_ETH_MII_RXD1_PORT           GPIOC
+#define RTE_ETH_MII_RXD1_PIN            5
+#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1))
+#define RTE_ETH_MII_RXD1_PORT           GPIOD
+#define RTE_ETH_MII_RXD1_PIN            10
+#else
+#error "Invalid ETH_MII_RXD1 Pin Configuration!"
+#endif
+
+#if   ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0))
+#define RTE_ETH_MII_RXD2_PORT           GPIOB
+#define RTE_ETH_MII_RXD2_PIN            0
+#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1))
+#define RTE_ETH_MII_RXD2_PORT           GPIOD
+#define RTE_ETH_MII_RXD2_PIN            11
+#else
+#error "Invalid ETH_MII_RXD2 Pin Configuration!"
+#endif
+
+#if   ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0))
+#define RTE_ETH_MII_RXD3_PORT           GPIOB
+#define RTE_ETH_MII_RXD3_PIN            1
+#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1))
+#define RTE_ETH_MII_RXD3_PORT           GPIOD
+#define RTE_ETH_MII_RXD3_PIN            12
+#else
+#error "Invalid ETH_MII_RXD3 Pin Configuration!"
+#endif
+
+#if   ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0))
+#define RTE_ETH_MII_RX_DV_PORT          GPIOA
+#define RTE_ETH_MII_RX_DV_PIN           7
+#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1))
+#define RTE_ETH_MII_RX_DV_PORT          GPIOD
+#define RTE_ETH_MII_RX_DV_PIN           8
+#else
+#error "Invalid ETH_MII_RX_DV Pin Configuration!"
+#endif
+
+//   <e> RMII (Reduced Media Independent Interface)
+#define RTE_ETH_RMII                    0
+
+//     <o> ETH_RMII_TXD0 Pin <0=>PB12
+#define RTE_ETH_RMII_TXD0_PORT_ID       0
+#if    (RTE_ETH_RMII_TXD0_PORT_ID == 0)
+#define RTE_ETH_RMII_TXD0_PORT          GPIOB
+#define RTE_ETH_RMII_TXD0_PIN           12
+#else
+#error "Invalid ETH_RMII_TXD0 Pin Configuration!"
+#endif
+//     <o> ETH_RMII_TXD1 Pin <0=>PB13
+#define RTE_ETH_RMII_TXD1_PORT_ID       0
+#if    (RTE_ETH_RMII_TXD1_PORT_ID == 0)
+#define RTE_ETH_RMII_TXD1_PORT          GPIOB
+#define RTE_ETH_RMII_TXD1_PIN           13
+#else
+#error "Invalid ETH_RMII_TXD1 Pin Configuration!"
+#endif
+//     <o> ETH_RMII_TX_EN Pin <0=>PB11
+#define RTE_ETH_RMII_TX_EN_PORT_ID      0
+#if    (RTE_ETH_RMII_TX_EN_PORT_ID == 0)
+#define RTE_ETH_RMII_TX_EN_PORT         GPIOB
+#define RTE_ETH_RMII_TX_EN_PIN          11
+#else
+#error "Invalid ETH_RMII_TX_EN Pin Configuration!"
+#endif
+//     <o> ETH_RMII_RXD0 Pin <0=>PC4
+#define RTE_ETH_RMII_RXD0_DEF           0
+
+//     <o> ETH_RMII_RXD1 Pin <0=>PC5
+#define RTE_ETH_RMII_RXD1_DEF           0
+
+//     <o> ETH_RMII_REF_CLK Pin <0=>PA1
+#define RTE_ETH_RMII_REF_CLK_PORT_ID    0
+#if    (RTE_ETH_RMII_REF_CLK_PORT_ID == 0)
+#define RTE_ETH_RMII_REF_CLK_PORT       GPIOA
+#define RTE_ETH_RMII_REF_CLK_PIN        1
+#else
+#error "Invalid ETH_RMII_REF_CLK Pin Configuration!"
+#endif
+//     <o> ETH_RMII_CRS_DV Pin <0=>PA7
+#define RTE_ETH_RMII_CRS_DV_DEF     0
+
+//   <e> Ethernet MAC I/O remapping
+//   <i> Remap Ethernet pins
+#define RTE_ETH_RMII_REMAP              0
+//     <o> ETH_RMII_RXD0 Pin <1=>PD9
+#define RTE_ETH_RMII_RXD0_REMAP         1
+
+//     <o> ETH_RMII_RXD1 Pin <1=>PD10
+#define RTE_ETH_RMII_RXD1_REMAP         1
+
+//     <o> ETH_RMII_CRS_DV Pin <1=>PD8
+#define RTE_ETH_RMII_CRS_DV_REMAP       1
+//   </e>
+
+#if    ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0))
+#define RTE_ETH_RMII_RXD0_PORT          GPIOC
+#define RTE_ETH_RMII_RXD0_PIN           4
+#elif  ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1))
+#define RTE_ETH_RMII_RXD0_PORT          GPIOD
+#define RTE_ETH_RMII_RXD0_PIN           9
+#else
+#error "Invalid ETH_RMII_RXD0 Pin Configuration!"
+#endif
+
+#if    ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0))
+#define RTE_ETH_RMII_RXD1_PORT          GPIOC
+#define RTE_ETH_RMII_RXD1_PIN           5
+#elif  ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1))
+#define RTE_ETH_RMII_RXD1_PORT          GPIOD
+#define RTE_ETH_RMII_RXD1_PIN           10
+#else
+#error "Invalid ETH_RMII_RXD1 Pin Configuration!"
+#endif
+
+#if    ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0))
+#define RTE_ETH_RMII_CRS_DV_PORT        GPIOA
+#define RTE_ETH_RMII_CRS_DV_PIN         7
+#elif  ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1))
+#define RTE_ETH_RMII_CRS_DV_PORT        GPIOD
+#define RTE_ETH_RMII_CRS_DV_PIN         8
+#else
+#error "Invalid ETH_RMII_CRS_DV Pin Configuration!"
+#endif
+
+//   </e>
+
+//   <h> Management Data Interface
+//     <o> ETH_MDC Pin <0=>PC1
+#define RTE_ETH_MDI_MDC_PORT_ID         0
+#if    (RTE_ETH_MDI_MDC_PORT_ID == 0)
+#define RTE_ETH_MDI_MDC_PORT            GPIOC
+#define RTE_ETH_MDI_MDC_PIN             1
+#else
+#error "Invalid ETH_MDC Pin Configuration!"
+#endif
+//     <o> ETH_MDIO Pin <0=>PA2
+#define RTE_ETH_MDI_MDIO_PORT_ID        0
+#if    (RTE_ETH_MDI_MDIO_PORT_ID == 0)
+#define RTE_ETH_MDI_MDIO_PORT           GPIOA
+#define RTE_ETH_MDI_MDIO_PIN            2
+#else
+#error "Invalid ETH_MDIO Pin Configuration!"
+#endif
+//   </h>
+
+//   <o> Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled
+#define RTE_ETH_REF_CLOCK_ID            0
+#if    (RTE_ETH_REF_CLOCK_ID == 0)
+#define RTE_ETH_REF_CLOCK               0
+#elif  (RTE_ETH_REF_CLOCK_ID == 1)
+#define RTE_ETH_REF_CLOCK               1
+#else
+#error "Invalid MCO Ethernet Reference Clock Configuration!"
+#endif
+// </e>
+
+
+// <e> USB Device Full-speed
+// <i> Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
+#define RTE_USB_DEVICE                  0
+
+//     <e> CON On/Off Pin
+//     <i> Configure Pin for driving D+ pull-up
+//     <i> GPIO Pxy (x = A..G, y = 0..15)
+//       <o1> Active State <0=>Low <1=>High
+//       <i>  Selects Active State Logical Level
+//       <o2> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//       <i>  Selects Port Name
+//       <o3> Bit <0-15>
+//       <i>  Selects Port Bit
+//     </e>
+#define RTE_USB_DEVICE_CON_PIN          1
+#define RTE_USB_DEVICE_CON_ACTIVE       0
+#define RTE_USB_DEVICE_CON_PORT         GPIO_PORT(1)
+#define RTE_USB_DEVICE_CON_BIT          14
+
+//   </e>
+
+
+// <e> USB OTG Full-speed
+#define RTE_USB_OTG_FS                  0
+
+//   <e> Host [Driver_USBH0]
+//   <i> Configuration settings for Driver_USBH0 in component ::Drivers:USB Host
+
+#define RTE_USB_OTG_FS_HOST             0
+
+//     <e> VBUS Power On/Off Pin
+//     <i> Configure Pin for driving VBUS
+//     <i> GPIO Pxy (x = A..G, y = 0..15)
+//       <o1> Active State <0=>Low <1=>High
+//       <i>  Selects Active State Logical Level
+//       <o2> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//       <i>  Selects Port Name
+//       <o3> Bit <0-15>
+//       <i>  Selects Port Bit
+//     </e>
+#define RTE_OTG_FS_VBUS_PIN             1
+#define RTE_OTG_FS_VBUS_ACTIVE          0
+#define RTE_OTG_FS_VBUS_PORT            GPIO_PORT(2)
+#define RTE_OTG_FS_VBUS_BIT             9
+
+//     <e> Overcurrent Detection Pin
+//     <i> Configure Pin for overcurrent detection
+//     <i> GPIO Pxy (x = A..G, y = 0..15)
+//       <o1> Active State <0=>Low <1=>High
+//       <i>  Selects Active State Logical Level
+//       <o2> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG
+//       <i>  Selects Port Name
+//       <o3> Bit <0-15>
+//       <i>  Selects Port Bit
+//     </e>
+#define RTE_OTG_FS_OC_PIN               1
+#define RTE_OTG_FS_OC_ACTIVE            0
+#define RTE_OTG_FS_OC_PORT              GPIO_PORT(4)
+#define RTE_OTG_FS_OC_BIT               1
+//   </e>
+
+// </e>
+
+
+#endif  /* __RTE_DEVICE_H */
diff --git a/RTE/Device/STM32F107VC/startup_stm32f10x_cl.s.update@1.0.1 b/RTE/Device/STM32F107VC/startup_stm32f10x_cl.s.update@1.0.1
new file mode 100644
index 0000000..e40f734
--- /dev/null
+++ b/RTE/Device/STM32F107VC/startup_stm32f10x_cl.s.update@1.0.1
@@ -0,0 +1,369 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f10x_cl.s
+;* Author             : MCD Application Team
+;* Version            : V3.5.1
+;* Date               : 08-September-2021
+;* Description        : STM32F10x Connectivity line devices vector table for MDK-ARM 
+;*                      toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+;*
+;* Copyright (c) 2011 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler            ; Window Watchdog
+                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler          ; Tamper
+                DCD     RTC_IRQHandler             ; RTC
+                DCD     FLASH_IRQHandler           ; Flash
+                DCD     RCC_IRQHandler             ; RCC
+                DCD     EXTI0_IRQHandler           ; EXTI Line 0
+                DCD     EXTI1_IRQHandler           ; EXTI Line 1
+                DCD     EXTI2_IRQHandler           ; EXTI Line 2
+                DCD     EXTI3_IRQHandler           ; EXTI Line 3
+                DCD     EXTI4_IRQHandler           ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler          ; ADC1 and ADC2
+                DCD     CAN1_TX_IRQHandler         ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler        ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
+                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
+                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
+                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler            ; TIM2
+                DCD     TIM3_IRQHandler            ; TIM3
+                DCD     TIM4_IRQHandler            ; TIM4
+                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler         ; I2C1 Error
+                DCD     SPI1_IRQHandler            ; SPI1
+                DCD     SPI2_IRQHandler            ; SPI2
+                DCD     USART1_IRQHandler          ; USART1
+                DCD     USART2_IRQHandler          ; USART2
+                DCD     USART3_IRQHandler          ; USART3
+                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
+                DCD     RTCAlarm_IRQHandler        ; RTC alarm through EXTI line
+                DCD     OTG_FS_WKUP_IRQHandler     ; USB OTG FS Wakeup through EXTI line
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     TIM5_IRQHandler            ; TIM5
+                DCD     SPI3_IRQHandler            ; SPI3
+                DCD     UART4_IRQHandler           ; UART4
+                DCD     UART5_IRQHandler           ; UART5
+                DCD     TIM6_IRQHandler            ; TIM6
+                DCD     TIM7_IRQHandler            ; TIM7
+                DCD     DMA2_Channel1_IRQHandler   ; DMA2 Channel1
+                DCD     DMA2_Channel2_IRQHandler   ; DMA2 Channel2
+                DCD     DMA2_Channel3_IRQHandler   ; DMA2 Channel3
+                DCD     DMA2_Channel4_IRQHandler   ; DMA2 Channel4
+                DCD     DMA2_Channel5_IRQHandler   ; DMA2 Channel5
+                DCD     ETH_IRQHandler             ; Ethernet
+                DCD     ETH_WKUP_IRQHandler        ; Ethernet Wakeup through EXTI line
+                DCD     CAN2_TX_IRQHandler         ; CAN2 TX
+                DCD     CAN2_RX0_IRQHandler        ; CAN2 RX0
+                DCD     CAN2_RX1_IRQHandler        ; CAN2 RX1
+                DCD     CAN2_SCE_IRQHandler        ; CAN2 SCE
+                DCD     OTG_FS_IRQHandler          ; USB OTG FS
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler            [WEAK]
+                EXPORT  PVD_IRQHandler             [WEAK]
+                EXPORT  TAMPER_IRQHandler          [WEAK]
+                EXPORT  RTC_IRQHandler             [WEAK]
+                EXPORT  FLASH_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler             [WEAK]
+                EXPORT  EXTI0_IRQHandler           [WEAK]
+                EXPORT  EXTI1_IRQHandler           [WEAK]
+                EXPORT  EXTI2_IRQHandler           [WEAK]
+                EXPORT  EXTI3_IRQHandler           [WEAK]
+                EXPORT  EXTI4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
+                EXPORT  ADC1_2_IRQHandler          [WEAK]
+                EXPORT  CAN1_TX_IRQHandler         [WEAK]
+                EXPORT  CAN1_RX0_IRQHandler        [WEAK]
+                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
+                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
+                EXPORT  EXTI9_5_IRQHandler         [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
+                EXPORT  TIM1_UP_IRQHandler         [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
+                EXPORT  TIM1_CC_IRQHandler         [WEAK]
+                EXPORT  TIM2_IRQHandler            [WEAK]
+                EXPORT  TIM3_IRQHandler            [WEAK]
+                EXPORT  TIM4_IRQHandler            [WEAK]
+                EXPORT  I2C1_EV_IRQHandler         [WEAK]
+                EXPORT  I2C1_ER_IRQHandler         [WEAK]
+                EXPORT  I2C2_EV_IRQHandler         [WEAK]
+                EXPORT  I2C2_ER_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler            [WEAK]
+                EXPORT  SPI2_IRQHandler            [WEAK]
+                EXPORT  USART1_IRQHandler          [WEAK]
+                EXPORT  USART2_IRQHandler          [WEAK]
+                EXPORT  USART3_IRQHandler          [WEAK]
+                EXPORT  EXTI15_10_IRQHandler       [WEAK]
+                EXPORT  RTCAlarm_IRQHandler        [WEAK]
+                EXPORT  OTG_FS_WKUP_IRQHandler     [WEAK]
+                EXPORT  TIM5_IRQHandler            [WEAK]
+                EXPORT  SPI3_IRQHandler            [WEAK]
+                EXPORT  UART4_IRQHandler           [WEAK]
+                EXPORT  UART5_IRQHandler           [WEAK]
+                EXPORT  TIM6_IRQHandler            [WEAK]
+                EXPORT  TIM7_IRQHandler            [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
+                EXPORT  ETH_IRQHandler             [WEAK]
+                EXPORT  ETH_WKUP_IRQHandler        [WEAK]
+                EXPORT  CAN2_TX_IRQHandler         [WEAK]
+                EXPORT  CAN2_RX0_IRQHandler        [WEAK]
+                EXPORT  CAN2_RX1_IRQHandler        [WEAK]
+                EXPORT  CAN2_SCE_IRQHandler        [WEAK]
+                EXPORT  OTG_FS_IRQHandler          [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+OTG_FS_WKUP_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+CAN2_TX_IRQHandler
+CAN2_RX0_IRQHandler
+CAN2_RX1_IRQHandler
+CAN2_SCE_IRQHandler
+OTG_FS_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
diff --git a/RTE/Device/STM32F107VC/system_stm32f10x.c.update@1.0.1 b/RTE/Device/STM32F107VC/system_stm32f10x.c.update@1.0.1
new file mode 100644
index 0000000..9e31f67
--- /dev/null
+++ b/RTE/Device/STM32F107VC/system_stm32f10x.c.update@1.0.1
@@ -0,0 +1,1092 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V3.5.1
+  * @date    08-September-2021
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2011 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depending on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef  STM32F10X_CL
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18;
+      
+      if (pllmull != 0x0D)
+      {
+         pllmull += 2;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13 / 2; 
+      }
+            
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        
+        if (prediv1source == 0)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *         and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+    if (HSE_VALUE <= 24000000)
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+	}
+	else
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+	}
+#endif /* STM32F10X_CL */
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }   
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+
+	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+#else    
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL7); 
+#else     
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
diff --git a/RTE/_R_el/RTE_Components.h b/RTE/_R_el/RTE_Components.h
index 5550143..1c77a1e 100644
--- a/RTE/_R_el/RTE_Components.h
+++ b/RTE/_R_el/RTE_Components.h
@@ -3,7 +3,7 @@
  * Auto generated Run-Time-Environment Configuration File
  *      *** Do not modify ! ***
  *
- * Project: 'Etape_0' 
+ * Project: 'Etape_3' 
  * Target:  'Réel' 
  */
 
diff --git a/RTE/_Simul_/RTE_Components.h b/RTE/_Simul_/RTE_Components.h
index 74bc5dc..e52ddb9 100644
--- a/RTE/_Simul_/RTE_Components.h
+++ b/RTE/_Simul_/RTE_Components.h
@@ -1,9 +1,9 @@
 
 /*
- * Auto generated Run-Time-Environment Component Configuration File
+ * Auto generated Run-Time-Environment Configuration File
  *      *** Do not modify ! ***
  *
- * Project: 'Etape_0' 
+ * Project: 'Etape_3' 
  * Target:  'Simulé' 
  */
 
@@ -17,4 +17,5 @@
 #define CMSIS_device_header "stm32f10x.h"
 
 
+
 #endif /* RTE_COMPONENTS_H */
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index 0000000..45ea5db
--- /dev/null
+++ b/capteur_signals.uvl
@@ -0,0 +1,28 @@
+[Signal 1]
+DispName=(portA & 0x00000100) >> 8
+PlotType=1
+Color=255
+ValHex=0
+MinDec=0
+MinVal=0.
+MaxDec=0
+MaxVal=65535.
+Mask=256
+Offset=8
+Adaptive=0
+DispNumber=1
+HeightFactor=0.5
+[Signal 2]
+DispName=(portB & 0x00000400) >> 10
+PlotType=1
+Color=32768
+ValHex=0
+MinDec=0
+MinVal=0.
+MaxDec=0
+MaxVal=65535.
+Mask=1024
+Offset=10
+Adaptive=0
+DispNumber=2
+HeightFactor=0.5