501 lines
15 KiB
Text
501 lines
15 KiB
Text
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ARM Macro Assembler Page 1
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1 00000000 ;*******************************************************
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********************
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2 00000000 THUMB
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3 00000000 REQUIRE8
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4 00000000 PRESERVE8
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5 00000000
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6 00000000 ;*******************************************************
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*******************
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7 00000000 ; Fichier Vierge.asm
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8 00000000 ; Auteur : V.MAHOUT
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9 00000000 ; Date : 12/11/2013
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10 00000000 ;*******************************************************
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*******************
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11 00000000
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12 00000000 ;***************IMPORT/EXPORT***************************
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*******************
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13 00000000
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14 00000000 EXPORT Set_SCLK
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15 00000000 EXPORT Reset_SCLK
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16 00000000 EXPORT DriverGlobal
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17 00000000
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18 00000000 ;*******************************************************
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*******************
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19 00000000
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20 00000000
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21 00000000
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22 00000000 ;***************CONSTANTES******************************
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*******************
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23 00000000
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24 00000000 include REG_UTILES.inc
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1 00000000
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2 00000000 ;**************************************
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3 00000000 ; Les adresess utiles
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4 00000000 ;***************************************
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5 00000000
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6 00000000
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7 00000000 ;**************************************
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8 00000000 ; Affectation des bits GPIO
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9 00000000 ;***************************************
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10 00000000 ; GSLCK..... PA0
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11 00000000 ; DSPRG..... PA1
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12 00000000 ; BLANK..... PA2
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13 00000000 ; XLAT...... PA3
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14 00000000 ; VPRG...... PA4
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15 00000000 ; SCLK...... PA5
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16 00000000 ; SIN1...... PA7
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17 00000000 ;Capteur.....PA8
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18 00000000
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19 00000000 ;LED.........PB10
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20 00000000 ;****************************************/
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21 00000000
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22 00000000
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23 00000000
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24 00000000 40010800
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GPIOBASEA
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EQU 0X40010800
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25 00000000 40010C00
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GPIOBASEB
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EQU 0X40010C00
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ARM Macro Assembler Page 2
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26 00000000
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27 00000000 00000008
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OffsetInput
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EQU 0x08
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28 00000000 0000000C
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OffsetOutput
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EQU 0x0C
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29 00000000 00000010
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OffsetSet
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EQU 0x10
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30 00000000 00000014
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OffsetReset
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EQU 0x14
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31 00000000
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32 00000000
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33 00000000 00000080
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MaskSerial_In1
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equ 0x80
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34 00000000 00000080
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MaskSerial_Dots
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equ 0x80
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35 00000000 00000010
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MaskVprg
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equ 0x10
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36 00000000 00000008
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MaskXlat
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equ 0x08
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37 00000000 00000004
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MaskBlank
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equ 0x04
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38 00000000 00000020
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MaskSclk
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equ 0x20
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39 00000000 00000002
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MaskDsprg
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equ 0x02
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40 00000000 00000001
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MaskGsclk
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equ 0x01
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41 00000000
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42 00000000
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43 00000000 E000ED08
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SCB_VTOR
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EQU 0xE000ED08
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44 00000000 40012C10
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TIM1_SR EQU 0x40012c10
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45 00000000 40012C24
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TIM1_CNT
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EQU 0x40012c24
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46 00000000 4000082C
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TIM4_ARR
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EQU 0x4000082C
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47 00000000 40000810
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TIM4_SR EQU 0x40000810
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48 00000000
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49 00000000
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50 00000000
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51 00000000
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52 00000000
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ARM Macro Assembler Page 3
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53 00000000 END
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25 00000000
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26 00000000 ;*******************************************************
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*******************
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27 00000000
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28 00000000
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29 00000000 ;***************VARIABLES*******************************
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*******************
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30 00000000 AREA MesDonnees, data, readwrite
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31 00000000 ;*******************************************************
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*******************
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32 00000000
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33 00000000
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34 00000000 00 01 00
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Barette1
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DCB 0,1,0
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35 00000003 00 01 00 DCB 0,1,0
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36 00000006 00 01 00 DCB 0,1,0
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37 00000009 00 01 00 DCB 0,1,0
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38 0000000C 00 01 00 DCB 0,1,0
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39 0000000F 00 01 00 DCB 0,1,0
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40 00000012 00 01 00 DCB 0,1,0
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41 00000015
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42 00000015
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43 00000015
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44 00000015 ;*******************************************************
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*******************
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45 00000015
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46 00000015
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47 00000015
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48 00000015 ;***************CODE************************************
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*******************
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49 00000015 AREA moncode, code, readonly
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50 00000000 ;*******************************************************
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*******************
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51 00000000
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52 00000000 Set_SCLK
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PROC
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53 00000000 B407 PUSH {R0-R2} ;On stocke R0 <20> R2
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54 00000002 490D LDR R1,=GPIOBASEA ;R1 -> Adresse de
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GPIOA
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55 00000004 898A LDRH R2,[R1,#OffsetOutput] ;Valeur <20>
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l'adresse d'ODR :
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R2 = GPIOA->ODR
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56 00000006 F042 0220 ORR R2, R2,#(0x01 << 5) ;similaire
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<20> GPIOA->ODR |= (1<
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<5)
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57 0000000A 818A STRH R2,[R1,#OffsetOutput] ;Etat du
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port B (R5) stock<63>
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dans ODR
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58 0000000C 4770 BX LR ;Retour
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59 0000000E
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60 0000000E ENDP
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61 0000000E
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62 0000000E Reset_SCLK
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PROC
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63 0000000E B407 PUSH {R0-R2} ;On stocke R0 <20> R2
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64 00000010 4909 LDR R1,=GPIOBASEA ;R1 -> Adresse de
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GPIOA
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ARM Macro Assembler Page 4
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65 00000012 898A LDRH R2,[R1,#OffsetOutput] ;Valeur <20>
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l'adresse d'ODR :
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R2 = GPIOA->ODR
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66 00000014 F022 0220 AND R2, R2,#~(0x01 << 5) ;similaire
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<20> GPIOA->ODR &= ~(
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1<<5)
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67 00000018 818A STRH R2,[R1,#OffsetOutput] ;Etat du
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port B (R5) stock<63>
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dans ODR
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68 0000001A 4770 BX LR ;Retour
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69 0000001C
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70 0000001C ENDP
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71 0000001C
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72 0000001C ;*******************************************************
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*********************
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73 0000001C ;R6 = NBLed
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74 0000001C ;R7 = *ValCourante
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75 0000001C ;R8 = ValCourante[NBLed]
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76 0000001C ;*******************************************************
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*********************
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77 0000001C DriverGlobal
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PROC
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78 0000001C F7FF FFFE BL Set_SCLK ;
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79 00000020 F04F 0600 MOV R6, #0 ;
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80 00000024 WHILE_NBLED
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81 00000024 ;Pour NbLed = 1 <20> 48
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82 00000024 4F05 LDR R7,=Barette1 ;On recup<75>re l'adr
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esse de base
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83 00000026 F817 8006 LDRB R8,[R7,R6] ;R8 = ValCourante[.
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..NBLed]
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84 0000002A
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85 0000002A EA4F 6808 LSL R8,#24 ;ValCourante[NBLed]
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<<24
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86 0000002E
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87 0000002E F106 0601 ADD R6, R6, #1 ;On incr<63>mente R6
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88 00000032 2E2F CMP R6, #47 ; SI R6==47 alors o
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n arr<72>te la boucle
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89 00000034 D1F6 BNE WHILE_NBLED
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90 00000036 ENDP
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91 00000036
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92 00000036 ;*******************************************************
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*******************
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93 00000036 END
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00 00 40010800
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00000000
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Command Line: --debug --xref --diag_suppress=9931,A1950W --cpu=Cortex-M3 --depe
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nd=.\objects\fonctionetape2.d -o.\objects\fonctionetape2.o -I.\RTE\Device\STM32
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F103RB -I.\RTE\_Simul_ -IC:\Users\alzyo\AppData\Local\Arm\Packs\ARM\CMSIS\5.9.0
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\CMSIS\Core\Include -IC:\Users\alzyo\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP
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\2.4.0\Device\Include --predefine="__EVAL SETA 1" --predefine="__MICROLIB SETA
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1" --predefine="__UVISION_VERSION SETA 538" --predefine="_RTE_ SETA 1" --predef
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ine="STM32F10X_MD SETA 1" --predefine="_RTE_ SETA 1" --predefine="STM32F10X_MD
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SETA 1" --list=.\listings\fonctionetape2.lst FonctionEtape2.asm
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ARM Macro Assembler Page 1 Alphabetic symbol ordering
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Relocatable symbols
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Barette1 00000000
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Symbol: Barette1
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Definitions
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At line 34 in file FonctionEtape2.asm
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Uses
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At line 82 in file FonctionEtape2.asm
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Comment: Barette1 used once
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MesDonnees 00000000
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Symbol: MesDonnees
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Definitions
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At line 30 in file FonctionEtape2.asm
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Uses
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None
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Comment: MesDonnees unused
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2 symbols
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ARM Macro Assembler Page 1 Alphabetic symbol ordering
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Relocatable symbols
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DriverGlobal 0000001C
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Symbol: DriverGlobal
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Definitions
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At line 77 in file FonctionEtape2.asm
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Uses
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At line 16 in file FonctionEtape2.asm
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Comment: DriverGlobal used once
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Reset_SCLK 0000000E
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Symbol: Reset_SCLK
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Definitions
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At line 62 in file FonctionEtape2.asm
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Uses
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At line 15 in file FonctionEtape2.asm
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Comment: Reset_SCLK used once
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Set_SCLK 00000000
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Symbol: Set_SCLK
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Definitions
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At line 52 in file FonctionEtape2.asm
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Uses
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At line 14 in file FonctionEtape2.asm
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At line 78 in file FonctionEtape2.asm
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WHILE_NBLED 00000024
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Symbol: WHILE_NBLED
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Definitions
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At line 80 in file FonctionEtape2.asm
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Uses
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At line 89 in file FonctionEtape2.asm
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Comment: WHILE_NBLED used once
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moncode 00000000
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Symbol: moncode
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Definitions
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At line 49 in file FonctionEtape2.asm
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Uses
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None
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Comment: moncode unused
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5 symbols
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ARM Macro Assembler Page 1 Alphabetic symbol ordering
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Absolute symbols
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GPIOBASEA 40010800
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Symbol: GPIOBASEA
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Definitions
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At line 24 in file REG_UTILES.inc
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Uses
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At line 54 in file FonctionEtape2.asm
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At line 64 in file FonctionEtape2.asm
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GPIOBASEB 40010C00
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Symbol: GPIOBASEB
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Definitions
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At line 25 in file REG_UTILES.inc
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Uses
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None
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Comment: GPIOBASEB unused
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MaskBlank 00000004
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Symbol: MaskBlank
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Definitions
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At line 37 in file REG_UTILES.inc
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Uses
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None
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Comment: MaskBlank unused
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MaskDsprg 00000002
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Symbol: MaskDsprg
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Definitions
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At line 39 in file REG_UTILES.inc
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Uses
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None
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Comment: MaskDsprg unused
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MaskGsclk 00000001
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Symbol: MaskGsclk
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Definitions
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At line 40 in file REG_UTILES.inc
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Uses
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None
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Comment: MaskGsclk unused
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MaskSclk 00000020
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Symbol: MaskSclk
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Definitions
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At line 38 in file REG_UTILES.inc
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Uses
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None
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Comment: MaskSclk unused
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MaskSerial_Dots 00000080
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Symbol: MaskSerial_Dots
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Definitions
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At line 34 in file REG_UTILES.inc
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Uses
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None
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Comment: MaskSerial_Dots unused
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MaskSerial_In1 00000080
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ARM Macro Assembler Page 2 Alphabetic symbol ordering
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Absolute symbols
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Symbol: MaskSerial_In1
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Definitions
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At line 33 in file REG_UTILES.inc
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Uses
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None
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Comment: MaskSerial_In1 unused
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MaskVprg 00000010
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Symbol: MaskVprg
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Definitions
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At line 35 in file REG_UTILES.inc
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Uses
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None
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Comment: MaskVprg unused
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MaskXlat 00000008
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Symbol: MaskXlat
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Definitions
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At line 36 in file REG_UTILES.inc
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Uses
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None
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Comment: MaskXlat unused
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OffsetInput 00000008
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Symbol: OffsetInput
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Definitions
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At line 27 in file REG_UTILES.inc
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Uses
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None
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Comment: OffsetInput unused
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OffsetOutput 0000000C
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Symbol: OffsetOutput
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Definitions
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At line 28 in file REG_UTILES.inc
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Uses
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At line 55 in file FonctionEtape2.asm
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At line 57 in file FonctionEtape2.asm
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At line 65 in file FonctionEtape2.asm
|
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At line 67 in file FonctionEtape2.asm
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OffsetReset 00000014
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Symbol: OffsetReset
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Definitions
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At line 30 in file REG_UTILES.inc
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Uses
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None
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Comment: OffsetReset unused
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OffsetSet 00000010
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Symbol: OffsetSet
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Definitions
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At line 29 in file REG_UTILES.inc
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Uses
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None
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Comment: OffsetSet unused
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SCB_VTOR E000ED08
|
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|
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ARM Macro Assembler Page 3 Alphabetic symbol ordering
|
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Absolute symbols
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|
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Symbol: SCB_VTOR
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Definitions
|
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At line 43 in file REG_UTILES.inc
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Uses
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None
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Comment: SCB_VTOR unused
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TIM1_CNT 40012C24
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Symbol: TIM1_CNT
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Definitions
|
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At line 45 in file REG_UTILES.inc
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Uses
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None
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Comment: TIM1_CNT unused
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TIM1_SR 40012C10
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||
|
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Symbol: TIM1_SR
|
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Definitions
|
||
At line 44 in file REG_UTILES.inc
|
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Uses
|
||
None
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||
Comment: TIM1_SR unused
|
||
TIM4_ARR 4000082C
|
||
|
||
Symbol: TIM4_ARR
|
||
Definitions
|
||
At line 46 in file REG_UTILES.inc
|
||
Uses
|
||
None
|
||
Comment: TIM4_ARR unused
|
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TIM4_SR 40000810
|
||
|
||
Symbol: TIM4_SR
|
||
Definitions
|
||
At line 47 in file REG_UTILES.inc
|
||
Uses
|
||
None
|
||
Comment: TIM4_SR unused
|
||
19 symbols
|
||
363 symbols in table
|