Merge branch 'main' into feature-data_memory
This commit is contained in:
commit
04002470a4
4 changed files with 338 additions and 2 deletions
34
README.md
34
README.md
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@ -1,4 +1,34 @@
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# memory_file
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# Banc de mémoire
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Architecture contenant deux mémoires : une mémoire pour les données et une mémoire pour les instructions.
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- **Entrées/Sorties :**
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- Entrées :
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- `@A(3:0)` : Adresse de la mémoire des données (4 bits).
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- `@B(3:0)` : Adresse de la mémoire des instructions (4 bits).
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- `DATA(7:0)` : Données à écrire dans la mémoire des données (8 bits).
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- `CLK` : Signal d'horloge.
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- `RST` : Signal de réinitialisation.
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- `@W(3:0)` : Adresse d'écriture pour la mémoire des données (4 bits).
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- `QA(7:0)` : Données lues depuis la mémoire des données (8 bits).
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- `QB(7:0)` : Données lues depuis la mémoire des instructions (8 bits).
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- `W` : Signal de sélection d'écriture dans la mémoire des données.
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- Sorties :
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- Aucune sortie spécifiée.
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- **Mémoire des données :**
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- La mémoire des données permet un accès en lecture ou en écriture.
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- L'adresse de la zone mémoire est fournie par l'entrée `@`.
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- Pour réaliser une lecture, `RW` doit être positionné à 1.
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- Pour réaliser une écriture, `RW` doit être positionné à 0. Dans le cas d'une écriture, le contenu de l'entrée `IN` est copié dans la mémoire à l'adresse `@`.
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- Le signal de reset, `RST`, permet d'initialiser le contenu de la mémoire à 0x00.
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- Les opérations de lecture, d'écriture et de reset se font synchrones avec l'horloge `CLK`.
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||||||
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- **Mémoire des instructions :**
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- La mémoire des instructions a une structure simplifiée et s'apparente à une ROM.
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- Le programme à exécuter par le microprocesseur est stocké dans cette mémoire au préalable.
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- À l'exécution, toute modification du contenu de cette mémoire est empêchée.
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- La lecture se fait synchrone avec l'horloge `CLK`.
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235
instruction_memory/memory_file.xpr
Normal file
235
instruction_memory/memory_file.xpr
Normal file
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@ -0,0 +1,235 @@
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<?xml version="1.0" encoding="UTF-8"?>
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||||||
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<!-- Product Version: Vivado v2023.1 (64-bit) -->
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||||||
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<!-- -->
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<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
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||||||
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<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
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||||||
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||||||
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<Project Product="Vivado" Version="7" Minor="63" Path="D:/Data/Alzyohan/GEI/VHDL/memory_file_vivado/memory_file.xpr">
|
||||||
|
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||||
|
<Configuration>
|
||||||
|
<Option Name="Id" Val="0ce82e7a6509434fa74c68762fdc2cf1"/>
|
||||||
|
<Option Name="Part" Val="xc7a35tcpg236-1"/>
|
||||||
|
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||||
|
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||||
|
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||||
|
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||||
|
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||||
|
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||||
|
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||||
|
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||||
|
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||||
|
<Option Name="SimulatorVersionXsim" Val="2023.1"/>
|
||||||
|
<Option Name="SimulatorVersionModelSim" Val="2022.3"/>
|
||||||
|
<Option Name="SimulatorVersionQuesta" Val="2022.3"/>
|
||||||
|
<Option Name="SimulatorVersionXcelium" Val="22.09.001"/>
|
||||||
|
<Option Name="SimulatorVersionVCS" Val="T-2022.06-SP1"/>
|
||||||
|
<Option Name="SimulatorVersionRiviera" Val="2022.04"/>
|
||||||
|
<Option Name="SimulatorVersionActiveHdl" Val="13.1"/>
|
||||||
|
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||||
|
<Option Name="TargetLanguage" Val="VHDL"/>
|
||||||
|
<Option Name="SimulatorLanguage" Val="VHDL"/>
|
||||||
|
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
|
||||||
|
<Option Name="BoardPartRepoPaths" Val="C:/Users/alzyo/AppData/Roaming/Xilinx/Vivado/2023.1/xhub/board_store/xilinx_board_store"/>
|
||||||
|
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||||
|
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="ProjectType" Val="Default"/>
|
||||||
|
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||||
|
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||||
|
<Option Name="IPCachePermission" Val="read"/>
|
||||||
|
<Option Name="IPCachePermission" Val="write"/>
|
||||||
|
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||||
|
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||||
|
<Option Name="SimCompileState" Val="TRUE"/>
|
||||||
|
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||||
|
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||||
|
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||||
|
<Option Name="EnableBDX" Val="FALSE"/>
|
||||||
|
<Option Name="DSABoardId" Val="basys3"/>
|
||||||
|
<Option Name="WTXSimLaunchSim" Val="4"/>
|
||||||
|
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTXSimExportSim" Val="0"/>
|
||||||
|
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||||
|
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||||
|
<Option Name="WTIesExportSim" Val="0"/>
|
||||||
|
<Option Name="WTVcsExportSim" Val="0"/>
|
||||||
|
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||||
|
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||||
|
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||||
|
<Option Name="XSimRadix" Val="hex"/>
|
||||||
|
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||||
|
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||||
|
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||||
|
<Option Name="SimTypes" Val="rtl"/>
|
||||||
|
<Option Name="SimTypes" Val="bfm"/>
|
||||||
|
<Option Name="SimTypes" Val="tlm"/>
|
||||||
|
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||||
|
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||||
|
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||||
|
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||||
|
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||||
|
</Configuration>
|
||||||
|
<FileSets Version="1" Minor="31">
|
||||||
|
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||||
|
<Filter Type="Srcs"/>
|
||||||
|
<File Path="$PPRDIR/../memory_file/src/instruction.vhd">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="instruction"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||||
|
<Filter Type="Constrs"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="ConstrsType" Val="XDC"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||||
|
<File Path="$PPRDIR/../memory_file/src/sim_instruction.vhd">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="test_instr"/>
|
||||||
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
<Option Name="TransportPathDelay" Val="0"/>
|
||||||
|
<Option Name="TransportIntDelay" Val="0"/>
|
||||||
|
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||||
|
<Option Name="PamDesignTestbench" Val=""/>
|
||||||
|
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||||
|
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||||
|
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||||
|
<Option Name="SrcSet" Val="sources_1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||||
|
<Filter Type="Utils"/>
|
||||||
|
<File Path="$PSRCDIR/utils_1/imports/synth_1/instruction.dcp">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedInSteps" Val="synth_1"/>
|
||||||
|
<Attr Name="AutoDcp" Val="1"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
</FileSets>
|
||||||
|
<Simulators>
|
||||||
|
<Simulator Name="XSim">
|
||||||
|
<Option Name="Description" Val="Vivado Simulator"/>
|
||||||
|
<Option Name="CompiledLib" Val="0"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="ModelSim">
|
||||||
|
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Questa">
|
||||||
|
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Riviera">
|
||||||
|
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="ActiveHDL">
|
||||||
|
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
</Simulators>
|
||||||
|
<Runs Version="1" Minor="20">
|
||||||
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/instruction.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 4 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
</Runs>
|
||||||
|
<Board>
|
||||||
|
<Jumpers/>
|
||||||
|
</Board>
|
||||||
|
<DashboardSummary Version="1" Minor="0">
|
||||||
|
<Dashboards>
|
||||||
|
<Dashboard Name="default_dashboard">
|
||||||
|
<Gadgets>
|
||||||
|
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||||
|
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||||
|
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
</Gadgets>
|
||||||
|
</Dashboard>
|
||||||
|
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||||
|
</Dashboards>
|
||||||
|
</DashboardSummary>
|
||||||
|
</Project>
|
||||||
40
instruction_memory/src/instruction.vhd
Normal file
40
instruction_memory/src/instruction.vhd
Normal file
|
|
@ -0,0 +1,40 @@
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||||
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||||
|
|
||||||
|
entity instruction is
|
||||||
|
port(
|
||||||
|
instruction: in STD_LOGIC_VECTOR(7 downto 0);
|
||||||
|
code: out STD_LOGIC_VECTOR(31 downto 0);
|
||||||
|
clk: in STD_LOGIC
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Array of STD_LOGIC_VECTOR
|
||||||
|
type code_array is array(0 to 256) of
|
||||||
|
STD_LOGIC_VECTOR(31 downto 0);
|
||||||
|
|
||||||
|
-- Initialize the code memory
|
||||||
|
function init return code_array is
|
||||||
|
variable init_result: code_array;
|
||||||
|
begin
|
||||||
|
--do something (e.g. read data from a file, perform some initialization calculation, ...)
|
||||||
|
-- Exemple :
|
||||||
|
for i in code_array'range loop
|
||||||
|
init_result(i) := std_logic_vector(conv_unsigned(i, 32));
|
||||||
|
end loop;
|
||||||
|
return init_result;
|
||||||
|
end function init;
|
||||||
|
end instruction;
|
||||||
|
|
||||||
|
architecture behavior_instr of instruction is
|
||||||
|
-- Memory variable
|
||||||
|
signal code_memory: code_array := init;
|
||||||
|
begin
|
||||||
|
process(instruction, clk) is
|
||||||
|
begin
|
||||||
|
if clk'event AND clk = '1' then
|
||||||
|
code <= code_memory(CONV_INTEGER(UNSIGNED(instruction)));
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
end behavior_instr;
|
||||||
31
instruction_memory/src/sim_instruction.vhd
Normal file
31
instruction_memory/src/sim_instruction.vhd
Normal file
|
|
@ -0,0 +1,31 @@
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
use IEEE.NUMERIC_STD.ALL;
|
||||||
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||||
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||||
|
|
||||||
|
entity test_instr is
|
||||||
|
end test_instr;
|
||||||
|
|
||||||
|
architecture bench of test_instr is
|
||||||
|
component instruction is
|
||||||
|
port(
|
||||||
|
instruction: in STD_LOGIC_VECTOR(7 downto 0);
|
||||||
|
code: out STD_LOGIC_VECTOR(31 downto 0);
|
||||||
|
clk: in STD_LOGIC
|
||||||
|
);
|
||||||
|
end component;
|
||||||
|
|
||||||
|
for all : instruction use entity work.instruction;
|
||||||
|
|
||||||
|
signal inAddress : STD_LOGIC_VECTOR(7 downto 0);
|
||||||
|
signal outCode : STD_LOGIC_VECTOR(31 downto 0);
|
||||||
|
signal inClock : STD_LOGIC := '0';
|
||||||
|
|
||||||
|
begin
|
||||||
|
testeur: instruction PORT MAP(inAddress, outCode, inClock);
|
||||||
|
inClock <= not inClock after 1ns;
|
||||||
|
|
||||||
|
inAddress <= X"00", X"0a" after 10ns;
|
||||||
|
|
||||||
|
end bench;
|
||||||
Loading…
Add table
Reference in a new issue