diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..48397b5 --- /dev/null +++ b/.gitignore @@ -0,0 +1,68 @@ +# Vivado project files +*.cache/ +*.data/ +*.hw/ +*.ip_user_files/ +*.runs/ +*.sim/ +*.srcs/ +*.sdk/ + +# Vivado settings and logs +*.jou +*.log +*.str +*.bak + +# Generated files +project_*.xpr +*.bit +*.bin +*.bmm +*.dcp +*.html +*.xdc +*.ltx +*.ngc +*.tcl +*.xgui +*.xise +*.xml +*_bd.tcl +*_top.xdc +*_wrapper.bmm +*_xmd.xdc +*_xmd.ini + +# Compiled files +webtalk.log +xgui/ +hdl/ +isim/ +project_*.cache/ +project_*.runs/ +project_*.srcs/ +project_*.xpr.user +*_vivado_* + +# IDE specific files +.DS_Store +*.suo +*.user +*.sln +*.ncb +*.aps +*.vsp +*.pidb +*.opensdf +*.VC.db + +# Ignore user-specific settings and configurations +*.xilinx +*.sws +*.cache +*.str +*.history + +# Ignore backup files created by text editors +*~ diff --git a/data_memory/data_memory/data_memory.cache/sim/ssm.db b/data_memory/data_memory/data_memory.cache/sim/ssm.db deleted file mode 100644 index 17276db..0000000 --- a/data_memory/data_memory/data_memory.cache/sim/ssm.db +++ /dev/null @@ -1,10 +0,0 @@ -################################################################################ -# DONOT REMOVE THIS FILE -# Unified simulation database file for selected simulation model for IP -# -# File: ssm.db (Sun Oct 1 13:53:31 2023) -# -# This file is generated by the unified simulation automation and contains the -# selected simulation model information for the IP/BD instances. -# DONOT REMOVE THIS FILE -################################################################################ diff --git a/data_memory/data_memory/data_memory.cache/wt/project.wpc b/data_memory/data_memory/data_memory.cache/wt/project.wpc deleted file mode 100644 index 9b34209..0000000 --- a/data_memory/data_memory/data_memory.cache/wt/project.wpc +++ /dev/null @@ -1,3 +0,0 @@ -version:1 -6d6f64655f636f756e7465727c4755494d6f6465:1 -eof: diff --git a/data_memory/data_memory/data_memory.cache/wt/synthesis.wdf b/data_memory/data_memory/data_memory.cache/wt/synthesis.wdf deleted file mode 100644 index 13280d6..0000000 --- a/data_memory/data_memory/data_memory.cache/wt/synthesis.wdf +++ /dev/null @@ -1,47 +0,0 @@ -version:1 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:786337613335746370673233362d31:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:446174614d656d6f7279:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 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mode 100644 index 50afb2c..0000000 --- a/data_memory/data_memory/data_memory.cache/wt/xsim.wdf +++ /dev/null @@ -1,4 +0,0 @@ -version:1 -7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 -7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 -eof:241934075 diff --git a/data_memory/data_memory/data_memory.hw/data_memory.lpr b/data_memory/data_memory/data_memory.hw/data_memory.lpr deleted file mode 100644 index 7c60ccc..0000000 --- a/data_memory/data_memory/data_memory.hw/data_memory.lpr +++ /dev/null @@ -1,6 +0,0 @@ - - - - - - diff --git a/data_memory/data_memory/data_memory.ip_user_files/README.txt b/data_memory/data_memory/data_memory.ip_user_files/README.txt deleted file mode 100644 index 023052c..0000000 --- a/data_memory/data_memory/data_memory.ip_user_files/README.txt +++ /dev/null @@ -1 +0,0 @@ -The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/data_memory/data_memory/data_memory.runs/.jobs/vrs_config_1.xml b/data_memory/data_memory/data_memory.runs/.jobs/vrs_config_1.xml deleted file mode 100644 index 0b56a7d..0000000 --- a/data_memory/data_memory/data_memory.runs/.jobs/vrs_config_1.xml +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/data_memory/data_memory/data_memory.runs/.jobs/vrs_config_2.xml b/data_memory/data_memory/data_memory.runs/.jobs/vrs_config_2.xml deleted file mode 100644 index 0b56a7d..0000000 --- a/data_memory/data_memory/data_memory.runs/.jobs/vrs_config_2.xml +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/data_memory/data_memory/data_memory.runs/.jobs/vrs_config_3.xml b/data_memory/data_memory/data_memory.runs/.jobs/vrs_config_3.xml deleted file mode 100644 index 0b56a7d..0000000 --- a/data_memory/data_memory/data_memory.runs/.jobs/vrs_config_3.xml +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/data_memory/data_memory/data_memory.runs/.jobs/vrs_config_4.xml b/data_memory/data_memory/data_memory.runs/.jobs/vrs_config_4.xml deleted file mode 100644 index 0b56a7d..0000000 --- a/data_memory/data_memory/data_memory.runs/.jobs/vrs_config_4.xml +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/data_memory/data_memory/data_memory.runs/.jobs/vrs_config_5.xml b/data_memory/data_memory/data_memory.runs/.jobs/vrs_config_5.xml deleted file mode 100644 index 0b56a7d..0000000 --- a/data_memory/data_memory/data_memory.runs/.jobs/vrs_config_5.xml +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/data_memory/data_memory/data_memory.runs/synth_1/.Vivado_Synthesis.queue.rst b/data_memory/data_memory/data_memory.runs/synth_1/.Vivado_Synthesis.queue.rst deleted file mode 100644 index e69de29..0000000 diff --git a/data_memory/data_memory/data_memory.runs/synth_1/.vivado.begin.rst b/data_memory/data_memory/data_memory.runs/synth_1/.vivado.begin.rst deleted file mode 100644 index 3df3fc4..0000000 --- a/data_memory/data_memory/data_memory.runs/synth_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/data_memory/data_memory/data_memory.runs/synth_1/.vivado.end.rst b/data_memory/data_memory/data_memory.runs/synth_1/.vivado.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/data_memory/data_memory/data_memory.runs/synth_1/DataMemory.dcp b/data_memory/data_memory/data_memory.runs/synth_1/DataMemory.dcp deleted file mode 100644 index 617c014..0000000 Binary files a/data_memory/data_memory/data_memory.runs/synth_1/DataMemory.dcp and /dev/null differ diff --git a/data_memory/data_memory/data_memory.runs/synth_1/DataMemory.tcl b/data_memory/data_memory/data_memory.runs/synth_1/DataMemory.tcl deleted file mode 100644 index 899a723..0000000 --- a/data_memory/data_memory/data_memory.runs/synth_1/DataMemory.tcl +++ /dev/null @@ -1,120 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -namespace eval ::optrace { - variable script "C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.runs/synth_1/DataMemory.tcl" - variable category "vivado_synth" -} - -# Try to connect to running dispatch if we haven't done so already. -# This code assumes that the Tcl interpreter is not using threads, -# since the ::dispatch::connected variable isn't mutex protected. -if {![info exists ::dispatch::connected]} { - namespace eval ::dispatch { - variable connected false - if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { - set result "true" - if {[catch { - if {[lsearch -exact [package names] DispatchTcl] < 0} { - set result [load librdi_cd_clienttcl[info sharedlibextension]] - } - if {$result eq "false"} { - puts "WARNING: Could not load dispatch client library" - } - set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] - if { $connect_id eq "" } { - puts "WARNING: Could not initialize dispatch client" - } else { - puts "INFO: Dispatch client connection id - $connect_id" - set connected true - } - } catch_res]} { - puts "WARNING: failed to connect to dispatch server - $catch_res" - } - } - } -} -if {$::dispatch::connected} { - # Remove the dummy proc if it exists. - if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { - rename ::OPTRACE "" - } - proc ::OPTRACE { task action {tags {} } } { - ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category - } - # dispatch is generic. We specifically want to attach logging. - ::vitis_log::connect_client -} else { - # Add dummy proc if it doesn't exist. - if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { - proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { - # Do nothing - } - } -} - -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -OPTRACE "synth_1" START { ROLLUP_AUTO } -OPTRACE "Creating in-memory project" START { } -create_project -in_memory -part xc7a35tcpg236-1 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_property webtalk.parent_dir C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.cache/wt [current_project] -set_property parent.project_path C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.xpr [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language VHDL [current_project] -set_property board_part_repo_paths {C:/Users/robin/AppData/Roaming/Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store} [current_project] -set_property board_part digilentinc.com:basys3:part0:1.2 [current_project] -set_property ip_output_repo c:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -OPTRACE "Creating in-memory project" END { } -OPTRACE "Adding files" START { } -read_vhdl -library xil_defaultlib C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.srcs/sources_1/new/design.vhd -OPTRACE "Adding files" END { } -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -set_param ips.enableIPCacheLiteLoad 1 -close [open __synthesis_is_running__ w] - -OPTRACE "synth_design" START { } -synth_design -top DataMemory -part xc7a35tcpg236-1 -OPTRACE "synth_design" END { } -if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } { - send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING" -} - - -OPTRACE "write_checkpoint" START { CHECKPOINT } -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef DataMemory.dcp -OPTRACE "write_checkpoint" END { } -OPTRACE "synth reports" START { REPORT } -create_report "synth_1_synth_report_utilization_0" "report_utilization -file DataMemory_utilization_synth.rpt -pb DataMemory_utilization_synth.pb" -OPTRACE "synth reports" END { } -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] -OPTRACE "synth_1" END { } diff --git a/data_memory/data_memory/data_memory.runs/synth_1/DataMemory.vds b/data_memory/data_memory/data_memory.runs/synth_1/DataMemory.vds deleted file mode 100644 index a18acf6..0000000 --- a/data_memory/data_memory/data_memory.runs/synth_1/DataMemory.vds +++ /dev/null @@ -1,191 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2022.2 (64-bit) -# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 -# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 -# Start of session at: Sun Oct 1 13:21:12 2023 -# Process ID: 14348 -# Current directory: C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.runs/synth_1 -# Command line: vivado.exe -log DataMemory.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source DataMemory.tcl -# Log file: C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.runs/synth_1/DataMemory.vds -# Journal file: C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.runs/synth_1\vivado.jou -# Running On: ASUS_Robin, OS: Windows, CPU Frequency: 2096 MHz, CPU Physical cores: 8, Host memory: 16576 MB -#----------------------------------------------------------- -source DataMemory.tcl -notrace -create_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 393.844 ; gain = 60.699 -Command: synth_design -top DataMemory -part xc7a35tcpg236-1 -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' -INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. -INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 3816 -INFO: [Synth 8-11241] undeclared symbol 'REGCCE', assumed default net type 'wire' [C:/Xilinx/Vivado/2022.2/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170] ---------------------------------------------------------------------------------- -Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 834.848 ; gain = 414.324 ---------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'DataMemory' [C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.srcs/sources_1/new/design.vhd:15] -INFO: [Synth 8-256] done synthesizing module 'DataMemory' (0#1) [C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.srcs/sources_1/new/design.vhd:15] ---------------------------------------------------------------------------------- -Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 968.109 ; gain = 547.586 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 968.109 ; gain = 547.586 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7a35tcpg236-1 ---------------------------------------------------------------------------------- -INFO: [Device 21-403] Loading part xc7a35tcpg236-1 -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 968.109 ; gain = 547.586 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 968.109 ; gain = 547.586 ---------------------------------------------------------------------------------- -No constraint files found. ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : -+---Registers : - 8 Bit Registers := 257 -+---Muxes : - 2 Input 1 Bit Muxes := 256 ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 90 (col length:60) -BRAMs: 100 (col length: RAMB18 60 RAMB36 30) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- -No constraint files found. ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -WARNING: [Synth 8-7080] Parallel synthesis criteria is not met ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1160.242 ; gain = 739.719 ---------------------------------------------------------------------------------- -No constraint files found. ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 1169.125 ; gain = 748.602 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1169.297 ; gain = 748.773 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 1169.297 ; gain = 748.773 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 1169.297 ; gain = 748.773 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 1169.297 ; gain = 748.773 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 1169.297 ; gain = 748.773 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 1169.297 ; gain = 748.773 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 1169.297 ; gain = 748.773 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+------+------+ -| |Cell |Count | -+------+------+------+ -|1 |BUFG | 1| -|2 |LUT2 | 51| -|3 |LUT4 | 30| -|4 |LUT6 | 800| -|5 |MUXF7 | 272| -|6 |MUXF8 | 136| -|7 |FDCE | 2048| -|8 |FDRE | 8| -|9 |IBUF | 19| -|10 |OBUF | 8| -+------+------+------+ - -Report Instance Areas: -+------+---------+-------+------+ -| |Instance |Module |Cells | -+------+---------+-------+------+ -|1 |top | | 3373| -+------+---------+-------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 1169.297 ; gain = 748.773 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 1169.297 ; gain = 748.773 -Synthesis Optimization Complete : Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 1169.297 ; gain = 748.773 -INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1181.184 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 408 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -WARNING: [Netlist 29-101] Netlist 'DataMemory' is not ideal for floorplanning, since the cellview 'DataMemory' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1237.270 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -Synth Design complete, checksum: f642343e -INFO: [Common 17-83] Releasing license: Synthesis -15 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:42 . Memory (MB): peak = 1237.270 ; gain = 840.602 -INFO: [Common 17-1381] The checkpoint 'C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.runs/synth_1/DataMemory.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file DataMemory_utilization_synth.rpt -pb DataMemory_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sun Oct 1 13:22:06 2023... diff --git a/data_memory/data_memory/data_memory.runs/synth_1/DataMemory_utilization_synth.pb b/data_memory/data_memory/data_memory.runs/synth_1/DataMemory_utilization_synth.pb deleted file mode 100644 index 06f4821..0000000 Binary files a/data_memory/data_memory/data_memory.runs/synth_1/DataMemory_utilization_synth.pb and /dev/null differ diff --git a/data_memory/data_memory/data_memory.runs/synth_1/DataMemory_utilization_synth.rpt b/data_memory/data_memory/data_memory.runs/synth_1/DataMemory_utilization_synth.rpt deleted file mode 100644 index a00b1c1..0000000 --- a/data_memory/data_memory/data_memory.runs/synth_1/DataMemory_utilization_synth.rpt +++ /dev/null @@ -1,182 +0,0 @@ -Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 -| Date : Sun Oct 1 13:22:06 2023 -| Host : ASUS_Robin running 64-bit major release (build 9200) -| Command : report_utilization -file DataMemory_utilization_synth.rpt -pb DataMemory_utilization_synth.pb -| Design : DataMemory -| Device : xc7a35tcpg236-1 -| Speed File : -1 -| Design State : Synthesized ---------------------------------------------------------------------------------------------------------------- - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Memory -3. DSP -4. IO and GT Specific -5. Clocking -6. Specific Feature -7. Primitives -8. Black Boxes -9. Instantiated Netlists - -1. Slice Logic --------------- - -+-------------------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+-------------------------+------+-------+------------+-----------+-------+ -| Slice LUTs* | 842 | 0 | 0 | 20800 | 4.05 | -| LUT as Logic | 842 | 0 | 0 | 20800 | 4.05 | -| LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 | -| Slice Registers | 2056 | 0 | 0 | 41600 | 4.94 | -| Register as Flip Flop | 2056 | 0 | 0 | 41600 | 4.94 | -| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 | -| F7 Muxes | 272 | 0 | 0 | 16300 | 1.67 | -| F8 Muxes | 136 | 0 | 0 | 8150 | 1.67 | -+-------------------------+------+-------+------------+-----------+-------+ -* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. -Warning! LUT value is adjusted to account for LUT combining. - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 2048 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 8 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Memory ---------- - -+----------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+----------------+------+-------+------------+-----------+-------+ -| Block RAM Tile | 0 | 0 | 0 | 50 | 0.00 | -| RAMB36/FIFO* | 0 | 0 | 0 | 50 | 0.00 | -| RAMB18 | 0 | 0 | 0 | 100 | 0.00 | -+----------------+------+-------+------------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -3. DSP ------- - -+-----------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+-----------+------+-------+------------+-----------+-------+ -| DSPs | 0 | 0 | 0 | 90 | 0.00 | -+-----------+------+-------+------------+-----------+-------+ - - -4. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+-----------------------------+------+-------+------------+-----------+-------+ -| Bonded IOB | 27 | 0 | 0 | 106 | 25.47 | -| Bonded IPADs | 0 | 0 | 0 | 10 | 0.00 | -| Bonded OPADs | 0 | 0 | 0 | 4 | 0.00 | -| PHY_CONTROL | 0 | 0 | 0 | 5 | 0.00 | -| PHASER_REF | 0 | 0 | 0 | 5 | 0.00 | -| OUT_FIFO | 0 | 0 | 0 | 20 | 0.00 | -| IN_FIFO | 0 | 0 | 0 | 20 | 0.00 | -| IDELAYCTRL | 0 | 0 | 0 | 5 | 0.00 | -| IBUFDS | 0 | 0 | 0 | 104 | 0.00 | -| GTPE2_CHANNEL | 0 | 0 | 0 | 2 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 20 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 20 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 250 | 0.00 | -| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 | -| ILOGIC | 0 | 0 | 0 | 106 | 0.00 | -| OLOGIC | 0 | 0 | 0 | 106 | 0.00 | -+-----------------------------+------+-------+------------+-----------+-------+ - - -5. Clocking ------------ - -+------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+------------+------+-------+------------+-----------+-------+ -| BUFGCTRL | 1 | 0 | 0 | 32 | 3.13 | -| BUFIO | 0 | 0 | 0 | 20 | 0.00 | -| MMCME2_ADV | 0 | 0 | 0 | 5 | 0.00 | -| PLLE2_ADV | 0 | 0 | 0 | 5 | 0.00 | -| BUFMRCE | 0 | 0 | 0 | 10 | 0.00 | -| BUFHCE | 0 | 0 | 0 | 72 | 0.00 | -| BUFR | 0 | 0 | 0 | 20 | 0.00 | -+------------+------+-------+------------+-----------+-------+ - - -6. Specific Feature -------------------- - -+-------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+-------------+------+-------+------------+-----------+-------+ -| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | -| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | -| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+------------+-----------+-------+ - - -7. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| FDCE | 2048 | Flop & Latch | -| LUT6 | 800 | LUT | -| MUXF7 | 272 | MuxFx | -| MUXF8 | 136 | MuxFx | -| LUT2 | 51 | LUT | -| LUT4 | 30 | LUT | -| IBUF | 19 | IO | -| OBUF | 8 | IO | -| FDRE | 8 | Flop & Latch | -| BUFG | 1 | Clock | -+----------+------+---------------------+ - - -8. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -9. Instantiated Netlists ------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/data_memory/data_memory/data_memory.runs/synth_1/ISEWrap.js b/data_memory/data_memory/data_memory.runs/synth_1/ISEWrap.js deleted file mode 100644 index db0a510..0000000 --- a/data_memory/data_memory/data_memory.runs/synth_1/ISEWrap.js +++ /dev/null @@ -1,269 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/data_memory/data_memory/data_memory.runs/synth_1/ISEWrap.sh b/data_memory/data_memory/data_memory.runs/synth_1/ISEWrap.sh deleted file mode 100644 index c2fbbb6..0000000 --- a/data_memory/data_memory/data_memory.runs/synth_1/ISEWrap.sh +++ /dev/null @@ -1,84 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -cmd_exists() -{ - command -v "$1" >/dev/null 2>&1 -} - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! - -HostNameFile=/proc/sys/kernel/hostname -if cmd_exists hostname -then -ISE_HOST=$(hostname) -elif cmd_exists uname -then -ISE_HOST=$(uname -n) -elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] -then -ISE_HOST=$(cat $HostNameFile) -elif [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi - -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/data_memory/data_memory/data_memory.runs/synth_1/__synthesis_is_complete__ b/data_memory/data_memory/data_memory.runs/synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29..0000000 diff --git a/data_memory/data_memory/data_memory.runs/synth_1/gen_run.xml b/data_memory/data_memory/data_memory.runs/synth_1/gen_run.xml deleted file mode 100644 index 5288ffe..0000000 --- a/data_memory/data_memory/data_memory.runs/synth_1/gen_run.xml +++ /dev/null @@ -1,44 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Vivado Synthesis Defaults - - - - diff --git a/data_memory/data_memory/data_memory.runs/synth_1/htr.txt b/data_memory/data_memory/data_memory.runs/synth_1/htr.txt deleted file mode 100644 index 7c9c555..0000000 --- a/data_memory/data_memory/data_memory.runs/synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -REM - -vivado -log DataMemory.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source DataMemory.tcl diff --git a/data_memory/data_memory/data_memory.runs/synth_1/project.wdf b/data_memory/data_memory/data_memory.runs/synth_1/project.wdf deleted file mode 100644 index 8cbc467..0000000 --- a/data_memory/data_memory/data_memory.runs/synth_1/project.wdf +++ /dev/null @@ -1,31 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:5648444c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3831653131636564363934333432643761343836353331303863373835353939:506172656e742050412070726f6a656374204944:00 -eof:2986823203 diff --git a/data_memory/data_memory/data_memory.runs/synth_1/rundef.js b/data_memory/data_memory/data_memory.runs/synth_1/rundef.js deleted file mode 100644 index 54c7c11..0000000 --- a/data_memory/data_memory/data_memory.runs/synth_1/rundef.js +++ /dev/null @@ -1,36 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "C:/Xilinx/Vivado/2022.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2022.2/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2022.2/bin;"; -} else { - PathVal = "C:/Xilinx/Vivado/2022.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2022.2/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2022.2/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log DataMemory.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source DataMemory.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/data_memory/data_memory/data_memory.runs/synth_1/runme.bat b/data_memory/data_memory/data_memory.runs/synth_1/runme.bat deleted file mode 100644 index 4fd70df..0000000 --- a/data_memory/data_memory/data_memory.runs/synth_1/runme.bat +++ /dev/null @@ -1,10 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/data_memory/data_memory/data_memory.runs/synth_1/runme.log b/data_memory/data_memory/data_memory.runs/synth_1/runme.log deleted file mode 100644 index 4891d1d..0000000 --- a/data_memory/data_memory/data_memory.runs/synth_1/runme.log +++ /dev/null @@ -1,190 +0,0 @@ - -*** Running vivado - with args -log DataMemory.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source DataMemory.tcl - - - -****** Vivado v2022.2 (64-bit) - **** SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 - **** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 - ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. - -source DataMemory.tcl -notrace -create_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 393.844 ; gain = 60.699 -Command: synth_design -top DataMemory -part xc7a35tcpg236-1 -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' -INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. -INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 3816 -INFO: [Synth 8-11241] undeclared symbol 'REGCCE', assumed default net type 'wire' [C:/Xilinx/Vivado/2022.2/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170] ---------------------------------------------------------------------------------- -Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 834.848 ; gain = 414.324 ---------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'DataMemory' [C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.srcs/sources_1/new/design.vhd:15] -INFO: [Synth 8-256] done synthesizing module 'DataMemory' (0#1) [C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.srcs/sources_1/new/design.vhd:15] ---------------------------------------------------------------------------------- -Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 968.109 ; gain = 547.586 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 968.109 ; gain = 547.586 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7a35tcpg236-1 ---------------------------------------------------------------------------------- -INFO: [Device 21-403] Loading part xc7a35tcpg236-1 -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 968.109 ; gain = 547.586 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 968.109 ; gain = 547.586 ---------------------------------------------------------------------------------- -No constraint files found. ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : -+---Registers : - 8 Bit Registers := 257 -+---Muxes : - 2 Input 1 Bit Muxes := 256 ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 90 (col length:60) -BRAMs: 100 (col length: RAMB18 60 RAMB36 30) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- -No constraint files found. ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -WARNING: [Synth 8-7080] Parallel synthesis criteria is not met ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1160.242 ; gain = 739.719 ---------------------------------------------------------------------------------- -No constraint files found. ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 1169.125 ; gain = 748.602 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1169.297 ; gain = 748.773 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 1169.297 ; gain = 748.773 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 1169.297 ; gain = 748.773 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 1169.297 ; gain = 748.773 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 1169.297 ; gain = 748.773 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 1169.297 ; gain = 748.773 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 1169.297 ; gain = 748.773 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+------+------+ -| |Cell |Count | -+------+------+------+ -|1 |BUFG | 1| -|2 |LUT2 | 51| -|3 |LUT4 | 30| -|4 |LUT6 | 800| -|5 |MUXF7 | 272| -|6 |MUXF8 | 136| -|7 |FDCE | 2048| -|8 |FDRE | 8| -|9 |IBUF | 19| -|10 |OBUF | 8| -+------+------+------+ - -Report Instance Areas: -+------+---------+-------+------+ -| |Instance |Module |Cells | -+------+---------+-------+------+ -|1 |top | | 3373| -+------+---------+-------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 1169.297 ; gain = 748.773 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 1169.297 ; gain = 748.773 -Synthesis Optimization Complete : Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 1169.297 ; gain = 748.773 -INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1181.184 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 408 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -WARNING: [Netlist 29-101] Netlist 'DataMemory' is not ideal for floorplanning, since the cellview 'DataMemory' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1237.270 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -Synth Design complete, checksum: f642343e -INFO: [Common 17-83] Releasing license: Synthesis -15 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:42 . Memory (MB): peak = 1237.270 ; gain = 840.602 -INFO: [Common 17-1381] The checkpoint 'C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.runs/synth_1/DataMemory.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file DataMemory_utilization_synth.rpt -pb DataMemory_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sun Oct 1 13:22:06 2023... diff --git a/data_memory/data_memory/data_memory.runs/synth_1/runme.sh b/data_memory/data_memory/data_memory.runs/synth_1/runme.sh deleted file mode 100644 index a313f10..0000000 --- a/data_memory/data_memory/data_memory.runs/synth_1/runme.sh +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -# - -echo "This script was generated under a different operating system." -echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" -exit - -if [ -z "$PATH" ]; then - PATH=C:/Xilinx/Vivado/2022.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2022.2/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2022.2/bin -else - PATH=C:/Xilinx/Vivado/2022.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2022.2/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2022.2/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.runs/synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log DataMemory.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source DataMemory.tcl diff --git a/data_memory/data_memory/data_memory.runs/synth_1/vivado.jou b/data_memory/data_memory/data_memory.runs/synth_1/vivado.jou deleted file mode 100644 index 64a38db..0000000 --- a/data_memory/data_memory/data_memory.runs/synth_1/vivado.jou +++ /dev/null @@ -1,13 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2022.2 (64-bit) -# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 -# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 -# Start of session at: Sun Oct 1 13:21:12 2023 -# Process ID: 14348 -# Current directory: C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.runs/synth_1 -# Command line: vivado.exe -log DataMemory.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source DataMemory.tcl -# Log file: C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.runs/synth_1/DataMemory.vds -# Journal file: C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.runs/synth_1\vivado.jou -# Running On: ASUS_Robin, OS: Windows, CPU Frequency: 2096 MHz, CPU Physical cores: 8, Host memory: 16576 MB -#----------------------------------------------------------- -source DataMemory.tcl -notrace diff --git a/data_memory/data_memory/data_memory.runs/synth_1/vivado.pb b/data_memory/data_memory/data_memory.runs/synth_1/vivado.pb deleted file mode 100644 index 9fb5f8e..0000000 Binary files a/data_memory/data_memory/data_memory.runs/synth_1/vivado.pb and /dev/null differ diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/DataMemory_TB.tcl b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/DataMemory_TB.tcl deleted file mode 100644 index 1094e45..0000000 --- a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/DataMemory_TB.tcl +++ /dev/null @@ -1,11 +0,0 @@ -set curr_wave [current_wave_config] -if { [string length $curr_wave] == 0 } { - if { [llength [get_objects]] > 0} { - add_wave / - set_property needs_save false [current_wave_config] - } else { - send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." - } -} - -run 1000ns diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/DataMemory_TB_behav.wdb b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/DataMemory_TB_behav.wdb deleted file mode 100644 index e69de29..0000000 diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/DataMemory_TB_vhdl.prj b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/DataMemory_TB_vhdl.prj deleted file mode 100644 index 881518f..0000000 --- a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/DataMemory_TB_vhdl.prj +++ /dev/null @@ -1,7 +0,0 @@ -# compile vhdl design source files -vhdl xil_defaultlib \ -"../../../../data_memory.srcs/sources_1/new/design.vhd" \ -"../../../../data_memory.srcs/sim_1/new/testbench.vhd" \ - -# Do not sort compile order -nosort diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/compile.bat b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/compile.bat deleted file mode 100644 index 2f8f856..0000000 --- a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/compile.bat +++ /dev/null @@ -1,26 +0,0 @@ -@echo off -REM **************************************************************************** -REM Vivado (TM) v2022.2 (64-bit) -REM -REM Filename : compile.bat -REM Simulator : Xilinx Vivado Simulator -REM Description : Script for compiling the simulation design source files -REM -REM Generated by Vivado on Sun Oct 01 13:58:36 +0200 2023 -REM SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 -REM -REM IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 -REM -REM usage: compile.bat -REM -REM **************************************************************************** -REM compile VHDL design sources -echo "xvhdl --incr --relax -prj DataMemory_TB_vhdl.prj" -call xvhdl --incr --relax -prj DataMemory_TB_vhdl.prj -log xvhdl.log -call type xvhdl.log > compile.log -if "%errorlevel%"=="1" goto END -if "%errorlevel%"=="0" goto SUCCESS -:END -exit 1 -:SUCCESS -exit 0 diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/compile.log b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/compile.log deleted file mode 100644 index 437c90f..0000000 --- a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/compile.log +++ /dev/null @@ -1,4 +0,0 @@ -INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.srcs/sources_1/new/design.vhd" into library xil_defaultlib -INFO: [VRFC 10-3107] analyzing entity 'DataMemory' -INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.srcs/sim_1/new/testbench.vhd" into library xil_defaultlib -INFO: [VRFC 10-3107] analyzing entity 'DataMemory_TB' diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/elaborate.bat b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/elaborate.bat deleted file mode 100644 index 9ac3bc9..0000000 --- a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/elaborate.bat +++ /dev/null @@ -1,25 +0,0 @@ -@echo off -REM **************************************************************************** -REM Vivado (TM) v2022.2 (64-bit) -REM -REM Filename : elaborate.bat -REM Simulator : Xilinx Vivado Simulator -REM Description : Script for elaborating the compiled design -REM -REM Generated by Vivado on Sun Oct 01 13:58:38 +0200 2023 -REM SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 -REM -REM IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 -REM -REM usage: elaborate.bat -REM -REM **************************************************************************** -REM elaborate design -echo "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot DataMemory_TB_behav xil_defaultlib.DataMemory_TB -log elaborate.log" -call xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot DataMemory_TB_behav xil_defaultlib.DataMemory_TB -log elaborate.log -if "%errorlevel%"=="0" goto SUCCESS -if "%errorlevel%"=="1" goto END -:END -exit 1 -:SUCCESS -exit 0 diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/elaborate.log b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/elaborate.log deleted file mode 100644 index b8f9748..0000000 --- a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/elaborate.log +++ /dev/null @@ -1,18 +0,0 @@ -Vivado Simulator v2022.2 -Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. -Running: C:/Xilinx/Vivado/2022.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot DataMemory_TB_behav xil_defaultlib.DataMemory_TB -log elaborate.log -Using 2 slave threads. -Starting static elaboration -Completed static elaboration -Starting simulation data flow analysis -Completed simulation data flow analysis -Time Resolution for simulation is 1ps -Compiling package std.standard -Compiling package std.textio -Compiling package ieee.std_logic_1164 -Compiling package ieee.std_logic_arith -Compiling package ieee.std_logic_unsigned -Compiling package ieee.numeric_std -Compiling architecture behavioral of entity xil_defaultlib.DataMemory [datamemory_default] -Compiling architecture behavioral of entity xil_defaultlib.datamemory_tb -Built simulation snapshot DataMemory_TB_behav diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/simulate.bat b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/simulate.bat deleted file mode 100644 index f79309f..0000000 --- a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/simulate.bat +++ /dev/null @@ -1,25 +0,0 @@ -@echo off -REM **************************************************************************** -REM Vivado (TM) v2022.2 (64-bit) -REM -REM Filename : simulate.bat -REM Simulator : Xilinx Vivado Simulator -REM Description : Script for simulating the design by launching the simulator -REM -REM Generated by Vivado on Sun Oct 01 13:58:40 +0200 2023 -REM SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 -REM -REM IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 -REM -REM usage: simulate.bat -REM -REM **************************************************************************** -REM simulate design -echo "xsim DataMemory_TB_behav -key {Behavioral:sim_1:Functional:DataMemory_TB} -tclbatch DataMemory_TB.tcl -log simulate.log" -call xsim DataMemory_TB_behav -key {Behavioral:sim_1:Functional:DataMemory_TB} -tclbatch DataMemory_TB.tcl -log simulate.log -if "%errorlevel%"=="0" goto SUCCESS -if "%errorlevel%"=="1" goto END -:END -exit 1 -:SUCCESS -exit 0 diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/simulate.log b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/simulate.log deleted file mode 100644 index e69de29..0000000 diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xelab.pb b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xelab.pb deleted file mode 100644 index e9bfae5..0000000 Binary files a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xelab.pb and /dev/null differ diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/Compile_Options.txt b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/Compile_Options.txt deleted file mode 100644 index baafceb..0000000 --- a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/Compile_Options.txt +++ /dev/null @@ -1 +0,0 @@ ---incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "DataMemory_TB_behav" "xil_defaultlib.DataMemory_TB" -log "elaborate.log" diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/TempBreakPointFile.txt b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/TempBreakPointFile.txt deleted file mode 100644 index fdbc612..0000000 --- a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/TempBreakPointFile.txt +++ /dev/null @@ -1 +0,0 @@ -Breakpoint File Version 1.0 diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/obj/xsim_0.win64.obj b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/obj/xsim_0.win64.obj deleted file mode 100644 index 11989e3..0000000 Binary files a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/obj/xsim_0.win64.obj and /dev/null differ diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/obj/xsim_1.c b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/obj/xsim_1.c deleted file mode 100644 index 386e734..0000000 --- a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/obj/xsim_1.c +++ /dev/null @@ -1,110 +0,0 @@ -/**********************************************************************/ -/* ____ ____ */ -/* / /\/ / */ -/* /___/ \ / */ -/* \ \ \/ */ -/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ -/* / / All Right Reserved. */ -/* /---/ /\ */ -/* \ \ / \ */ -/* \___\/\___\ */ -/**********************************************************************/ - -#if defined(_WIN32) - #include "stdio.h" - #define IKI_DLLESPEC __declspec(dllimport) -#else - #define IKI_DLLESPEC -#endif -#include "iki.h" -#include -#include -#ifdef __GNUC__ -#include -#else -#include -#define alloca _alloca -#endif -/**********************************************************************/ -/* ____ ____ */ -/* / /\/ / */ -/* /___/ \ / */ -/* \ \ \/ */ -/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ -/* / / All Right Reserved. */ -/* /---/ /\ */ -/* \ \ / \ */ -/* \___\/\___\ */ -/**********************************************************************/ - -#if defined(_WIN32) - #include "stdio.h" - #define IKI_DLLESPEC __declspec(dllimport) -#else - #define IKI_DLLESPEC -#endif -#include "iki.h" -#include -#include -#ifdef __GNUC__ -#include -#else -#include -#define alloca _alloca -#endif -typedef void (*funcp)(char *, char *); -extern int main(int, char**); -IKI_DLLESPEC extern void execute_17(char*, char *); -IKI_DLLESPEC extern void execute_18(char*, char *); -IKI_DLLESPEC extern void execute_16(char*, char *); -IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); -IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); -funcp funcTab[5] = {(funcp)execute_17, (funcp)execute_18, (funcp)execute_16, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback}; -const int NumRelocateId= 5; - -void relocate(char *dp) -{ - iki_relocate(dp, "xsim.dir/DataMemory_TB_behav/xsim.reloc", (void **)funcTab, 5); - iki_vhdl_file_variable_register(dp + 7480); - iki_vhdl_file_variable_register(dp + 7536); - - - /*Populate the transaction function pointer field in the whole net structure */ -} - -void sensitize(char *dp) -{ - iki_sensitize(dp, "xsim.dir/DataMemory_TB_behav/xsim.reloc"); -} - -void simulate(char *dp) -{ - iki_schedule_processes_at_time_zero(dp, "xsim.dir/DataMemory_TB_behav/xsim.reloc"); - // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net - iki_execute_processes(); - - // Schedule resolution functions for the multiply driven Verilog nets that have strength - // Schedule transaction functions for the singly driven Verilog nets that have strength - -} -#include "iki_bridge.h" -void relocate(char *); - -void sensitize(char *); - -void simulate(char *); - -extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); -extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; -extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; - -int main(int argc, char **argv) -{ - iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; - iki_set_sv_type_file_path_name("xsim.dir/DataMemory_TB_behav/xsim.svtype"); - iki_set_crvs_dump_file_path_name("xsim.dir/DataMemory_TB_behav/xsim.crvsdump"); - void* design_handle = iki_create_design("xsim.dir/DataMemory_TB_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); - iki_set_rc_trial_count(100); - (void) design_handle; - return iki_simulate_design(); -} diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/obj/xsim_1.win64.obj b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/obj/xsim_1.win64.obj deleted file mode 100644 index c151de2..0000000 Binary files a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/obj/xsim_1.win64.obj and /dev/null differ diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.dbg b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.dbg deleted file mode 100644 index 9a97997..0000000 Binary files a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.dbg and /dev/null differ diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.mem b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.mem deleted file mode 100644 index bd1a512..0000000 Binary files a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.mem and /dev/null differ diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.reloc b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.reloc deleted file mode 100644 index da309c4..0000000 Binary files a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.reloc and /dev/null differ diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.rlx b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.rlx deleted file mode 100644 index 84beea6..0000000 --- a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.rlx +++ /dev/null @@ -1,12 +0,0 @@ - -{ - crc : 2267898614907848146 , - ccp_crc : 0 , - cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot DataMemory_TB_behav xil_defaultlib.DataMemory_TB" , - buildDate : "Oct 14 2022" , - buildTime : "05:20:55" , - linkCmd : "C:\\Xilinx\\Vivado\\2022.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/DataMemory_TB_behav/xsimk.exe\" \"xsim.dir/DataMemory_TB_behav/obj/xsim_0.win64.obj\" \"xsim.dir/DataMemory_TB_behav/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2022.2\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" , - aggregate_nets : - [ - ] -} \ No newline at end of file diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.rtti b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.rtti deleted file mode 100644 index 7d72f7b..0000000 Binary files a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.rtti and /dev/null differ diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.svtype b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.svtype deleted file mode 100644 index afe268b..0000000 Binary files a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.svtype and /dev/null differ diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.type b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.type deleted file mode 100644 index 5fd5846..0000000 Binary files a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.type and /dev/null differ diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.xdbg b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.xdbg deleted file mode 100644 index 1e20d11..0000000 Binary files a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsim.xdbg and /dev/null differ diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsimSettings.ini b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsimSettings.ini deleted file mode 100644 index 3e34404..0000000 --- a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsimSettings.ini +++ /dev/null @@ -1,50 +0,0 @@ -[General] -ARRAY_DISPLAY_LIMIT=1024 -RADIX=hex -TIME_UNIT=ns -TRACE_LIMIT=65536 -VHDL_ENTITY_SCOPE_FILTER=true -VHDL_PACKAGE_SCOPE_FILTER=false -VHDL_BLOCK_SCOPE_FILTER=true -VHDL_PROCESS_SCOPE_FILTER=false -VHDL_PROCEDURE_SCOPE_FILTER=false -VERILOG_MODULE_SCOPE_FILTER=true -VERILOG_PACKAGE_SCOPE_FILTER=false -VERILOG_BLOCK_SCOPE_FILTER=false -VERILOG_TASK_SCOPE_FILTER=false -VERILOG_PROCESS_SCOPE_FILTER=false -INPUT_OBJECT_FILTER=true -OUTPUT_OBJECT_FILTER=true -INOUT_OBJECT_FILTER=true -INTERNAL_OBJECT_FILTER=true -CONSTANT_OBJECT_FILTER=true -VARIABLE_OBJECT_FILTER=true -INPUT_PROTOINST_FILTER=true -OUTPUT_PROTOINST_FILTER=true -INOUT_PROTOINST_FILTER=true -INTERNAL_PROTOINST_FILTER=true -CONSTANT_PROTOINST_FILTER=true -VARIABLE_PROTOINST_FILTER=true -SCOPE_NAME_COLUMN_WIDTH=143 -SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 -SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 -OBJECT_NAME_COLUMN_WIDTH=75 -OBJECT_VALUE_COLUMN_WIDTH=75 -OBJECT_DATA_TYPE_COLUMN_WIDTH=75 -PROCESS_NAME_COLUMN_WIDTH=0 -PROCESS_TYPE_COLUMN_WIDTH=0 -FRAME_INDEX_COLUMN_WIDTH=0 -FRAME_NAME_COLUMN_WIDTH=0 -FRAME_FILE_NAME_COLUMN_WIDTH=0 -FRAME_LINE_NUM_COLUMN_WIDTH=0 -LOCAL_NAME_COLUMN_WIDTH=0 -LOCAL_VALUE_COLUMN_WIDTH=0 -LOCAL_DATA_TYPE_COLUMN_WIDTH=0 -PROTO_NAME_COLUMN_WIDTH=0 -PROTO_VALUE_COLUMN_WIDTH=0 -INPUT_LOCAL_FILTER=1 -OUTPUT_LOCAL_FILTER=1 -INOUT_LOCAL_FILTER=1 -INTERNAL_LOCAL_FILTER=1 -CONSTANT_LOCAL_FILTER=1 -VARIABLE_LOCAL_FILTER=1 diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsimcrash.log b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsimcrash.log deleted file mode 100644 index e69de29..0000000 diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsimk.exe b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsimk.exe deleted file mode 100644 index b7f87a5..0000000 Binary files a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsimk.exe and /dev/null differ diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsimkernel.log b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/DataMemory_TB_behav/xsimkernel.log deleted file mode 100644 index e69de29..0000000 diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/datamemory.vdb b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/datamemory.vdb deleted file mode 100644 index 781ba42..0000000 Binary files a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/datamemory.vdb and /dev/null differ diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/datamemory_tb.vdb b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/datamemory_tb.vdb deleted file mode 100644 index 7483009..0000000 Binary files a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/datamemory_tb.vdb and /dev/null differ diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx deleted file mode 100644 index 7a621a9..0000000 --- a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx +++ /dev/null @@ -1,6 +0,0 @@ -0.7 -2020.2 -Oct 14 2022 -05:20:55 -C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.srcs/sim_1/new/testbench.vhd,1696161441,vhdl,,,,datamemory_tb,,,,,,,, -C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.srcs/sources_1/new/design.vhd,1696161504,vhdl,C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.srcs/sim_1/new/testbench.vhd,,,datamemory,,,,,,,, diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.ini b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.ini deleted file mode 100644 index e8199b2..0000000 --- a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xsim.ini +++ /dev/null @@ -1 +0,0 @@ -xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xvhdl.log b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xvhdl.log deleted file mode 100644 index 437c90f..0000000 --- a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xvhdl.log +++ /dev/null @@ -1,4 +0,0 @@ -INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.srcs/sources_1/new/design.vhd" into library xil_defaultlib -INFO: [VRFC 10-3107] analyzing entity 'DataMemory' -INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/robin/Dev/memory_file/data_memory/data_memory/data_memory.srcs/sim_1/new/testbench.vhd" into library xil_defaultlib -INFO: [VRFC 10-3107] analyzing entity 'DataMemory_TB' diff --git a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xvhdl.pb b/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xvhdl.pb deleted file mode 100644 index 4fe5ca4..0000000 Binary files a/data_memory/data_memory/data_memory.sim/sim_1/behav/xsim/xvhdl.pb and /dev/null differ