diff --git a/instruction_memory/memory_file.xpr b/instruction_memory/memory_file.xpr new file mode 100644 index 0000000..58bbd2f --- /dev/null +++ b/instruction_memory/memory_file.xpr @@ -0,0 +1,235 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/instruction_memory/src/instruction.vhd b/instruction_memory/src/instruction.vhd new file mode 100644 index 0000000..1a0e6d8 --- /dev/null +++ b/instruction_memory/src/instruction.vhd @@ -0,0 +1,40 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity instruction is + port( + instruction: in STD_LOGIC_VECTOR(7 downto 0); + code: out STD_LOGIC_VECTOR(31 downto 0); + clk: in STD_LOGIC + ); + + -- Array of STD_LOGIC_VECTOR + type code_array is array(0 to 256) of + STD_LOGIC_VECTOR(31 downto 0); + + -- Initialize the code memory + function init return code_array is + variable init_result: code_array; + begin + --do something (e.g. read data from a file, perform some initialization calculation, ...) + -- Exemple : + for i in code_array'range loop + init_result(i) := std_logic_vector(conv_unsigned(i, 32)); + end loop; + return init_result; + end function init; +end instruction; + +architecture behavior_instr of instruction is + -- Memory variable + signal code_memory: code_array := init; +begin + process(instruction, clk) is + begin + if clk'event AND clk = '1' then + code <= code_memory(CONV_INTEGER(UNSIGNED(instruction))); + end if; + end process; +end behavior_instr; \ No newline at end of file diff --git a/instruction_memory/src/sim_instruction.vhd b/instruction_memory/src/sim_instruction.vhd new file mode 100644 index 0000000..db14e8d --- /dev/null +++ b/instruction_memory/src/sim_instruction.vhd @@ -0,0 +1,31 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity test_instr is +end test_instr; + +architecture bench of test_instr is + component instruction is + port( + instruction: in STD_LOGIC_VECTOR(7 downto 0); + code: out STD_LOGIC_VECTOR(31 downto 0); + clk: in STD_LOGIC + ); + end component; + + for all : instruction use entity work.instruction; + + signal inAddress : STD_LOGIC_VECTOR(7 downto 0); + signal outCode : STD_LOGIC_VECTOR(31 downto 0); + signal inClock : STD_LOGIC := '0'; + +begin + testeur: instruction PORT MAP(inAddress, outCode, inClock); + inClock <= not inClock after 1ns; + + inAddress <= X"00", X"0a" after 10ns; + +end bench;