From d823f37938586efbcfd24ae6db89a2eceb71252e Mon Sep 17 00:00:00 2001 From: Yohan Boujon Date: Sun, 1 Oct 2023 23:17:50 +0200 Subject: [PATCH] Added basic behavior, Added Vivado Project file --- memory_file.xpr | 234 ++++++++++++++++++++++++++++++++++++++++ src/instruction.vhd | 34 ++++-- src/sim_instruction.vhd | 4 +- 3 files changed, 262 insertions(+), 10 deletions(-) create mode 100644 memory_file.xpr diff --git a/memory_file.xpr b/memory_file.xpr new file mode 100644 index 0000000..57f70ee --- /dev/null +++ b/memory_file.xpr @@ -0,0 +1,234 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/src/instruction.vhd b/src/instruction.vhd index 08ab29f..9caf15d 100644 --- a/src/instruction.vhd +++ b/src/instruction.vhd @@ -4,21 +4,37 @@ use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity instruction is -port( - instruction: in STD_LOGIC_VECTOR(7 downto 0); - code: out STD_LOGIC_VECTOR(31 downto 0); - clk: in STD_LOGIC -); + port( + instruction: in STD_LOGIC_VECTOR(7 downto 0); + code: out STD_LOGIC_VECTOR(31 downto 0); + clk: in STD_LOGIC + ); + + -- Array of STD_LOGIC_VECTOR + type code_array is array(0 to 256) of + STD_LOGIC_VECTOR(31 downto 0); + + -- Initialize the code memory + function init return code_array is + variable init_result: code_array; + begin + --do something (e.g. read data from a file, perform some initialization calculation, ...) + -- Exemple : + for i in code_array'range loop + init_result(i) := (others => '0'); + end loop; + return init_result; + end function init; end instruction; architecture behavior_instr of instruction is - -- Array of STD_LOGIC_VECTOR - type code_array is array(0 to 15) of - STD_LOGIC_VECTOR(7 downto 0); -- Memory variable - signal code_memory: code_array; + signal code_memory: code_array := init; begin process(instruction, clk) is begin + if clk'event AND clk = '1' then + code <= code_memory(CONV_INTEGER(UNSIGNED(instruction))); + end if; end process; end behavior_instr; \ No newline at end of file diff --git a/src/sim_instruction.vhd b/src/sim_instruction.vhd index 6a8c3eb..db14e8d 100644 --- a/src/sim_instruction.vhd +++ b/src/sim_instruction.vhd @@ -11,7 +11,7 @@ architecture bench of test_instr is component instruction is port( instruction: in STD_LOGIC_VECTOR(7 downto 0); - code: in STD_LOGIC_VECTOR(31 downto 0); + code: out STD_LOGIC_VECTOR(31 downto 0); clk: in STD_LOGIC ); end component; @@ -24,6 +24,8 @@ architecture bench of test_instr is begin testeur: instruction PORT MAP(inAddress, outCode, inClock); + inClock <= not inClock after 1ns; + inAddress <= X"00", X"0a" after 10ns; end bench;