src/instruction.vhd

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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity instruction is
+port(
+  instruction:  in  STD_LOGIC_VECTOR(7 downto 0);
+  code:         out STD_LOGIC_VECTOR(31 downto 0);
+  clk:          in  STD_LOGIC
+);
+end instruction;
+
+architecture behavior_instr of instruction is
+    -- Array of STD_LOGIC_VECTOR
+    type code_array is array(0 to 15) of
+        STD_LOGIC_VECTOR(7 downto 0);
+    -- Memory variable
+    signal code_memory: code_array;
+begin
+    process(instruction, clk) is
+    begin
+    end process;
+end behavior_instr;

src/sim_instruction.vhd

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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity test_instr is
+end test_instr;
+
+architecture bench of test_instr is
+  component instruction is
+    port(
+      instruction:  in  STD_LOGIC_VECTOR(7 downto 0);
+      code:         in STD_LOGIC_VECTOR(31 downto 0);
+      clk:          in  STD_LOGIC
+    );
+  end component;
+
+  for all : instruction use entity work.instruction;
+
+  signal inAddress : STD_LOGIC_VECTOR(7 downto 0);
+  signal outCode : STD_LOGIC_VECTOR(31 downto 0);
+  signal inClock : STD_LOGIC := '0';
+  
+begin
+    testeur: instruction PORT MAP(inAddress, outCode, inClock);
+    
+
+end bench;