40 lines
No EOL
1.1 KiB
VHDL
40 lines
No EOL
1.1 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity instruction is
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port(
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instruction: in STD_LOGIC_VECTOR(7 downto 0);
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code: out STD_LOGIC_VECTOR(31 downto 0);
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clk: in STD_LOGIC
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);
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-- Array of STD_LOGIC_VECTOR
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type code_array is array(0 to 256) of
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STD_LOGIC_VECTOR(31 downto 0);
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-- Initialize the code memory
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function init return code_array is
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variable init_result: code_array;
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begin
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--do something (e.g. read data from a file, perform some initialization calculation, ...)
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-- Exemple :
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for i in code_array'range loop
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init_result(i) := std_logic_vector(conv_unsigned(i, 32));
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end loop;
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return init_result;
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end function init;
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end instruction;
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architecture behavior_instr of instruction is
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-- Memory variable
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signal code_memory: code_array := init;
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begin
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process(instruction, clk) is
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begin
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if clk'event AND clk = '1' then
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code <= code_memory(CONV_INTEGER(UNSIGNED(instruction)));
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end if;
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end process;
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end behavior_instr; |