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Fixed li links that are no longer required. Switch case done after step1_lidi. Fixed di_A being faster.

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This commit is contained in:
Yohan Boujon 2023-11-21 17:40:22 +01:00
parent 8bf6e8aa4d
commit 3958f90873
2 changed files with 14 additions and 15 deletions
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2
cpu_project/cpu_project.xpr
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@ -60,7 +60,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="WTXSimLaunchSim" Val="65"/>
<Option Name="WTXSimLaunchSim" Val="75"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>

27
src/cpu.vhd
View file

@ -67,12 +67,12 @@ ARCHITECTURE cpu_arch OF cpu IS
);
END COMPONENT;
signal li_A, di_A, ex_A, mem_A, re_A : STD_LOGIC_VECTOR(7 downto 0);
signal li_B, ex_B, mem_B, re_B : STD_LOGIC_VECTOR(7 downto 0);
signal li_C, di_C, ex_C, mem_C, re_C : STD_LOGIC_VECTOR(7 downto 0);
signal li_OP, di_OP, ex_OP, mem_OP, re_OP : STD_LOGIC_VECTOR(3 downto 0);
signal ex_A, mem_A, re_A : STD_LOGIC_VECTOR(7 downto 0);
signal ex_B, mem_B, re_B : STD_LOGIC_VECTOR(7 downto 0);
signal di_C, ex_C, mem_C, re_C : STD_LOGIC_VECTOR(7 downto 0);
signal ex_OP, mem_OP, re_OP : STD_LOGIC_VECTOR(3 downto 0);
-- Banc de registres
signal di_B_in, di_B_out, qA : STD_LOGIC_VECTOR(7 downto 0);
signal di_A_in, di_A_out, di_B_in, di_B_out, qA : STD_LOGIC_VECTOR(7 downto 0);
signal di_OP_in, di_OP_out : STD_LOGIC_VECTOR(3 downto 0);
signal write_enable : STD_LOGIC;
@ -85,13 +85,13 @@ ARCHITECTURE cpu_arch OF cpu IS
signal empty_4 : STD_LOGIC_VECTOR(3 downto 0);
begin
step1_lidi : pipeline_step PORT MAP(li_A, li_B, li_C, inst(7 downto 4), clk, di_A, di_B_out, di_C, di_OP_out);
step2_diex : pipeline_step PORT MAP(di_A, di_B_in, di_C, di_OP_in, clk, ex_A, ex_B, ex_C, ex_OP);
step1_lidi : pipeline_step PORT MAP(inst(23 downto 16), inst(15 downto 8), inst(7 downto 0), inst(27 downto 24), clk, di_A_out, di_B_out, di_C, di_OP_out);
step2_diex : pipeline_step PORT MAP(di_A_in, di_B_in, di_C, di_OP_in, clk, ex_A, ex_B, ex_C, ex_OP);
step3_exmem : pipeline_step PORT MAP(ex_A, ex_B, ex_C, ex_OP, clk, mem_A, mem_B, mem_C, mem_OP);
step4_memre : pipeline_step PORT MAP(mem_A, mem_B, mem_C, mem_OP, clk, re_A, re_B, re_C, re_OP);
instruction_memory_inst : instruction PORT MAP(PC, inst , clk);
memory_register_inst : reg PORT MAP(li_B(3 downto 0), empty_4, re_A(3 downto 0), re_OP(0), re_B, '1', clk, qA, empty_8);
memory_register_inst : reg PORT MAP(di_B_out(3 downto 0), empty_4, re_A(3 downto 0), re_OP(0), re_B, '1', clk, qA, empty_8);
-- alu_inst : alu PORT MAP();
-- data_memory_inst : data_memory PORT MAP();
@ -99,22 +99,21 @@ begin
process(clk)
begin
if clk'event and clk='1' then
li_OP <= inst(27 downto 24);
li_A <= inst(23 downto 16);
li_B <= inst(15 downto 8);
li_C <= inst(7 downto 0);
-- In this case, copy the content of li_A directly to di_A (just the idea)
case li_OP is
case di_OP_out is
-- AFC
when X"6" =>
di_B_in <= li_B;
di_B_in <= di_B_out;
di_A_in <= di_A_out;
di_OP_in <= "0001";
-- In this case, put the content in memory_register_inst and get QA in di_A (just the idea)
when X"5" =>
di_B_in <= qA;
di_A_in <= di_A_out;
di_OP_in <= "0001";
when others =>
di_B_in <= di_B_out;
di_A_in <= di_A_out;
di_OP_in <= di_OP_out;
end case;
PC <= PC+'1';