diff --git a/cpu_project/cpu_project.xpr b/cpu_project/cpu_project.xpr
index e83f68d..faa5cc1 100644
--- a/cpu_project/cpu_project.xpr
+++ b/cpu_project/cpu_project.xpr
@@ -60,7 +60,7 @@
-
+
@@ -176,6 +176,11 @@
+
+
+
+
+
@@ -189,6 +194,7 @@
+
diff --git a/cpu_project/simu_save_1.wcfg b/cpu_project/simu_save_1.wcfg
new file mode 100644
index 0000000..e10155e
--- /dev/null
+++ b/cpu_project/simu_save_1.wcfg
@@ -0,0 +1,75 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ inClock
+ inClock
+
+
+ Memory[0:255][7:0]
+ Memory[0:255][7:0]
+
+
+ OP_LI_DI[7:0]
+ OP_LI_DI[7:0]
+
+
+ OP_DI_EX[7:0]
+ OP_DI_EX[7:0]
+
+
+ OP_EX_MEM[7:0]
+ OP_EX_MEM[7:0]
+
+
+ OP_MEM_RE[7:0]
+ OP_MEM_RE[7:0]
+
+
+ W_ENABLE_HANDLE
+ W_ENABLE_HANDLE
+
+
+ W_ADDRESS_HANDLE[3:0]
+ W_ADDRESS_HANDLE[3:0]
+
+
+ W_DATA_HANDLE[7:0]
+ W_DATA_HANDLE[7:0]
+
+
+ DATAMEM_DATA_OUT[7:0]
+ DATAMEM_DATA_OUT[7:0]
+
+
+ B_MEM_RE[7:0]
+ B_MEM_RE[7:0]
+
+
+ memory[0:15][7:0]
+ memory[0:15][7:0]
+
+
+
+ Memory[0:255][7:0]
+ Memory[0:255][7:0]
+
+
diff --git a/src/cpu.vhd b/src/cpu.vhd
index 558a654..205f82a 100644
--- a/src/cpu.vhd
+++ b/src/cpu.vhd
@@ -104,6 +104,8 @@ ARCHITECTURE cpu_arch OF cpu IS
signal DATAMEM_ADDRESS : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal DATAMEM_DATA_IN : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal DATAMEM_DATA_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+ signal temp : STD_LOGIC_VECTOR(7 DOWNTO 0) := X"00";
BEGIN
@@ -180,10 +182,17 @@ BEGIN
DI_EX: process(clk)
begin
if rising_edge(clk) then
- if OP_DI_EX = X"06" then
+ if OP_DI_EX = X"06" then -- AFC
OP_EX_MEM <= OP_DI_EX;
A_EX_MEM <= A_DI_EX;
- B_EX_MEM <= B_DI_EX;
+ B_EX_MEM <= B_DI_EX;
+ elsif OP_DI_EX = X"07" then -- LOAD
+ OP_EX_MEM <= OP_DI_EX;
+ A_EX_MEM <= A_DI_EX;
+ B_EX_MEM <= B_DI_EX;
+
+ DATAMEM_RESET <= '0';
+ DATAMEM_ADDRESS <= B_DI_EX;
elsif OP_DI_EX = X"05" or OP_DI_EX = X"08" then -- COPY / STORE
OP_EX_MEM <= OP_DI_EX;
A_EX_MEM <= A_DI_EX;
@@ -224,9 +233,13 @@ BEGIN
elsif OP_EX_MEM = X"08" then -- STORE
OP_MEM_RE <= OP_EX_MEM;
DATAMEM_RESET <= '0';
- DATAMEM_RW_ENABLE <= '0'; -- Ecriture
DATAMEM_DATA_IN <= B_EX_MEM; -- On met ce qu'il y a dans B
DATAMEM_ADDRESS <= A_EX_MEM; -- A l'adresse de A
+ elsif OP_EX_MEM = X"07" then -- LOAD
+ OP_MEM_RE <= OP_EX_MEM;
+ A_MEM_RE <= A_EX_MEM;
+ B_MEM_RE <= DATAMEM_DATA_OUT;
+ temp <= X"01";
else
OP_MEM_RE <= X"00";
A_MEM_RE <= X"00";
@@ -243,6 +256,9 @@ BEGIN
if OP_MEM_RE = X"06" or OP_MEM_RE = X"05" or OP_MEM_RE = X"01" or OP_MEM_RE = X"02" or OP_MEM_RE = X"03" then
W_ADDRESS_HANDLE <= A_MEM_RE(3 downto 0);
W_DATA_HANDLE <= B_MEM_RE;
+ elsif OP_MEM_RE = X"07" then
+ W_ADDRESS_HANDLE <= A_MEM_RE(3 downto 0);
+ W_DATA_HANDLE <= B_MEM_RE;
elsif OP_MEM_RE = X"08" then
null;
else
@@ -252,11 +268,11 @@ BEGIN
end process;
- -- W_ENABLE HANDLING "MUX"
+ -- W_ENABLE HANDLING MUX
process(clk)
begin
if rising_edge(clk) then
- if OP_MEM_RE = X"06" or OP_MEM_RE = X"05" or OP_MEM_RE = X"01" or OP_MEM_RE = X"02" or OP_MEM_RE = X"03" then
+ if OP_MEM_RE = X"06" or OP_MEM_RE = X"05" or OP_MEM_RE = X"01" or OP_MEM_RE = X"02" or OP_MEM_RE = X"03" or OP_MEM_RE = X"07" then
W_ENABLE_HANDLE <= '1';
else
W_ENABLE_HANDLE <= '0';
@@ -264,6 +280,11 @@ BEGIN
end if;
end process;
+ -- DATAMEM_RW_ENABLE HANDLING MUX
+ DATAMEM_RW_ENABLE <= '1' when OP_DI_EX = X"07" else -- Lecture pour instruction 0x07
+ '0' when OP_EX_MEM = X"08" else -- Ecriture pour instruction 0x08
+ '0';
+
PC_UPDATE: process(clk)
begin
if rising_edge(clk) then
diff --git a/src/instruction_memory.vhd b/src/instruction_memory.vhd
index b971e82..c66cdfb 100644
--- a/src/instruction_memory.vhd
+++ b/src/instruction_memory.vhd
@@ -49,9 +49,14 @@ entity instruction is
init_result(19) := X"03020303"; -- Soustraction 1 - 1
init_result(20) := X"03020504"; -- Soustraction 3 - 2
-- STORE
- init_result(21) := X"08000100";
+ init_result(21) := X"08000100"; -- On store R01 à l'adresse @00
-- LOAD
- -- init_result(22) := X"07000000";
+ init_result(22) := X"00000000";
+ init_result(23) := X"00000000";
+ init_result(24) := X"00000000";
+ init_result(25) := X"00000000";
+ init_result(26) := X"00000000";
+ init_result(27) := X"07070000"; -- On load ce qu'il y a à @00 dans R7
return init_result;
end function init;