From 4c1983c39ddb2d320538b22d06c23db818e201e7 Mon Sep 17 00:00:00 2001
From: Yohan Boujon <yo.boujon@gmail.com>
Date: Wed, 22 Nov 2023 12:17:24 +0100
Subject: [PATCH] Finished store. Boilerplate for load.

---
 cpu_project/cpu_project.xpr | 27 ++++++++++++++++--------
 src/cpu.vhd                 | 41 ++++++++++++++++++++++++++++---------
 src/instruction_memory.vhd  |  2 ++
 src/mux/mux_bdr.vhd         |  1 +
 src/mux/mux_mem_ldr.vhd     | 20 ++++++++++++++++++
 src/mux/mux_mem_str.vhd     | 21 +++++++++++++++++++
 6 files changed, 94 insertions(+), 18 deletions(-)
 create mode 100644 src/mux/mux_mem_ldr.vhd
 create mode 100644 src/mux/mux_mem_str.vhd

diff --git a/cpu_project/cpu_project.xpr b/cpu_project/cpu_project.xpr
index 5c83a46..22f6fda 100644
--- a/cpu_project/cpu_project.xpr
+++ b/cpu_project/cpu_project.xpr
@@ -60,7 +60,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="125"/>
+    <Option Name="WTXSimLaunchSim" Val="153"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -97,6 +97,12 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PPRDIR/../src/data_memory.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PPRDIR/../src/instruction_memory.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -109,6 +115,18 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PPRDIR/../src/mux/mux_mem_ldr.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/mux/mux_mem_str.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PPRDIR/../src/mux/mux_ual.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -133,13 +151,6 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PPRDIR/../src/data_memory.vhd">
-        <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="cpu"/>
diff --git a/src/cpu.vhd b/src/cpu.vhd
index 5b806f3..cf1706f 100644
--- a/src/cpu.vhd
+++ b/src/cpu.vhd
@@ -27,6 +27,22 @@ ARCHITECTURE cpu_arch OF cpu IS
             mux_sortie: OUT STD_LOGIC_VECTOR(7 downto 0)
         );
     END COMPONENT;
+    COMPONENT mux_mem_str IS
+        PORT (
+            mux_op: IN STD_LOGIC_VECTOR(3 downto 0);
+            mux_b_in: IN STD_LOGIC_VECTOR(7 downto 0);
+            mux_mem_out_in: IN STD_LOGIC_VECTOR(7 downto 0);
+            mux_sortie: OUT STD_LOGIC_VECTOR(7 downto 0)
+        );
+    END COMPONENT;
+    COMPONENT mux_mem_ldr IS
+        PORT (
+            mux_op: IN STD_LOGIC_VECTOR(3 downto 0);
+            mux_a_in: IN STD_LOGIC_VECTOR(7 downto 0);
+            mux_b_in: IN STD_LOGIC_VECTOR(7 downto 0);
+            mux_sortie: OUT STD_LOGIC_VECTOR(7 downto 0)
+        );
+    END COMPONENT;
 
     -- Logical components and memory
     COMPONENT instruction IS
@@ -85,11 +101,6 @@ ARCHITECTURE cpu_arch OF cpu IS
       OP_out:   out  STD_LOGIC_VECTOR(3 downto 0)
     );
     END COMPONENT;
-
-    signal mem_A, re_A  : STD_LOGIC_VECTOR(7 downto 0);
-    signal mem_B, re_B : STD_LOGIC_VECTOR(7 downto 0);
-    signal mem_C, re_C : STD_LOGIC_VECTOR(7 downto 0);
-    signal mem_OP, re_OP : STD_LOGIC_VECTOR(3 downto 0);
     
     -- Banc de registres
     signal di_A, di_B_in, di_B_out, di_C_in, di_C_out, qA : STD_LOGIC_VECTOR(7 downto 0);
@@ -99,14 +110,18 @@ ARCHITECTURE cpu_arch OF cpu IS
     signal ex_A, ex_B_out, ex_B_in, ex_C, S_ALU : STD_LOGIC_VECTOR(7 downto 0);
     signal ex_OP : STD_LOGIC_VECTOR(3 downto 0);
     signal OP_ALU : STD_LOGIC_VECTOR(2 downto 0);
+    -- Memoire des donnees
+    signal mem_A, mem_B_in, mem_B_out, mem_C, mem_address, mem_data : STD_LOGIC_VECTOR(7 downto 0);
+    signal mem_OP: STD_LOGIC_VECTOR(3 downto 0);
+    signal RW_MEM: STD_LOGIC;
     -- Step 4
+    signal re_A, re_B, re_C : STD_LOGIC_VECTOR(7 downto 0);
+    signal re_OP : STD_LOGIC_VECTOR(3 downto 0);
     signal W_enable: STD_LOGIC;
 
     --- internal component of cpu
     signal inst : STD_LOGIC_VECTOR(31 downto 0);
     signal PC : STD_LOGIC_VECTOR(7 downto 0) := X"00";
-    ---signal main_clk : STD_LOGIC;
-    
     signal empty_8 : STD_LOGIC_VECTOR(7 downto 0);
     signal empty_4 : STD_LOGIC_VECTOR(3 downto 0);
     
@@ -130,11 +145,17 @@ begin
     mux_ual_inst :  mux_ual PORT MAP(ex_OP,ex_B_out,S_ALU,ex_B_in);
     
     -- rest for now
-    step3_exmem : pipeline_step PORT MAP(ex_A, ex_B_in, ex_C, ex_OP, clk, mem_A, mem_B, mem_C, mem_OP);
-    step4_memre : pipeline_step PORT MAP(mem_A, mem_B, mem_C, mem_OP, clk, re_A, re_B, re_C, re_OP);
-    -- data_memory_inst        : data_memory PORT MAP();
+    step3_exmem :       pipeline_step PORT MAP(ex_A, ex_B_in, ex_C, ex_OP, clk, mem_A, mem_B_in, mem_C, mem_OP);
+    mux_mem_ldr_inst :  mux_mem_ldr PORT MAP(mem_OP, mem_A, mem_B_in, mem_address);
+    with mem_OP select
+    RW_MEM <=   '0' when X"8",
+                '1' when others;
+    data_memory_inst :  data_memory PORT MAP(clk, '0', RW_MEM, mem_address, mem_B_in, mem_data);
+    mux_mem_str_inst :  mux_mem_str PORT MAP(mem_OP, mem_B_in, mem_data, mem_B_out);
 
+    -- Penser à changer comment le write fonctionne pour permettre le LOAD
     -- step4 pipeline
+    step4_memre : pipeline_step PORT MAP(mem_A, mem_B_out, mem_C, mem_OP, clk, re_A, re_B, re_C, re_OP);
     -- LC step 4
     with re_OP select
         W_enable <= '1' when X"6",
diff --git a/src/instruction_memory.vhd b/src/instruction_memory.vhd
index d211f97..1d1402e 100644
--- a/src/instruction_memory.vhd
+++ b/src/instruction_memory.vhd
@@ -32,6 +32,8 @@ entity instruction is
         init_result(6) := X"01060102"; -- ADD R06=R01+R02
         init_result(7) := X"02070103"; -- MUL R07=R01*R03
         init_result(8) := X"03080201"; -- SOUS R08=R01-R02
+        init_result(9) := X"08000100"; -- STORE [@00] <- R01
+        init_result(20) := X"07090000"; -- LOAD R09 -< [@00]
         return init_result;
     end function init;
 end instruction;
diff --git a/src/mux/mux_bdr.vhd b/src/mux/mux_bdr.vhd
index 46736d4..b2afd09 100644
--- a/src/mux/mux_bdr.vhd
+++ b/src/mux/mux_bdr.vhd
@@ -19,5 +19,6 @@ begin
                         mux_qa_in when X"1",
                         mux_qa_in when X"2",
                         mux_qa_in when X"3",
+                        mux_qa_in when X"8",
                         mux_b_in when others;
 end Behavioral;
\ No newline at end of file
diff --git a/src/mux/mux_mem_ldr.vhd b/src/mux/mux_mem_ldr.vhd
new file mode 100644
index 0000000..bfcc3d5
--- /dev/null
+++ b/src/mux/mux_mem_ldr.vhd
@@ -0,0 +1,20 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity mux_mem_ldr is
+    PORT (
+        mux_op: IN STD_LOGIC_VECTOR(3 downto 0);
+        mux_a_in: IN STD_LOGIC_VECTOR(7 downto 0);
+        mux_b_in: IN STD_LOGIC_VECTOR(7 downto 0);
+        mux_sortie: OUT STD_LOGIC_VECTOR(7 downto 0)
+    );
+end mux_mem_ldr;
+
+architecture Behavioral of mux_mem_ldr is
+begin
+    with mux_op select
+        mux_sortie <=   mux_a_in when X"8", -- store @a
+                        mux_b_in when others;
+end Behavioral;
\ No newline at end of file
diff --git a/src/mux/mux_mem_str.vhd b/src/mux/mux_mem_str.vhd
new file mode 100644
index 0000000..2470b31
--- /dev/null
+++ b/src/mux/mux_mem_str.vhd
@@ -0,0 +1,21 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity mux_mem_str is
+    PORT (
+        mux_op: IN STD_LOGIC_VECTOR(3 downto 0);
+        mux_b_in: IN STD_LOGIC_VECTOR(7 downto 0);
+        mux_mem_out_in: IN STD_LOGIC_VECTOR(7 downto 0);
+        mux_sortie: OUT STD_LOGIC_VECTOR(7 downto 0)
+    );
+end mux_mem_str;
+
+architecture Behavioral of mux_mem_str is
+begin
+    with mux_op select
+        mux_sortie <=   mux_mem_out_in when X"7",
+                        mux_mem_out_in when X"8",
+                        mux_b_in when others;
+end Behavioral;
\ No newline at end of file