INSA/vhdl_processor
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Lemonochrome 2023-12-03 11:53:16 +01:00
parent ca7412e7c7
commit 5325019c07
3 changed files with 49 additions and 16 deletions
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25
cpu_project/cpu_project.xpr
View file

@ -60,7 +60,7 @@
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="892"/>
<Option Name="WTXSimLaunchSim" Val="902"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@ -97,6 +97,12 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/data_memory.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/instruction_memory.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@ -115,13 +121,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/data_memory.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/mux/mux_bdr.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
@ -194,6 +193,14 @@
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<File Path="$PSRCDIR/utils_1/imports/synth_1/cpu.dcp">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedInSteps" Val="synth_1"/>
<Attr Name="AutoDcp" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
@ -218,7 +225,7 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/cpu.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>

35
src/cpu.vhd
View file

@ -98,6 +98,14 @@ ARCHITECTURE cpu_arch OF cpu IS
signal ALU_DATA_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal ALU_FLAGS : STD_LOGIC_VECTOR(3 DOWNTO 0);
-- Data Memory specific signals
signal DATAMEM_RESET : STD_lOGIC := '0'; -- Reset invactif par defaut
signal DATAMEM_RW_ENABLE : STD_lOGIC := '1'; -- Lecture par defaut pour éviter les écritures non voulues
signal DATAMEM_ADDRESS : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal DATAMEM_DATA_IN : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal DATAMEM_DATA_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
-- Instantiation des composants
RegisterFile_Instance: reg PORT MAP (
@ -127,6 +135,14 @@ BEGIN
flags => ALU_FLAGS
);
DataMemory_Instance: data_memory PORT MAP (
clk => clk,
rst => DATAMEM_RESET, -- Reset actif à '1'
rw_enable => DATAMEM_RW_ENABLE, -- Lecture: '1' Ecriture: '0'
addr => DATAMEM_ADDRESS, -- Adresse de la zone mémoire
data_in => DATAMEM_DATA_IN, -- Data écrite à l'adresse addr
data_out => DATAMEM_DATA_OUT -- Data présente à l'adresse addr
);
-- Pipeline
OP_LI_DI <= IR(31 downto 24);
@ -137,17 +153,17 @@ BEGIN
begin
if rising_edge(clk) then
-- Banc de registre
if OP_LI_DI = X"06" then -- AFC
if OP_LI_DI = X"06" or OP_LI_DI = X"07" then -- AFC / LOAD
OP_DI_EX <= OP_LI_DI;
A_DI_EX <= A_LI_DI;
B_DI_EX <= B_LI_DI;
C_DI_EX <= C_LI_DI;
elsif OP_LI_DI = X"05" then -- COPY
elsif OP_LI_DI = X"05" or OP_LI_DI = X"08" then -- COPY / STORE
OP_DI_EX <= OP_LI_DI;
A_DI_EX <= A_LI_DI;
C_DI_EX <= C_LI_DI;
R_ADDRESS_A_HANDLE <= B_LI_DI(3 downto 0);
elsif OP_LI_DI = X"01" or OP_LI_DI = X"02" or OP_LI_DI = X"03" then -- ADD
elsif OP_LI_DI = X"01" or OP_LI_DI = X"02" or OP_LI_DI = X"03" then -- ALU
OP_DI_EX <= OP_LI_DI;
A_DI_EX <= A_LI_DI;
R_ADDRESS_B_HANDLE <= C_LI_DI(3 downto 0);
@ -168,10 +184,10 @@ BEGIN
OP_EX_MEM <= OP_DI_EX;
A_EX_MEM <= A_DI_EX;
B_EX_MEM <= B_DI_EX;
elsif OP_DI_EX = X"05" then
elsif OP_DI_EX = X"05" or OP_DI_EX = X"08" then -- COPY / STORE
OP_EX_MEM <= OP_DI_EX;
A_EX_MEM <= A_DI_EX;
B_EX_MEM <= A_DATA_OUT_HANDLE; -- Pour éviter décallage temporel on passe directement A_DATA_OUT_HANDLE au lieu de B_DI_EX
B_EX_MEM <= A_DATA_OUT_HANDLE; -- Pour éviter tout décallage temporel on passe directement A_DATA_OUT_HANDLE au lieu de B_DI_EX
elsif OP_DI_EX = X"01" or OP_DI_EX = X"02" or OP_DI_EX = X"03" then
-- ALU
OP_EX_MEM <= OP_DI_EX;
@ -205,6 +221,12 @@ BEGIN
OP_MEM_RE <= OP_EX_MEM;
A_MEM_RE <= A_EX_MEM;
B_MEM_RE <= ALU_DATA_OUT;
elsif OP_EX_MEM = X"08" then -- STORE
OP_MEM_RE <= OP_EX_MEM;
DATAMEM_RESET <= '0';
DATAMEM_RW_ENABLE <= '0'; -- Ecriture
DATAMEM_DATA_IN <= B_EX_MEM; -- On met ce qu'il y a dans B
DATAMEM_ADDRESS <= A_EX_MEM; -- A l'adresse de A
else
OP_MEM_RE <= X"00";
A_MEM_RE <= X"00";
@ -221,6 +243,8 @@ BEGIN
if OP_MEM_RE = X"06" or OP_MEM_RE = X"05" or OP_MEM_RE = X"01" or OP_MEM_RE = X"02" or OP_MEM_RE = X"03" then
W_ADDRESS_HANDLE <= A_MEM_RE(3 downto 0);
W_DATA_HANDLE <= B_MEM_RE;
elsif OP_MEM_RE = X"08" then
null;
else
null;
end if;
@ -240,7 +264,6 @@ BEGIN
end if;
end process;
PC_UPDATE: process(clk)
begin
if rising_edge(clk) then

5
src/instruction_memory.vhd
View file

@ -48,7 +48,10 @@ entity instruction is
-- Soustraction
init_result(19) := X"03020303"; -- Soustraction 1 - 1
init_result(20) := X"03020504"; -- Soustraction 3 - 2
-- STORE
init_result(21) := X"08000100";
-- LOAD
-- init_result(22) := X"07000000";
return init_result;
end function init;