INSA/vhdl_processor
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This commit is contained in:
Yohan Boujon 2023-11-27 16:43:24 +01:00
parent 4c1983c39d
commit 549b54dba8
3 changed files with 10 additions and 12 deletions
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2
cpu_project/cpu_project.xpr
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@ -60,7 +60,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="WTXSimLaunchSim" Val="153"/>
<Option Name="WTXSimLaunchSim" Val="199"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>

16
src/cpu.vhd
View file

@ -111,19 +111,17 @@ ARCHITECTURE cpu_arch OF cpu IS
signal ex_OP : STD_LOGIC_VECTOR(3 downto 0);
signal OP_ALU : STD_LOGIC_VECTOR(2 downto 0);
-- Memoire des donnees
signal mem_A, mem_B_in, mem_B_out, mem_C, mem_address, mem_data : STD_LOGIC_VECTOR(7 downto 0);
signal mem_A, mem_B_in, mem_B_out, mem_address, mem_data : STD_LOGIC_VECTOR(7 downto 0);
signal mem_OP: STD_LOGIC_VECTOR(3 downto 0);
signal RW_MEM: STD_LOGIC;
-- Step 4
signal re_A, re_B, re_C : STD_LOGIC_VECTOR(7 downto 0);
signal re_A, re_B : STD_LOGIC_VECTOR(7 downto 0);
signal re_OP : STD_LOGIC_VECTOR(3 downto 0);
signal W_enable: STD_LOGIC;
--- internal component of cpu
signal inst : STD_LOGIC_VECTOR(31 downto 0);
signal PC : STD_LOGIC_VECTOR(7 downto 0) := X"00";
signal empty_8 : STD_LOGIC_VECTOR(7 downto 0);
signal empty_4 : STD_LOGIC_VECTOR(3 downto 0);
begin
instruction_memory_inst : instruction PORT MAP(PC, inst , clk);
@ -144,8 +142,8 @@ begin
alu_inst : alu PORT MAP(ex_B_out, ex_C, OP_ALU, S_ALU);
mux_ual_inst : mux_ual PORT MAP(ex_OP,ex_B_out,S_ALU,ex_B_in);
-- rest for now
step3_exmem : pipeline_step PORT MAP(ex_A, ex_B_in, ex_C, ex_OP, clk, mem_A, mem_B_in, mem_C, mem_OP);
-- step 3 pipeline
step3_exmem : pipeline_step PORT MAP(ex_A, ex_B_in, ex_C, ex_OP, clk, mem_A, mem_B_in, open, mem_OP);
mux_mem_ldr_inst : mux_mem_ldr PORT MAP(mem_OP, mem_A, mem_B_in, mem_address);
with mem_OP select
RW_MEM <= '0' when X"8",
@ -153,12 +151,12 @@ begin
data_memory_inst : data_memory PORT MAP(clk, '0', RW_MEM, mem_address, mem_B_in, mem_data);
mux_mem_str_inst : mux_mem_str PORT MAP(mem_OP, mem_B_in, mem_data, mem_B_out);
-- Penser à changer comment le write fonctionne pour permettre le LOAD
-- step4 pipeline
step4_memre : pipeline_step PORT MAP(mem_A, mem_B_out, mem_C, mem_OP, clk, re_A, re_B, re_C, re_OP);
step4_memre : pipeline_step PORT MAP(mem_A, mem_B_out, X"00", mem_OP, clk, re_A, re_B, open, re_OP);
-- LC step 4
with re_OP select
W_enable <= '1' when X"6",
W_enable <= '1' when X"7",
'1' when X"6",
'1' when X"5",
'1' when X"1",
'1' when X"2",

4
src/instruction_memory.vhd
View file

@ -32,8 +32,8 @@ entity instruction is
init_result(6) := X"01060102"; -- ADD R06=R01+R02
init_result(7) := X"02070103"; -- MUL R07=R01*R03
init_result(8) := X"03080201"; -- SOUS R08=R01-R02
init_result(9) := X"08000100"; -- STORE [@00] <- R01
init_result(20) := X"07090000"; -- LOAD R09 -< [@00]
init_result(9) := X"08010200"; -- STORE [@01] <- R02
init_result(20) := X"07090100"; -- LOAD R09 -< [@01]
return init_result;
end function init;
end instruction;