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Lemonochrome 2023-11-29 21:27:57 +01:00
parent 909de11c18
commit 77791b514a
4 changed files with 124 additions and 65 deletions
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2
cpu_project/cpu_project.xpr
View file

@ -60,7 +60,7 @@
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="501"/>
<Option Name="WTXSimLaunchSim" Val="815"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>

111
src/cpu.vhd
View file

@ -89,10 +89,12 @@ ARCHITECTURE cpu_arch OF cpu IS
signal R_ADDRESS_B_HANDLE : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal W_ADDRESS_HANDLE : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal W_DATA_HANDLE : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal W_ENABLE_HANDLE : STD_LOGIC;
signal W_ENABLE_HANDLE : STD_LOGIC := '0';
signal A_DATA_OUT_HANDLE : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal B_DATA_OUT_HANDLE : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal TEST : STD_LOGIC_VECTOR(7 downto 0) := X"FF";
BEGIN
-- Instantiation des composants
RegisterFile_Instance: reg PORT MAP (
@ -116,6 +118,10 @@ BEGIN
-- Pipeline
OP_LI_DI <= IR(31 downto 24);
A_LI_DI <= IR(23 downto 16);
B_LI_DI <= IR(15 downto 8);
@ -124,15 +130,24 @@ BEGIN
begin
if rising_edge(clk) then
-- Banc de registre
case OP_LI_DI is
when X"06" => -- AFC
OP_DI_EX <= OP_LI_DI;
A_DI_EX <= A_LI_DI;
B_DI_EX <= B_LI_DI;
C_DI_EX <= C_LI_DI;
when others =>
null;
end case;
if OP_LI_DI = X"06" then -- AFC
OP_DI_EX <= OP_LI_DI;
A_DI_EX <= A_LI_DI;
B_DI_EX <= B_LI_DI;
C_DI_EX <= C_LI_DI;
elsif OP_LI_DI = X"05" then
OP_DI_EX <= OP_LI_DI;
A_DI_EX <= A_LI_DI;
C_DI_EX <= C_LI_DI;
-- B_DI_EX <= A_DATA_OUT_HANDLE;
R_ADDRESS_A_HANDLE <= B_LI_DI(3 downto 0);
else
OP_DI_EX <= X"00";
A_DI_EX <= X"00";
B_DI_EX <= X"00";
C_DI_EX <= X"00";
end if;
end if;
end process;
@ -140,15 +155,22 @@ BEGIN
begin
if rising_edge(clk) then
-- Executer instruction si nécéssaire (ALU)
case OP_DI_EX is
when X"06" =>
OP_EX_MEM <= OP_DI_EX;
A_EX_MEM <= A_DI_EX;
B_EX_MEM <= B_DI_EX;
C_EX_MEM <= C_DI_EX;
when others =>
null;
end case;
if OP_DI_EX = X"06" then
OP_EX_MEM <= OP_DI_EX;
A_EX_MEM <= A_DI_EX;
B_EX_MEM <= B_DI_EX;
C_EX_MEM <= C_DI_EX;
elsif OP_DI_EX = X"05" then
OP_EX_MEM <= OP_DI_EX;
A_EX_MEM <= A_DI_EX;
B_EX_MEM <= A_DATA_OUT_HANDLE;
C_EX_MEM <= C_DI_EX;
else
OP_EX_MEM <= X"00";
A_EX_MEM <= X"00";
B_EX_MEM <= X"00";
C_EX_MEM <= X"00";
end if;
end if;
end process;
@ -156,15 +178,17 @@ BEGIN
begin
if rising_edge(clk) then
-- Ecrire ou lire memoire des données
case OP_EX_MEM is
when X"06" =>
OP_MEM_RE <= OP_EX_MEM;
A_MEM_RE <= A_EX_MEM;
B_MEM_RE <= B_EX_MEM;
C_MEM_RE <= C_EX_MEM;
when others =>
null;
end case;
if OP_EX_MEM = X"06" or OP_EX_MEM = X"05" then
OP_MEM_RE <= OP_EX_MEM;
A_MEM_RE <= A_EX_MEM;
B_MEM_RE <= B_EX_MEM;
C_MEM_RE <= C_EX_MEM;
else
OP_MEM_RE <= X"00";
A_MEM_RE <= X"00";
B_MEM_RE <= X"00";
C_MEM_RE <= X"00";
end if;
end if;
end process;
@ -173,17 +197,32 @@ BEGIN
begin
if rising_edge(clk) then
-- Ecrire dans les registres
case OP_MEM_RE is -- Si OP_RE : b c Si OP_MEM : a b
when X"06" =>
W_ENABLE_HANDLE <= '1';
W_ADDRESS_HANDLE <= A_MEM_RE(3 downto 0);
W_DATA_HANDLE <= B_MEM_RE;
when others =>
null;
end case;
if OP_MEM_RE = X"06" then
W_ADDRESS_HANDLE <= A_MEM_RE(3 downto 0);
W_DATA_HANDLE <= B_MEM_RE;
elsif OP_MEM_RE = X"05" then
W_ADDRESS_HANDLE <= A_MEM_RE(3 downto 0);
W_DATA_HANDLE <= B_MEM_RE;
else
null;
end if;
end if;
end process;
-- W_ENABLE HANDLING "MUX"
process(clk)
begin
if rising_edge(clk) then
if OP_MEM_RE = X"06" or OP_MEM_RE = X"05" then
W_ENABLE_HANDLE <= '1';
else
W_ENABLE_HANDLE <= '0';
end if;
end if;
end process;
PC_UPDATE: process(clk)
begin
if rising_edge(clk) then

19
src/instruction_memory.vhd
View file

@ -23,10 +23,21 @@ entity instruction is
for i in code_array'range loop
init_result(i) := std_logic_vector(conv_unsigned(0, 32));
end loop;
init_result(0) := X"06000A0F";
init_result(1) := X"06010B0F";
init_result(2) := X"06020B0F";
init_result(0) := X"0600AA00";
init_result(1) := X"0601BB00";
init_result(2) := X"0602CC00";
init_result(3) := X"0603DD00";
init_result(4) := X"0604EE00";
init_result(5) := X"0605FF00";
init_result(6) := X"00000000";
init_result(7) := X"00000000";
init_result(8) := X"00000000";
init_result(9) := X"00000000";
init_result(10) := X"00000000";
init_result(11) := X"00000000";
init_result(12) := X"00000000";
-- Copy
init_result(13) := X"05000300"; -- Copier ce qu'il y a à @03 à @00
-- init_result(6) := X"0502010F";
return init_result;

49
src/register.vhd
View file

@ -1,40 +1,49 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg is
port(
address_A: in STD_LOGIC_VECTOR(3 downto 0);
address_B: in STD_LOGIC_VECTOR(3 downto 0);
address_W: in STD_LOGIC_VECTOR(3 downto 0);
W_Enable: in STD_LOGIC;
W_Data: in STD_LOGIC_VECTOR(7 downto 0);
reset: in STD_LOGIC;
clk: in STD_LOGIC;
A_Data: out STD_LOGIC_VECTOR(7 downto 0);
B_Data: out STD_LOGIC_VECTOR(7 downto 0)
address_A: in STD_LOGIC_VECTOR(3 downto 0);
address_B: in STD_LOGIC_VECTOR(3 downto 0);
address_W: in STD_LOGIC_VECTOR(3 downto 0);
W_Enable: in STD_LOGIC;
W_Data: in STD_LOGIC_VECTOR(7 downto 0);
reset: in STD_LOGIC;
clk: in STD_LOGIC;
A_Data: out STD_LOGIC_VECTOR(7 downto 0);
B_Data: out STD_LOGIC_VECTOR(7 downto 0)
);
end reg;
architecture behavior_reg of reg is
type memory_array is array(0 to 15) of STD_LOGIC_VECTOR(7 downto 0);
-- Array of STD_LOGIC_VECTOR
type memory_array is array(0 to 15) of
STD_LOGIC_VECTOR(7 downto 0);
-- Memory variable
signal memory: memory_array;
begin
-- bypass
A_Data <= memory(to_integer(unsigned(address_A))) when (W_Enable = '0' or address_A /= address_W)
-- Convert address_A and address_B to integers
-- Using Bypass to avoid delay between Read Data and Write Data if they are at the same time called (WEnable = 1)
A_Data <= memory(CONV_INTEGER(unsigned(address_A))) when (W_Enable = '0' or address_A /= address_W)
else W_Data;
B_Data <= memory(to_integer(unsigned(address_B))) when (W_Enable = '0' or address_B /= address_W)
B_Data <= memory(CONV_INTEGER(unsigned(address_B))) when (W_Enable = '0' or address_B /= address_W)
else W_Data;
process(clk)
-- Write data synchronously
process(clk) is
begin
if rising_edge(clk) then
if reset = '0' then
memory <= (others => (others => '0'));
elsif W_Enable = '1' then
memory(to_integer(unsigned(address_W))) <= W_Data;
-- Reset the memory if shutdown
if reset = '0' then
memory <= (others => "00000000");
end if;
-- Else Doing writing routine at each clock tick
if reset = '1' then
if W_Enable = '1' then
memory(CONV_INTEGER(unsigned(address_W))) <= W_Data;
end if;
end if;
end process;