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ADD, MUL and SOU finished.

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This commit is contained in:
Yohan Boujon 2023-11-22 11:15:55 +01:00
parent 1ce3d7cd2b
commit 799b8c595a
5 changed files with 70 additions and 19 deletions
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21
cpu_project/cpu_project.xpr
View file

@ -60,7 +60,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="WTXSimLaunchSim" Val="96"/>
<Option Name="WTXSimLaunchSim" Val="125"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@ -91,6 +91,12 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../src/alu.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/instruction_memory.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@ -103,6 +109,12 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/mux/mux_ual.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/pipeline_step.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@ -121,13 +133,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/alu.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/data_memory.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>

39
src/cpu.vhd
View file

@ -9,8 +9,16 @@ entity cpu is
);
end cpu;
-- Multiplexers
ARCHITECTURE cpu_arch OF cpu IS
-- Multiplexers
COMPONENT mux_ual IS
PORT (
mux_op: IN STD_LOGIC_VECTOR(3 downto 0);
mux_b_in: IN STD_LOGIC_VECTOR(7 downto 0);
mux_alu_s_in: IN STD_LOGIC_VECTOR(7 downto 0);
mux_sortie: OUT STD_LOGIC_VECTOR(7 downto 0)
);
END COMPONENT;
COMPONENT mux_bdr IS
PORT (
mux_op: IN STD_LOGIC_VECTOR(3 downto 0);
@ -19,6 +27,7 @@ ARCHITECTURE cpu_arch OF cpu IS
mux_sortie: OUT STD_LOGIC_VECTOR(7 downto 0)
);
END COMPONENT;
-- Logical components and memory
COMPONENT instruction IS
PORT (
@ -77,17 +86,18 @@ ARCHITECTURE cpu_arch OF cpu IS
);
END COMPONENT;
signal ex_A, mem_A, re_A : STD_LOGIC_VECTOR(7 downto 0);
signal ex_B, mem_B, re_B : STD_LOGIC_VECTOR(7 downto 0);
signal ex_C, mem_C, re_C : STD_LOGIC_VECTOR(7 downto 0);
signal ex_OP, mem_OP, re_OP : STD_LOGIC_VECTOR(3 downto 0);
signal mem_A, re_A : STD_LOGIC_VECTOR(7 downto 0);
signal mem_B, re_B : STD_LOGIC_VECTOR(7 downto 0);
signal mem_C, re_C : STD_LOGIC_VECTOR(7 downto 0);
signal mem_OP, re_OP : STD_LOGIC_VECTOR(3 downto 0);
-- Banc de registres
signal di_A, di_B_in, di_B_out, di_C_in, di_C_out, qA : STD_LOGIC_VECTOR(7 downto 0);
signal di_OP : STD_LOGIC_VECTOR(3 downto 0);
signal write_enable : STD_LOGIC;
-- UAL
signal ex_A_out, ex_A_in, ex_B_out, ex_B_in, ex_C_out, ex_C_in, S_ALU : STD_LOGIC_VECTOR(7 downto 0);
signal ex_OP_out, ex_OP_in : STD_LOGIC_VECTOR(3 downto 0);
signal ex_A, ex_B_out, ex_B_in, ex_C, S_ALU : STD_LOGIC_VECTOR(7 downto 0);
signal ex_OP : STD_LOGIC_VECTOR(3 downto 0);
signal OP_ALU : STD_LOGIC_VECTOR(2 downto 0);
-- Step 4
signal W_enable: STD_LOGIC;
@ -109,11 +119,18 @@ begin
mux_bdr_inst : mux_bdr PORT MAP(di_OP,di_B_out,qA,di_B_in);
-- step2 pipeline
step2_diex : pipeline_step PORT MAP(di_A, di_B_in, di_C_in, di_OP, clk, ex_A_in, ex_B_in, ex_C_in, ex_OP_in);
-- alu_inst : alu PORT MAP(ex_B_out, ex_C_out, OP_ALU, S_ALU);
step2_diex : pipeline_step PORT MAP(di_A, di_B_in, di_C_in, di_OP, clk, ex_A, ex_B_out, ex_C, ex_OP);
-- LC step 2
with ex_OP select
OP_ALU <= "000" when X"1",
"110" when X"2",
"001" when X"3",
"111" when others;
alu_inst : alu PORT MAP(ex_B_out, ex_C, OP_ALU, S_ALU);
mux_ual_inst : mux_ual PORT MAP(ex_OP,ex_B_out,S_ALU,ex_B_in);
-- rest for now
step3_exmem : pipeline_step PORT MAP(ex_A_in, ex_B_in, ex_C_in, ex_OP_in, clk, mem_A, mem_B, mem_C, mem_OP);
step3_exmem : pipeline_step PORT MAP(ex_A, ex_B_in, ex_C, ex_OP, clk, mem_A, mem_B, mem_C, mem_OP);
step4_memre : pipeline_step PORT MAP(mem_A, mem_B, mem_C, mem_OP, clk, re_A, re_B, re_C, re_OP);
-- data_memory_inst : data_memory PORT MAP();
@ -123,6 +140,8 @@ begin
W_enable <= '1' when X"6",
'1' when X"5",
'1' when X"1",
'1' when X"2",
'1' when X"3",
'0' when others;
process(clk)

5
src/instruction_memory.vhd
View file

@ -25,10 +25,13 @@ entity instruction is
end loop;
init_result(0) := X"06010A00"; -- AFC 0x0a to R01
init_result(1) := X"06020B00"; -- AFC 0x0b to R02
init_result(2) := X"06030C00"; -- AFC 0x0c to R03
init_result(2) := X"06030200"; -- AFC 0x0c to R03
init_result(3) := X"06040D00"; -- AFC 0x0d to R04
init_result(4) := X"06050E00"; -- AFC 0x0e to R05
init_result(5) := X"05000100"; -- COPY R01 to R00
init_result(6) := X"01060102"; -- ADD R06=R01+R02
init_result(7) := X"02070103"; -- MUL R07=R01*R03
init_result(8) := X"03080201"; -- SOUS R08=R01-R02
return init_result;
end function init;
end instruction;

2
src/mux/mux_bdr.vhd
View file

@ -17,5 +17,7 @@ begin
with mux_op select
mux_sortie <= mux_qa_in when X"5",
mux_qa_in when X"1",
mux_qa_in when X"2",
mux_qa_in when X"3",
mux_b_in when others;
end Behavioral;

22
src/mux/mux_ual.vhd Normal file
View file

@ -0,0 +1,22 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_ual is
PORT (
mux_op: IN STD_LOGIC_VECTOR(3 downto 0);
mux_b_in: IN STD_LOGIC_VECTOR(7 downto 0);
mux_alu_s_in: IN STD_LOGIC_VECTOR(7 downto 0);
mux_sortie: OUT STD_LOGIC_VECTOR(7 downto 0)
);
end mux_ual;
architecture Behavioral of mux_ual is
begin
with mux_op select
mux_sortie <= mux_alu_s_in when X"1",
mux_alu_s_in when X"2",
mux_alu_s_in when X"3",
mux_b_in when others;
end Behavioral;