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Hot fix for LOAD: using falling edge to respect timing.

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This commit is contained in:
Yohan Boujon 2023-12-05 20:50:22 +01:00
parent 51b0f03dbb
commit 86d986894c
2 changed files with 4 additions and 12 deletions
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14
cpu_project/cpu_project.xpr
View file

@ -4,7 +4,7 @@
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="63" Path="/home/boujon/Documents/VHDL/vhdl_processor/cpu_project/cpu_project.xpr">
<Project Product="Vivado" Version="7" Minor="63" Path="/home/alzyohan/Documents/VHDL/vhdl_processor/cpu_project/cpu_project.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="9387f5f0c1dd420aa386916f9002b826"/>
@ -60,7 +60,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="WTXSimLaunchSim" Val="337"/>
<Option Name="WTXSimLaunchSim" Val="348"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@ -188,14 +188,6 @@
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<File Path="$PSRCDIR/utils_1/imports/synth_1/data_memory.dcp">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedInSteps" Val="synth_1"/>
<Attr Name="AutoDcp" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
@ -223,7 +215,7 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="20">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/data_memory.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>

2
src/data_memory.vhd
View file

@ -20,7 +20,7 @@ begin
begin
if RST = '1' then
Memory <= (others => X"00"); -- Reset the memory to 0x00
elsif rising_edge(CLK) then
elsif falling_edge(CLK) then
if RW_ENABLE = '1' then -- Read
DATA_OUT <= Memory(to_integer(unsigned(ADDR)));
else -- Write