INSA/vhdl_processor
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FIXED MEMORY

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This commit is contained in:
Yohan Boujon 2023-11-21 15:50:59 +01:00
parent c42c0bcf22
commit 87b358b667
3 changed files with 8 additions and 28 deletions
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2
cpu_project/cpu_project.xpr
View file

@ -60,7 +60,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="WTXSimLaunchSim" Val="7"/>
<Option Name="WTXSimLaunchSim" Val="29"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>

18
src/cpu.vhd
View file

@ -5,13 +5,8 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cpu is
Port (
clk : in STD_LOGIC;
pc_out : out STD_LOGIC_VECTOR(7 downto 0);
op_out: out STD_LOGIC_VECTOR(3 DOWNTO 0);
a_out: out STD_LOGIC_VECTOR(7 DOWNTO 0);
b_out: out STD_LOGIC_VECTOR(7 DOWNTO 0);
c_out: out STD_LOGIC_VECTOR(7 DOWNTO 0)
);
clk : in STD_LOGIC
);
end cpu;
ARCHITECTURE cpu_arch OF cpu IS
@ -91,18 +86,11 @@ begin
step4_memre : pipeline_step PORT MAP(mem_A, mem_B, mem_C, mem_OP, clk, re_A, re_B, re_C, re_OP);
instruction_memory_inst : instruction PORT MAP(PC, inst , clk);
memory_register_inst : reg PORT MAP(empty_4, empty_4, re_A(3 downto 0), re_OP(0), re_B, '0', clk, empty_8, empty_8);
memory_register_inst : reg PORT MAP(empty_4, empty_4, re_A(3 downto 0), '1', re_B, '1', clk, empty_8, empty_8);
-- alu_inst : alu PORT MAP();
-- data_memory_inst : data_memory PORT MAP();
a_out <= re_A;
b_out <= re_B;
c_out <= re_C;
OP_out <= re_OP;
pc_out <= PC;
process(clk)
begin
if clk'event and clk='1' then

16
src/cpu_tb.vhd
View file

@ -8,12 +8,7 @@ end test_cpu;
architecture bench of test_cpu is
component cpu
Port (
clk : in STD_LOGIC;
pc_out : out STD_LOGIC_VECTOR(7 downto 0);
op_out : out STD_LOGIC_VECTOR(3 DOWNTO 0);
a_out : out STD_LOGIC_VECTOR(7 DOWNTO 0);
b_out : out STD_LOGIC_VECTOR(7 DOWNTO 0);
c_out : out STD_LOGIC_VECTOR(7 DOWNTO 0)
clk : in STD_LOGIC
);
end component;
@ -25,15 +20,12 @@ architecture bench of test_cpu is
begin
uut: cpu PORT MAP(
inClock,
int_PC,
int_re_OP,
int_re_A,
int_re_B,
int_re_C
inClock
);
-- Clock generation
inClock <= not inClock after 10 ns; -- Adjust clock period as necessary
end bench;