From 884ecdbded35b07408ecce40f772f6b069fafe26 Mon Sep 17 00:00:00 2001
From: Yohan Boujon <yo.boujon@gmail.com>
Date: Mon, 20 Nov 2023 12:02:40 +0100
Subject: [PATCH] AFC instruction done. Test Bench for CPU (AFC) done.

---
 cpu_project/cpu_project.xpr | 21 ++++++++-------
 src/cpu.vhd                 | 52 +++++++++++++++++++++++++++++--------
 src/cpu_tb.vhd              | 39 ++++++++++++++++++++++++++++
 src/instruction_memory.vhd  |  3 ++-
 4 files changed, 94 insertions(+), 21 deletions(-)
 create mode 100644 src/cpu_tb.vhd

diff --git a/cpu_project/cpu_project.xpr b/cpu_project/cpu_project.xpr
index c0e6921..35af264 100644
--- a/cpu_project/cpu_project.xpr
+++ b/cpu_project/cpu_project.xpr
@@ -60,7 +60,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTXSimLaunchSim" Val="7"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -142,9 +142,16 @@
       </Config>
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/../src/cpu_tb.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="cpu"/>
+        <Option Name="TopModule" Val="test_cpu"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TopAutoSet" Val="TRUE"/>
         <Option Name="TransportPathDelay" Val="0"/>
@@ -196,9 +203,7 @@
   <Runs Version="1" Minor="20">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/data_memory.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -206,11 +211,9 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
diff --git a/src/cpu.vhd b/src/cpu.vhd
index 0a694cb..7f67e10 100644
--- a/src/cpu.vhd
+++ b/src/cpu.vhd
@@ -6,7 +6,11 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
 entity cpu is
     Port (
         clk : in STD_LOGIC;
-        instruction_pointer : in STD_LOGIC_VECTOR(7 downto 0)
+        pc_out : out STD_LOGIC_VECTOR(7 downto 0);
+        op_out: out STD_LOGIC_VECTOR(3 DOWNTO 0);
+        a_out: out STD_LOGIC_VECTOR(7 DOWNTO 0);
+        b_out: out STD_LOGIC_VECTOR(7 DOWNTO 0);
+        c_out: out STD_LOGIC_VECTOR(7 DOWNTO 0)
     );
 end cpu;
 
@@ -45,12 +49,12 @@ ARCHITECTURE cpu_arch OF cpu IS
     
     COMPONENT data_memory IS
 	PORT (
-		CLK : IN STD_LOGIC;
-		RST : IN STD_LOGIC;
-		RW_ENABLE : IN STD_LOGIC;
-		ADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+		clk : IN STD_LOGIC;
+		rst : IN STD_LOGIC;
+		rw_enable : IN STD_LOGIC;
+		addr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
 	);
     END COMPONENT;
     
@@ -71,22 +75,48 @@ ARCHITECTURE cpu_arch OF cpu IS
     signal li_A, di_A, ex_A, mem_A, re_A  : STD_LOGIC_VECTOR(7 downto 0);
     signal li_B, di_B, ex_B, mem_B, re_B : STD_LOGIC_VECTOR(7 downto 0);
     signal li_C, di_C, ex_C, mem_C, re_C : STD_LOGIC_VECTOR(7 downto 0);
-    signal di_OP, ex_OP, mem_OP, re_OP : STD_LOGIC_VECTOR(3 downto 0);
-    signal li_OP : STD_LOGIC_VECTOR(31 downto 0);
+    signal li_OP, di_OP, ex_OP, mem_OP, re_OP : STD_LOGIC_VECTOR(3 downto 0);
+    signal inst : STD_LOGIC_VECTOR(31 downto 0);
+    --- internal component of cpu
+    signal PC : STD_LOGIC_VECTOR(7 downto 0) := X"00";
     ---signal main_clk : STD_LOGIC;
     
     signal empty_8 : STD_LOGIC_VECTOR(7 downto 0);
     signal empty_4 : STD_LOGIC_VECTOR(3 downto 0);
     
 begin
-    step1_lidi  : pipeline_step PORT MAP(li_A, li_B, li_C, li_OP(7 downto 4), clk, di_A, di_B, di_C, di_OP);
+    step1_lidi  : pipeline_step PORT MAP(li_A, li_B, li_C, inst(7 downto 4), clk, di_A, di_B, di_C, di_OP);
     step2_diex  : pipeline_step PORT MAP(di_A, di_B, di_C, di_OP, clk, ex_A, ex_B, ex_C, ex_OP);
     step3_exmem : pipeline_step PORT MAP(ex_A, ex_B, ex_C, ex_OP, clk, mem_A, mem_B, mem_C, mem_OP);
     step4_memre : pipeline_step PORT MAP(mem_A, mem_B, mem_C, mem_OP, clk, re_A, re_B, re_C, re_OP);
     
-    instruction_memory_inst : instruction PORT MAP(instruction_pointer, li_OP , clk);
+    instruction_memory_inst : instruction PORT MAP(PC, inst , clk);
     memory_register_inst    : reg PORT MAP(empty_4, empty_4, re_A(3 downto 0), re_OP(0), re_B, '0', clk, empty_8, empty_8);
+    
     -- alu_inst                : alu PORT MAP();
     -- data_memory_inst        : data_memory PORT MAP();
 
+    a_out <= re_A;
+    b_out <= re_B;
+    c_out <= re_C;
+    OP_out <= re_OP;
+    pc_out <= PC;
+    
+
+    process(clk)
+        begin
+            if clk'event and clk='1' then
+                li_OP <= inst(27 downto 24);
+                li_A <= inst(23 downto 16);
+                li_B <= inst(15 downto 8);
+                li_C <= inst(7 downto 0);
+                --case li_OP is
+                    -- AFC
+                    --when => X"06" =>
+
+                --end case
+                PC <= PC+'1';
+            end if;
+    end process;
+
 END cpu_arch;
\ No newline at end of file
diff --git a/src/cpu_tb.vhd b/src/cpu_tb.vhd
new file mode 100644
index 0000000..0679cba
--- /dev/null
+++ b/src/cpu_tb.vhd
@@ -0,0 +1,39 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity test_cpu is
+end test_cpu;
+
+architecture bench of test_cpu is
+    component cpu
+        Port (
+            clk : in STD_LOGIC;
+            pc_out : out STD_LOGIC_VECTOR(7 downto 0);
+            op_out : out STD_LOGIC_VECTOR(3 DOWNTO 0);
+            a_out : out STD_LOGIC_VECTOR(7 DOWNTO 0);
+            b_out : out STD_LOGIC_VECTOR(7 DOWNTO 0);
+            c_out : out STD_LOGIC_VECTOR(7 DOWNTO 0)
+        );
+    end component;
+
+    signal inClock : STD_LOGIC := '0';  
+    
+    -- Signals for monitoring internal states
+    signal int_PC, int_re_A, int_re_B, int_re_C : STD_LOGIC_VECTOR(7 downto 0);
+    signal int_re_OP : STD_LOGIC_VECTOR(3 downto 0);
+    
+begin
+    uut: cpu PORT MAP( 
+        inClock,
+        int_PC,
+        int_re_OP,
+        int_re_A,
+        int_re_B,
+        int_re_C
+    );
+
+    -- Clock generation
+    inClock <= not inClock after 10 ns; -- Adjust clock period as necessary
+
+end bench;
diff --git a/src/instruction_memory.vhd b/src/instruction_memory.vhd
index 1a0e6d8..31b21cf 100644
--- a/src/instruction_memory.vhd
+++ b/src/instruction_memory.vhd
@@ -21,8 +21,9 @@ entity instruction is
         --do something (e.g. read data from a file, perform some initialization calculation, ...)
         -- Exemple :
         for i in code_array'range loop
-            init_result(i) := std_logic_vector(conv_unsigned(i, 32));
+            init_result(i) := std_logic_vector(conv_unsigned(0, 32));
         end loop;
+        init_result(0) := X"06010C00";
         return init_result;
     end function init;
 end instruction;