From 909de11c18bde7ec12ea31c139939ac473ae0693 Mon Sep 17 00:00:00 2001
From: Lemonochrome <example>
Date: Tue, 28 Nov 2023 19:34:50 +0100
Subject: [PATCH] Fixed timing problems by re-organizing the pipeline

---
 cpu_project/cpu_project.xpr |   2 +-
 src/cpu.vhd                 | 137 +++++++++++++++++-------------------
 src/data_memory.vhd         |   2 +-
 src/instruction_memory.vhd  |  12 ++--
 src/pipeline_step.vhd       |  31 --------
 src/register.vhd            |  59 +++++++---------
 6 files changed, 96 insertions(+), 147 deletions(-)
 delete mode 100644 src/pipeline_step.vhd

diff --git a/cpu_project/cpu_project.xpr b/cpu_project/cpu_project.xpr
index e4b2453..6d8ef2e 100644
--- a/cpu_project/cpu_project.xpr
+++ b/cpu_project/cpu_project.xpr
@@ -60,7 +60,7 @@
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
     <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
-    <Option Name="WTXSimLaunchSim" Val="306"/>
+    <Option Name="WTXSimLaunchSim" Val="501"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
diff --git a/src/cpu.vhd b/src/cpu.vhd
index 786c87f..466257e 100644
--- a/src/cpu.vhd
+++ b/src/cpu.vhd
@@ -58,51 +58,56 @@ ARCHITECTURE cpu_arch OF cpu IS
     END COMPONENT;
 
     -- Signaux internes
-    signal PC : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; -- Program Counter
+    signal PC : STD_LOGIC_VECTOR (7 downto 0)  := "00000000"; -- Program Counter
     signal IR : STD_LOGIC_VECTOR (31 downto 0); -- Instruction Register
-    signal OP : STD_LOGIC_VECTOR (7 downto 0);
-    signal A : STD_LOGIC_VECTOR (7 downto 0);
-    signal B : STD_LOGIC_VECTOR (7 downto 0);
-    signal C : STD_LOGIC_VECTOR (7 downto 0);
 
-    signal OP_DI : STD_LOGIC_VECTOR (7 downto 0);
-    signal A_DI  : STD_LOGIC_VECTOR (7 downto 0); 
-    signal B_DI  : STD_LOGIC_VECTOR (7 downto 0);
-    signal C_DI  : STD_LOGIC_VECTOR (7 downto 0);
-    
-    signal OP_EX : STD_LOGIC_VECTOR (7 downto 0);
-    signal A_EX  : STD_LOGIC_VECTOR (7 downto 0);
-    signal B_EX  : STD_LOGIC_VECTOR (7 downto 0);
-    signal C_EX  : STD_LOGIC_VECTOR (7 downto 0);
+    signal OP_LI_DI : STD_LOGIC_VECTOR (7 downto 0);
+    signal A_LI_DI  : STD_LOGIC_VECTOR (7 downto 0);
+    signal B_LI_DI  : STD_LOGIC_VECTOR (7 downto 0);
+    signal C_LI_DI  : STD_LOGIC_VECTOR (7 downto 0);
 
-    signal OP_MEM: STD_LOGIC_VECTOR (7 downto 0);
-    signal A_MEM : STD_LOGIC_VECTOR (7 downto 0);
-    signal B_MEM : STD_LOGIC_VECTOR (7 downto 0);
-    signal C_MEM : STD_LOGIC_VECTOR (7 downto 0);
+    signal OP_DI_EX : STD_LOGIC_VECTOR (7 downto 0);
+    signal A_DI_EX : STD_LOGIC_VECTOR (7 downto 0);
+    signal B_DI_EX  : STD_LOGIC_VECTOR (7 downto 0);
+    signal C_DI_EX  : STD_LOGIC_VECTOR (7 downto 0);
 
-    signal OP_RE : STD_LOGIC_VECTOR (7 downto 0);
-    signal A_RE  : STD_LOGIC_VECTOR (7 downto 0);
-    signal B_RE  : STD_LOGIC_VECTOR (7 downto 0);
-    signal C_RE  : STD_LOGIC_VECTOR (7 downto 0);
+    signal OP_EX_MEM : STD_LOGIC_VECTOR (7 downto 0);
+    signal A_EX_MEM  : STD_LOGIC_VECTOR (7 downto 0);
+    signal B_EX_MEM  : STD_LOGIC_VECTOR (7 downto 0);
+    signal C_EX_MEM  : STD_LOGIC_VECTOR (7 downto 0);
 
-    signal W_ADDRESS_HANDLE : STD_LOGIC_VECTOR(3 DOWNTO 0);
-    signal W_DATA_HANDLE    : STD_LOGIC_VECTOR(7 DOWNTO 0);
-    signal W_ENABLE_HANDLE  : STD_LOGIC;
+    signal OP_MEM_RE: STD_LOGIC_VECTOR (7 downto 0);
+    signal A_MEM_RE : STD_LOGIC_VECTOR (7 downto 0);
+    signal B_MEM_RE : STD_LOGIC_VECTOR (7 downto 0);
+    signal C_MEM_RE : STD_LOGIC_VECTOR (7 downto 0);
+
+
+
+
+    -- Register file specific signals
+    signal R_ADDRESS_A_HANDLE : STD_LOGIC_VECTOR(3 DOWNTO 0);
+    signal R_ADDRESS_B_HANDLE : STD_LOGIC_VECTOR(3 DOWNTO 0);
+    signal W_ADDRESS_HANDLE   : STD_LOGIC_VECTOR(3 DOWNTO 0);
+    signal W_DATA_HANDLE      : STD_LOGIC_VECTOR(7 DOWNTO 0);
+    signal W_ENABLE_HANDLE    : STD_LOGIC;
+    signal A_DATA_OUT_HANDLE  : STD_LOGIC_VECTOR(7 DOWNTO 0);
+    signal B_DATA_OUT_HANDLE  : STD_LOGIC_VECTOR(7 DOWNTO 0);
 
 BEGIN
    -- Instantiation des composants
    RegisterFile_Instance: reg PORT MAP (
-    address_A => "0000",
-    address_B => "0000",
+    address_A => R_ADDRESS_A_HANDLE,
+    address_B => R_ADDRESS_B_HANDLE,
     address_W => W_ADDRESS_HANDLE,
     W_Enable  => W_ENABLE_HANDLE,
     W_Data    => W_DATA_HANDLE,
-    reset     => '1',
+    reset     => '1', -- Reset unactive
     clk       => clk,
-    A_Data    => open,
-    B_Data    => open
+    A_Data    => A_DATA_OUT_HANDLE,
+    B_Data    => B_DATA_OUT_HANDLE
     );
 
+
     InstructionMemory_Instance: instruction PORT MAP (
 		instruction => PC,
         code        => IR,
@@ -110,83 +115,69 @@ BEGIN
     );
 
 
-
     -- Pipeline
-
-    -- Lecture Instruction (LI)
-    LI: process(clk)
-    begin
-        if rising_edge(clk) then
-            -- Charger les instruction
-            OP <= IR(31 downto 24);
-            A  <= IR(23 downto 16);
-            B  <= IR(15 downto 8);
-            C  <= IR(7 downto 0);
-        end if;
-    end process;
-
-    DI: process(clk)
+    OP_LI_DI <= IR(31 downto 24);
+    A_LI_DI  <= IR(23 downto 16);
+    B_LI_DI  <= IR(15 downto 8);
+    C_LI_DI  <= IR(7 downto 0);
+    LI_DI: process(clk)
     begin
         if rising_edge(clk) then
             -- Banc de registre
-            OP_DI <= OP;
-            case OP is
-                when X"06" =>
-                    A_DI <= A;
-                    B_DI <= B;
-                    C_DI <= C;
+            case OP_LI_DI is
+                when X"06" => -- AFC
+                    OP_DI_EX <= OP_LI_DI;
+                    A_DI_EX  <= A_LI_DI; 
+                    B_DI_EX  <= B_LI_DI;  
+                    C_DI_EX  <= C_LI_DI; 
                 when others =>
                     null;
             end case;
         end if;
     end process;
 
-    EX: process(clk)
+    DI_EX: process(clk)
     begin
         if rising_edge(clk) then
             -- Executer instruction si nécéssaire (ALU)
-            OP_EX <= OP_DI;
-            case OP_DI is
+            case OP_DI_EX is
                 when X"06" =>
-                    A_EX <= A_DI;
-                    B_EX <= B_DI;
-                    C_EX <= C_DI;
+                    OP_EX_MEM <= OP_DI_EX;
+                    A_EX_MEM  <= A_DI_EX; 
+                    B_EX_MEM  <= B_DI_EX;  
+                    C_EX_MEM  <= C_DI_EX; 
                 when others =>
                     null;
             end case;
         end if;
     end process;
 
-    MEM: process(clk)
+    EX_MEM: process(clk)
     begin
         if rising_edge(clk) then
             -- Ecrire ou lire memoire des données
-            OP_MEM <= OP_EX;
-            case OP_EX is
+            case OP_EX_MEM is
                 when X"06" =>
-                    A_MEM <= A_EX;
-                    B_MEM <= B_EX;
-                    C_MEM <= C_EX;
+                    OP_MEM_RE <= OP_EX_MEM;
+                    A_MEM_RE  <= A_EX_MEM; 
+                    B_MEM_RE  <= B_EX_MEM;  
+                    C_MEM_RE  <= C_EX_MEM;  
                 when others =>
                     null;
             end case;
         end if;
     end process;
 
-    RE: process(clk)
+    -- Write Back (RE)
+    MEM_RE: process(clk)
     begin
-        if rising_edge(clk) then
+        if rising_edge(clk) then          
             -- Ecrire dans les registres
-            OP_RE <= OP_MEM;
-            case OP_MEM is
+            case OP_MEM_RE is -- Si OP_RE : b c Si OP_MEM : a b
                 when X"06" =>
-                    A_RE <= A_MEM;
-                    B_RE <= B_MEM;
-                    C_RE <= C_MEM;
-
                     W_ENABLE_HANDLE  <= '1';
-                    W_ADDRESS_HANDLE <= A_RE(3 downto 0);
-                    W_DATA_HANDLE    <= B_RE;
+                    W_ADDRESS_HANDLE <= A_MEM_RE(3 downto 0);
+                    W_DATA_HANDLE    <= B_MEM_RE;
                 when others =>
                     null;
             end case;
diff --git a/src/data_memory.vhd b/src/data_memory.vhd
index 6d890ce..26fabaf 100644
--- a/src/data_memory.vhd
+++ b/src/data_memory.vhd
@@ -16,7 +16,7 @@ architecture Behavioral of data_memory is
     type MemoryArray is array (0 to 255) of STD_LOGIC_VECTOR(7 downto 0);
     signal Memory : MemoryArray := (others => X"00");
 begin
-    process(CLK, RST)
+    process(CLK)
     begin
         if RST = '1' then
             Memory <= (others => X"00");  -- Reset the memory to 0x00
diff --git a/src/instruction_memory.vhd b/src/instruction_memory.vhd
index 3b568cc..be71061 100644
--- a/src/instruction_memory.vhd
+++ b/src/instruction_memory.vhd
@@ -25,10 +25,10 @@ entity instruction is
         end loop;
         init_result(0) := X"06000A0F";
         init_result(1) := X"06010B0F";
-        init_result(2) := X"06020C0F";
-        init_result(3) := X"06030D0F";
-        init_result(4) := X"06040E0F";
-        init_result(5) := X"06050F0F";
+        init_result(2) := X"06020B0F";
+
+        
+        -- init_result(6) := X"0502010F";
         return init_result;
     end function init;
 end instruction;
@@ -37,9 +37,9 @@ architecture behavior_instr of instruction is
     -- Memory variable
     signal code_memory: code_array := init;
 begin
-    process(instruction, clk) is
+    process(clk) is
     begin
-        if clk'event AND clk = '1' then
+        if rising_edge(clk) then
             code <= code_memory(CONV_INTEGER(UNSIGNED(instruction)));
         end if;
     end process;
diff --git a/src/pipeline_step.vhd b/src/pipeline_step.vhd
deleted file mode 100644
index fe8e3d6..0000000
--- a/src/pipeline_step.vhd
+++ /dev/null
@@ -1,31 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-entity pipeline_step is
-port(
-  A_in:    in  STD_LOGIC_VECTOR(7 downto 0);
-  B_in:    in  STD_LOGIC_VECTOR(7 downto 0);
-  C_in:    in  STD_LOGIC_VECTOR(7 downto 0);
-  OP_in:   in  STD_LOGIC_VECTOR(3 downto 0);
-  clk : in STD_LOGIC;
-  A_out:    out  STD_LOGIC_VECTOR(7 downto 0);
-  B_out:    out  STD_LOGIC_VECTOR(7 downto 0);
-  C_out:    out  STD_LOGIC_VECTOR(7 downto 0);
-  OP_out:   out  STD_LOGIC_VECTOR(3 downto 0)
-);
-end pipeline_step;
-
-architecture behavior_pipeline_step of pipeline_step is
-begin
-    process(clk, A_in, B_in, C_in, OP_in)
-        begin
-            if clk'event and clk='1' then
-                A_out <= A_in;
-                B_out <= B_in;
-                C_out <= C_in;
-                OP_out <= OP_in;
-            end if;
-    end process;
-end behavior_pipeline_step;
\ No newline at end of file
diff --git a/src/register.vhd b/src/register.vhd
index 6a8cf54..1cf41a3 100644
--- a/src/register.vhd
+++ b/src/register.vhd
@@ -1,52 +1,41 @@
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.ALL;
 
 entity reg is
 port(
-  address_A:    in  STD_LOGIC_VECTOR(3 downto 0);
-  address_B:    in  STD_LOGIC_VECTOR(3 downto 0);
-  address_W:    in  STD_LOGIC_VECTOR(3 downto 0);
-  W_Enable:     in  STD_LOGIC;
-  W_Data:       in  STD_LOGIC_VECTOR(7 downto 0);
-  reset:        in  STD_LOGIC;
-  clk:          in  STD_LOGIC;
-  A_Data:       out STD_LOGIC_VECTOR(7 downto 0);
-  B_Data:       out STD_LOGIC_VECTOR(7 downto 0)
+    address_A:    in  STD_LOGIC_VECTOR(3 downto 0);
+    address_B:    in  STD_LOGIC_VECTOR(3 downto 0);
+    address_W:    in  STD_LOGIC_VECTOR(3 downto 0);
+    W_Enable:     in  STD_LOGIC;
+    W_Data:       in  STD_LOGIC_VECTOR(7 downto 0);
+    reset:        in  STD_LOGIC;
+    clk:          in  STD_LOGIC;
+    A_Data:       out STD_LOGIC_VECTOR(7 downto 0);
+    B_Data:       out STD_LOGIC_VECTOR(7 downto 0)
 );
 end reg;
 
 architecture behavior_reg of reg is
-    -- Array of STD_LOGIC_VECTOR
-    type memory_array is array(0 to 15) of
-        STD_LOGIC_VECTOR(7 downto 0);
-    -- Memory variable
+    type memory_array is array(0 to 15) of STD_LOGIC_VECTOR(7 downto 0);
     signal memory: memory_array;
 begin
-    
-    -- Convert address_A and address_B to integers
-    -- Using Bypass to avoid delay between Read Data and Write Data if they are at the same time called (WEnable = 1)
-    A_Data <= memory(CONV_INTEGER(unsigned(address_A))) when (W_Enable = '0' or address_A /= address_W)
+
+    -- bypass
+    A_Data <= memory(to_integer(unsigned(address_A))) when (W_Enable = '0' or address_A /= address_W)
         else W_Data;
-    
-    B_Data <= memory(CONV_INTEGER(unsigned(address_B))) when (W_Enable = '0' or address_B /= address_W)
+
+    B_Data <= memory(to_integer(unsigned(address_B))) when (W_Enable = '0' or address_B /= address_W)
         else W_Data;
-    
-    -- Write data synchronously
-    process(address_W, W_Enable, W_Data, reset, clk) is
+
+    process(clk)
     begin
-        -- Reset the memory if shutdown
-        if reset = '0' then
-            memory <= (others => "00000000");
-        end if;
-        -- Else Doing writing routine at each clock tick
-        if reset = '1' then
-            if clk'event and clk='1' then
-                if W_Enable = '1' then
-                    memory(CONV_INTEGER(unsigned(address_W))) <= W_Data;
-                end if;
+        if rising_edge(clk) then
+            if reset = '0' then
+                memory <= (others => (others => '0'));
+            elsif W_Enable = '1' then
+                memory(to_integer(unsigned(address_W))) <= W_Data;
             end if;
         end if;
     end process;
-end behavior_reg;
\ No newline at end of file
+end behavior_reg;