Data flow done.

cpu_project/cpu_project.xpr

@@ -60,7 +60,7 @@
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
     <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
-    <Option Name="WTXSimLaunchSim" Val="219"/>
+    <Option Name="WTXSimLaunchSim" Val="285"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -91,6 +91,12 @@
   <FileSets Version="1" Minor="32">
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
       <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/../src/instruction_memory.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PPRDIR/../src/register.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -110,13 +116,6 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PPRDIR/../src/instruction_memory.vhd">
-        <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
       <File Path="$PPRDIR/../src/data_memory.vhd">
         <FileInfo>
           <Attr Name="AutoDisabled" Val="1"/>

src/cpu.vhd

@@ -60,10 +60,31 @@ ARCHITECTURE cpu_arch OF cpu IS
     -- Signaux internes
     signal PC : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; -- Program Counter
     signal IR : STD_LOGIC_VECTOR (31 downto 0); -- Instruction Register
+    signal OP : STD_LOGIC_VECTOR (7 downto 0);
     signal A : STD_LOGIC_VECTOR (7 downto 0);
     signal B : STD_LOGIC_VECTOR (7 downto 0);
     signal C : STD_LOGIC_VECTOR (7 downto 0);
 
+    signal OP_DI : STD_LOGIC_VECTOR (7 downto 0);
+    signal A_DI  : STD_LOGIC_VECTOR (7 downto 0); 
+    signal B_DI  : STD_LOGIC_VECTOR (7 downto 0);
+    signal C_DI  : STD_LOGIC_VECTOR (7 downto 0);
+    
+    signal OP_EX : STD_LOGIC_VECTOR (7 downto 0);
+    signal A_EX  : STD_LOGIC_VECTOR (7 downto 0);
+    signal B_EX  : STD_LOGIC_VECTOR (7 downto 0);
+    signal C_EX  : STD_LOGIC_VECTOR (7 downto 0);
+
+    signal OP_MEM: STD_LOGIC_VECTOR (7 downto 0);
+    signal A_MEM : STD_LOGIC_VECTOR (7 downto 0);
+    signal B_MEM : STD_LOGIC_VECTOR (7 downto 0);
+    signal C_MEM : STD_LOGIC_VECTOR (7 downto 0);
+
+    signal OP_RE : STD_LOGIC_VECTOR (7 downto 0);
+    signal A_RE  : STD_LOGIC_VECTOR (7 downto 0);
+    signal B_RE  : STD_LOGIC_VECTOR (7 downto 0);
+    signal C_RE  : STD_LOGIC_VECTOR (7 downto 0);
+
     
 BEGIN
    -- Instantiation des composants
@@ -79,6 +100,12 @@ BEGIN
     B_Data    => open
     );
 
+    InstructionMemory_Instance: instruction PORT MAP (
+		instruction => PC,
+        code        => IR,
+        clk         => clk
+    );
+
 
 
     -- Pipeline
@@ -88,20 +115,42 @@ BEGIN
     begin
         if rising_edge(clk) then
             -- Charger les instruction
+            OP <= IR(31 downto 24);
+            A  <= IR(23 downto 16);
+            B  <= IR(15 downto 8);
+            C  <= IR(7 downto 0);
         end if;
     end process;
 
     DI: process(clk)
     begin
         if rising_edge(clk) then
-            -- Decoder IR et init A B C
+            -- Banc de registre
+            OP_DI <= OP;
+            case OP is
+                when X"06" =>
+                    A_DI <= A;
+                    B_DI <= B;
+                    C_DI <= C;
+                when others =>
+                    null;
+            end case;
         end if;
     end process;
 
     EX: process(clk)
     begin
         if rising_edge(clk) then
-            -- Executer instruction si nécéssaire
+            -- Executer instruction si nécéssaire (ALU)
+            OP_EX <= OP_DI;
+            case OP_DI is
+                when X"06" =>
+                    A_EX <= A_DI;
+                    B_EX <= B_DI;
+                    C_EX <= C_DI;
+                when others =>
+                    null;
+            end case;
         end if;
     end process;
 
@@ -109,6 +158,15 @@ BEGIN
     begin
         if rising_edge(clk) then
             -- Ecrire ou lire memoire des données
+            OP_MEM <= OP_EX;
+            case OP_EX is
+                when X"06" =>
+                    A_MEM <= A_EX;
+                    B_MEM <= B_EX;
+                    C_MEM <= C_EX;
+                when others =>
+                    null;
+            end case;
         end if;
     end process;
 
@@ -116,6 +174,15 @@ BEGIN
     begin
         if rising_edge(clk) then
             -- Ecrire dans les registres
+            OP_RE <= OP_MEM;
+            case OP_MEM is
+                when X"06" =>
+                    A_RE <= A_MEM;
+                    B_RE <= B_MEM;
+                    C_RE <= C_MEM;
+                when others =>
+                    null;
+            end case;
         end if;
     end process;
 

src/instruction_memory.vhd

@@ -23,8 +23,9 @@ entity instruction is
         for i in code_array'range loop
             init_result(i) := std_logic_vector(conv_unsigned(0, 32));
         end loop;
-        init_result(0) := X"06010A00"; -- AFC 0x0a to R01
+        init_result(0) := X"060A0B0C";
-        init_result(1) := X"06020B00"; -- AFC 0x0b to R02
+        init_result(1) := X"060F0F0F";
+        init_result(2) := X"060A0B0C";
         return init_result;
     end function init;
 end instruction;