From a14fe3226153f7cff96399a507687fdf663e7d54 Mon Sep 17 00:00:00 2001
From: Robin Marin--Muller <80280962+Lemonochrme@users.noreply.github.com>
Date: Thu, 2 Jan 2025 22:51:14 +0100
Subject: [PATCH] Update README.md

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 README.md | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

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 # Risc V VHDL 5 Stages Pipeline
 
 ![image (3)](https://github.com/user-attachments/assets/323dff06-e9e8-466a-80a0-488c203bee9c)
+
+
+**Key Improvements in Develop Branch:**
+- Better understanding of VHDL allowed for a more efficient design.
+- The removal of redundant pipeline stage components streamlined the microprocessor, reducing bottlenecks and increasing operational frequency.
+
+
+1. **Main Branch:**
+   - Frequency: 68.19 MHz
+   - Design philosophy:
+     - Relied on components for pipeline stages.
+     - These components added complexity and increased the number of logical gates required, leading to slower processing.
+
+2. **Develop Branch:**
+   - Frequency: 168.55 MHz
+   - Design philosophy:
+     - Simplified architecture by eliminating unnecessary pipeline stage components.
+     - Optimized signal paths and reduced the number of logical gate transitions, leading to higher efficiency and speed.
+