Added pipeline, added cpu declarations.

cpu_project/cpu_project.xpr

@@ -99,28 +99,37 @@
       </File>
       <File Path="$PPRDIR/../src/data_memory.vhd">
         <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
       <File Path="$PPRDIR/../src/instruction_memory.vhd">
         <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/pipeline_step.vhd">
+        <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
       <File Path="$PPRDIR/../src/register.vhd">
         <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/cpu.vhd">
+        <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="alu"/>
+        <Option Name="TopModule" Val="cpu"/>
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
     </FileSet>
@@ -133,7 +142,7 @@
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="alu"/>
+        <Option Name="TopModule" Val="cpu"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TopAutoSet" Val="TRUE"/>
         <Option Name="TransportPathDelay" Val="0"/>
@@ -175,13 +184,14 @@
     </Simulator>
   </Simulators>
   <Runs Version="1" Minor="20">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
       <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>

src/cpu.vhd

@@ -0,0 +1,79 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity cpu is
+end cpu;
+
+ARCHITECTURE cpu_arch OF cpu IS
+	COMPONENT instruction IS
+		PORT (
+			instruction : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+			code : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			clk : IN STD_LOGIC
+		);
+	END COMPONENT;
+
+    COMPONENT reg IS
+	PORT (
+		address_A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		address_B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		address_W : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		W_Enable : IN STD_LOGIC;
+		W_Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		reset : IN STD_LOGIC;
+		clk : IN STD_LOGIC;
+		A_Data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		B_Data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+    END COMPONENT;
+
+    COMPONENT alu IS
+	PORT (
+		a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		b : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		op : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		s : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		flags : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+    END COMPONENT;
+    
+    COMPONENT data_memory IS
+	PORT (
+		CLK : IN STD_LOGIC;
+		RST : IN STD_LOGIC;
+		RW_ENABLE : IN STD_LOGIC;
+		ADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+    END COMPONENT;
+    
+    COMPONENT pipeline_step IS
+    PORT ( 
+      A_in:    in  STD_LOGIC_VECTOR(7 downto 0);
+      B_in:    in  STD_LOGIC_VECTOR(7 downto 0);
+      C_in:    in  STD_LOGIC_VECTOR(7 downto 0);
+      OP_in:   in  STD_LOGIC_VECTOR(3 downto 0);
+      clk : in STD_LOGIC;
+      A_out:    out  STD_LOGIC_VECTOR(7 downto 0);
+      B_out:    out  STD_LOGIC_VECTOR(7 downto 0);
+      C_out:    out  STD_LOGIC_VECTOR(7 downto 0);
+      OP_out:   out  STD_LOGIC_VECTOR(3 downto 0)
+    );
+    END COMPONENT;
+
+	---FOR ALL : instruction USE ENTITY work.instruction;
+begin
+    step1_lidi  : pipeline_step PORT MAP();
+    step2_diex  : pipeline_step PORT MAP();
+    step3_exmem : pipeline_step PORT MAP();
+    step4_memre : pipeline_step PORT MAP();
+    
+    instruction_memory_inst : instruction PORT MAP();
+    memory_register_inst    : reg PORT MAP();
+    alu_inst                : alu PORT_MAP();
+    data_memory_inst        : data_memory PORT MAP();
+
+END cpu_arch;

src/pipeline_step.vhd

@@ -0,0 +1,31 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity pipeline_step is
+port(
+  A_in:    in  STD_LOGIC_VECTOR(7 downto 0);
+  B_in:    in  STD_LOGIC_VECTOR(7 downto 0);
+  C_in:    in  STD_LOGIC_VECTOR(7 downto 0);
+  OP_in:   in  STD_LOGIC_VECTOR(3 downto 0);
+  clk : in STD_LOGIC;
+  A_out:    out  STD_LOGIC_VECTOR(7 downto 0);
+  B_out:    out  STD_LOGIC_VECTOR(7 downto 0);
+  C_out:    out  STD_LOGIC_VECTOR(7 downto 0);
+  OP_out:   out  STD_LOGIC_VECTOR(3 downto 0)
+);
+end pipeline_step;
+
+architecture behavior_pipeline_step of pipeline_step is
+begin
+    process(clk, A_in, B_in, C_in, OP_in)
+        begin
+            if clk'event and clk='1' then
+                A_out <= A_in;
+                A_out <= B_in;
+                A_out <= C_in;
+                A_out <= OP_in;
+            end if;
+    end process;
+end behavior_pipeline_step;