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Commented component for clarity

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Lemonochrome 2023-11-26 16:23:26 +01:00
parent 4c1983c39d
commit c251bc227b
3 changed files with 92 additions and 216 deletions
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118
cpu_project/cpu_project.xpr
View file

@ -1,10 +1,10 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.1 (64-bit) -->
<!-- Product Version: Vivado v2023.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="63" Path="/home/boujon/Documents/VHDL/vhdl_processor/cpu_project/cpu_project.xpr">
<Project Product="Vivado" Version="7" Minor="65" Path="C:/Users/robin/Documents/Dev/vhdl_processor/cpu_project/cpu_project.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="9387f5f0c1dd420aa386916f9002b826"/>
@ -29,13 +29,13 @@
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2023.1"/>
<Option Name="SimulatorVersionModelSim" Val="2022.3"/>
<Option Name="SimulatorVersionQuesta" Val="2022.3"/>
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
<Option Name="SimulatorVersionXcelium" Val="22.09.001"/>
<Option Name="SimulatorVersionVCS" Val="T-2022.06-SP1"/>
<Option Name="SimulatorVersionRiviera" Val="2022.04"/>
<Option Name="SimulatorVersionActiveHdl" Val="13.1"/>
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
@ -43,8 +43,7 @@
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2023.1/xhub/board_store/xilinx_board_store"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
@ -60,7 +59,8 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="WTXSimLaunchSim" Val="153"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="175"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@ -88,65 +88,74 @@
<Option Name="ClassicSocBoot" Val="FALSE"/>
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSets Version="1" Minor="32">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../src/cpu.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/alu.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/data_memory.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/instruction_memory.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/mux/mux_bdr.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/mux/mux_mem_ldr.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/mux/mux_mem_str.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/mux/mux_ual.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/pipeline_step.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/register.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/cpu.vhd">
<File Path="$PPRDIR/../src/mux/mux_bdr.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/mux/mux_mem_ldr.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/mux/mux_mem_str.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/mux/mux_ual.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/pipeline_step.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
@ -188,14 +197,6 @@
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<File Path="$PSRCDIR/utils_1/imports/synth_1/data_memory.dcp">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedInSteps" Val="synth_1"/>
<Attr Name="AutoDcp" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
@ -212,18 +213,15 @@
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="20">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/data_memory.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
@ -251,9 +249,7 @@
<RQSFiles/>
</Run>
</Runs>
<Board>
<Jumpers/>
</Board>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">

181
src/cpu.vhd
View file

@ -10,166 +10,55 @@ entity cpu is
end cpu;
ARCHITECTURE cpu_arch OF cpu IS
-- Multiplexers
COMPONENT mux_ual IS
PORT (
mux_op: IN STD_LOGIC_VECTOR(3 downto 0);
mux_b_in: IN STD_LOGIC_VECTOR(7 downto 0);
mux_alu_s_in: IN STD_LOGIC_VECTOR(7 downto 0);
mux_sortie: OUT STD_LOGIC_VECTOR(7 downto 0)
);
END COMPONENT;
COMPONENT mux_bdr IS
PORT (
mux_op: IN STD_LOGIC_VECTOR(3 downto 0);
mux_b_in: IN STD_LOGIC_VECTOR(7 downto 0);
mux_qa_in: IN STD_LOGIC_VECTOR(7 downto 0);
mux_sortie: OUT STD_LOGIC_VECTOR(7 downto 0)
);
END COMPONENT;
COMPONENT mux_mem_str IS
PORT (
mux_op: IN STD_LOGIC_VECTOR(3 downto 0);
mux_b_in: IN STD_LOGIC_VECTOR(7 downto 0);
mux_mem_out_in: IN STD_LOGIC_VECTOR(7 downto 0);
mux_sortie: OUT STD_LOGIC_VECTOR(7 downto 0)
);
END COMPONENT;
COMPONENT mux_mem_ldr IS
PORT (
mux_op: IN STD_LOGIC_VECTOR(3 downto 0);
mux_a_in: IN STD_LOGIC_VECTOR(7 downto 0);
mux_b_in: IN STD_LOGIC_VECTOR(7 downto 0);
mux_sortie: OUT STD_LOGIC_VECTOR(7 downto 0)
);
END COMPONENT;
-- Logical components and memory
-- Code memory
COMPONENT instruction IS
PORT (
instruction : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
code : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instruction : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Adresse de l'instruction
code : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- Code de l'instruction
clk : IN STD_LOGIC
);
END COMPONENT;
COMPONENT reg IS
PORT (
address_A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
address_B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
address_W : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
W_Enable : IN STD_LOGIC;
W_Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
A_Data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
B_Data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
COMPONENT alu IS
PORT (
a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
op : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
flags : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
-- Data memory
COMPONENT data_memory IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
rw_enable : IN STD_LOGIC;
addr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
rst : IN STD_LOGIC; -- Reset actif à '1'
rw_enable : IN STD_LOGIC; -- Lecture: '1' Ecriture: '0'
addr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Adresse de la zone mémoire
data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Data écrite à l'adresse addr
data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) -- Data présente à l'adresse addr
);
END COMPONENT;
-- Register file
COMPONENT reg IS
PORT (
address_A : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Permet de lire le registre à l'address_A sortie sur A_Data
address_B : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Permet de lire le registre à l'address_B sortie sur B_Data
address_W : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Permet d'écrire les données de W_Data à l'adresse address_W
W_Enable : IN STD_LOGIC; -- Si W_Enable='1' alors écriture
W_Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Données à écrire
reset : IN STD_LOGIC; -- Reset actif à '0'
clk : IN STD_LOGIC;
A_Data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Sortie des données présentes à l'address_A
B_Data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) -- Sortie des données présentes à l'address_B
);
END COMPONENT;
-- Arithmentic Logic Unit
COMPONENT alu IS
PORT (
a : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Opérande a
b : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Opérande b
op : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- Code de l'operation
s : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Sortie de l'operation
flags : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) -- Flags de l'ALU (C, N, Z, O)
);
END COMPONENT;
COMPONENT pipeline_step IS
PORT (
A_in: in STD_LOGIC_VECTOR(7 downto 0);
B_in: in STD_LOGIC_VECTOR(7 downto 0);
C_in: in STD_LOGIC_VECTOR(7 downto 0);
OP_in: in STD_LOGIC_VECTOR(3 downto 0);
clk: in STD_LOGIC;
A_out: out STD_LOGIC_VECTOR(7 downto 0);
B_out: out STD_LOGIC_VECTOR(7 downto 0);
C_out: out STD_LOGIC_VECTOR(7 downto 0);
OP_out: out STD_LOGIC_VECTOR(3 downto 0)
);
END COMPONENT;
-- Banc de registres
signal di_A, di_B_in, di_B_out, di_C_in, di_C_out, qA : STD_LOGIC_VECTOR(7 downto 0);
signal di_OP : STD_LOGIC_VECTOR(3 downto 0);
signal write_enable : STD_LOGIC;
-- UAL
signal ex_A, ex_B_out, ex_B_in, ex_C, S_ALU : STD_LOGIC_VECTOR(7 downto 0);
signal ex_OP : STD_LOGIC_VECTOR(3 downto 0);
signal OP_ALU : STD_LOGIC_VECTOR(2 downto 0);
-- Memoire des donnees
signal mem_A, mem_B_in, mem_B_out, mem_C, mem_address, mem_data : STD_LOGIC_VECTOR(7 downto 0);
signal mem_OP: STD_LOGIC_VECTOR(3 downto 0);
signal RW_MEM: STD_LOGIC;
-- Step 4
signal re_A, re_B, re_C : STD_LOGIC_VECTOR(7 downto 0);
signal re_OP : STD_LOGIC_VECTOR(3 downto 0);
signal W_enable: STD_LOGIC;
--- internal component of cpu
signal inst : STD_LOGIC_VECTOR(31 downto 0);
signal PC : STD_LOGIC_VECTOR(7 downto 0) := X"00";
signal empty_8 : STD_LOGIC_VECTOR(7 downto 0);
signal empty_4 : STD_LOGIC_VECTOR(3 downto 0);
begin
instruction_memory_inst : instruction PORT MAP(PC, inst , clk);
-- step1 pipeline
step1_lidi : pipeline_step PORT MAP(inst(23 downto 16), inst(15 downto 8), inst(7 downto 0), inst(27 downto 24), clk, di_A, di_B_out, di_C_out, di_OP);
memory_register_inst : reg PORT MAP(di_B_out(3 downto 0), di_C_out(3 downto 0), re_A(3 downto 0), W_enable, re_B, '1', clk, qA, di_C_in);
mux_bdr_inst : mux_bdr PORT MAP(di_OP,di_B_out,qA,di_B_in);
-- step2 pipeline
step2_diex : pipeline_step PORT MAP(di_A, di_B_in, di_C_in, di_OP, clk, ex_A, ex_B_out, ex_C, ex_OP);
-- LC step 2
with ex_OP select
OP_ALU <= "000" when X"1",
"110" when X"2",
"001" when X"3",
"111" when others;
alu_inst : alu PORT MAP(ex_B_out, ex_C, OP_ALU, S_ALU);
mux_ual_inst : mux_ual PORT MAP(ex_OP,ex_B_out,S_ALU,ex_B_in);
-- rest for now
step3_exmem : pipeline_step PORT MAP(ex_A, ex_B_in, ex_C, ex_OP, clk, mem_A, mem_B_in, mem_C, mem_OP);
mux_mem_ldr_inst : mux_mem_ldr PORT MAP(mem_OP, mem_A, mem_B_in, mem_address);
with mem_OP select
RW_MEM <= '0' when X"8",
'1' when others;
data_memory_inst : data_memory PORT MAP(clk, '0', RW_MEM, mem_address, mem_B_in, mem_data);
mux_mem_str_inst : mux_mem_str PORT MAP(mem_OP, mem_B_in, mem_data, mem_B_out);
-- Penser à changer comment le write fonctionne pour permettre le LOAD
-- step4 pipeline
step4_memre : pipeline_step PORT MAP(mem_A, mem_B_out, mem_C, mem_OP, clk, re_A, re_B, re_C, re_OP);
-- LC step 4
with re_OP select
W_enable <= '1' when X"6",
'1' when X"5",
'1' when X"1",
'1' when X"2",
'1' when X"3",
'0' when others;
process(clk)
begin
if clk'event and clk='1' then
PC <= PC+'1';
end if;
end process;
END cpu_arch;

9
src/instruction_memory.vhd
View file

@ -25,15 +25,6 @@ entity instruction is
end loop;
init_result(0) := X"06010A00"; -- AFC 0x0a to R01
init_result(1) := X"06020B00"; -- AFC 0x0b to R02
init_result(2) := X"06030200"; -- AFC 0x0c to R03
init_result(3) := X"06040D00"; -- AFC 0x0d to R04
init_result(4) := X"06050E00"; -- AFC 0x0e to R05
init_result(5) := X"05000100"; -- COPY R01 to R00
init_result(6) := X"01060102"; -- ADD R06=R01+R02
init_result(7) := X"02070103"; -- MUL R07=R01*R03
init_result(8) := X"03080201"; -- SOUS R08=R01-R02
init_result(9) := X"08000100"; -- STORE [@00] <- R01
init_result(20) := X"07090000"; -- LOAD R09 -< [@00]
return init_result;
end function init;
end instruction;