INSA/vhdl_processor
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SOUSTRACTION Done.

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Lemonochrome 2023-12-01 23:10:19 +01:00
parent d422136f63
commit ca7412e7c7
3 changed files with 11 additions and 6 deletions
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2
cpu_project/cpu_project.xpr
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@ -60,7 +60,7 @@
<Option Name="EnableBDX" Val="FALSE"/> <Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/> <Option Name="DSABoardId" Val="basys3"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/> <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="880"/> <Option Name="WTXSimLaunchSim" Val="892"/>
<Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/>

12
src/cpu.vhd
View file

@ -147,7 +147,7 @@ BEGIN
A_DI_EX <= A_LI_DI; A_DI_EX <= A_LI_DI;
C_DI_EX <= C_LI_DI; C_DI_EX <= C_LI_DI;
R_ADDRESS_A_HANDLE <= B_LI_DI(3 downto 0); R_ADDRESS_A_HANDLE <= B_LI_DI(3 downto 0);
elsif OP_LI_DI = X"01" or OP_LI_DI = X"02" then -- ADD elsif OP_LI_DI = X"01" or OP_LI_DI = X"02" or OP_LI_DI = X"03" then -- ADD
OP_DI_EX <= OP_LI_DI; OP_DI_EX <= OP_LI_DI;
A_DI_EX <= A_LI_DI; A_DI_EX <= A_LI_DI;
R_ADDRESS_B_HANDLE <= C_LI_DI(3 downto 0); R_ADDRESS_B_HANDLE <= C_LI_DI(3 downto 0);
@ -172,7 +172,7 @@ BEGIN
OP_EX_MEM <= OP_DI_EX; OP_EX_MEM <= OP_DI_EX;
A_EX_MEM <= A_DI_EX; A_EX_MEM <= A_DI_EX;
B_EX_MEM <= A_DATA_OUT_HANDLE; -- Pour éviter décallage temporel on passe directement A_DATA_OUT_HANDLE au lieu de B_DI_EX B_EX_MEM <= A_DATA_OUT_HANDLE; -- Pour éviter décallage temporel on passe directement A_DATA_OUT_HANDLE au lieu de B_DI_EX
elsif OP_DI_EX = X"01" or OP_DI_EX = X"02" then elsif OP_DI_EX = X"01" or OP_DI_EX = X"02" or OP_DI_EX = X"03" then
-- ALU -- ALU
OP_EX_MEM <= OP_DI_EX; OP_EX_MEM <= OP_DI_EX;
A_EX_MEM <= A_DI_EX; A_EX_MEM <= A_DI_EX;
@ -182,6 +182,8 @@ BEGIN
ALU_OP_TYPE <= "000"; -- ADD ALU_OP_TYPE <= "000"; -- ADD
elsif OP_DI_EX = X"02" then elsif OP_DI_EX = X"02" then
ALU_OP_TYPE <= "110"; -- Multiplication ALU_OP_TYPE <= "110"; -- Multiplication
elsif OP_DI_EX = X"03" then
ALU_OP_TYPE <= "001"; -- Soustraction
end if; end if;
else else
OP_EX_MEM <= X"00"; OP_EX_MEM <= X"00";
@ -199,7 +201,7 @@ BEGIN
OP_MEM_RE <= OP_EX_MEM; OP_MEM_RE <= OP_EX_MEM;
A_MEM_RE <= A_EX_MEM; A_MEM_RE <= A_EX_MEM;
B_MEM_RE <= B_EX_MEM; B_MEM_RE <= B_EX_MEM;
elsif OP_EX_MEM = X"01" or OP_EX_MEM = X"02" then elsif OP_EX_MEM = X"01" or OP_EX_MEM = X"02" or OP_EX_MEM = X"03" then
OP_MEM_RE <= OP_EX_MEM; OP_MEM_RE <= OP_EX_MEM;
A_MEM_RE <= A_EX_MEM; A_MEM_RE <= A_EX_MEM;
B_MEM_RE <= ALU_DATA_OUT; B_MEM_RE <= ALU_DATA_OUT;
@ -216,7 +218,7 @@ BEGIN
begin begin
if rising_edge(clk) then if rising_edge(clk) then
-- Ecrire dans les registres -- Ecrire dans les registres
if OP_MEM_RE = X"06" or OP_MEM_RE = X"05" or OP_MEM_RE = X"01" or OP_MEM_RE = X"02" then if OP_MEM_RE = X"06" or OP_MEM_RE = X"05" or OP_MEM_RE = X"01" or OP_MEM_RE = X"02" or OP_MEM_RE = X"03" then
W_ADDRESS_HANDLE <= A_MEM_RE(3 downto 0); W_ADDRESS_HANDLE <= A_MEM_RE(3 downto 0);
W_DATA_HANDLE <= B_MEM_RE; W_DATA_HANDLE <= B_MEM_RE;
else else
@ -230,7 +232,7 @@ BEGIN
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if OP_MEM_RE = X"06" or OP_MEM_RE = X"05" or OP_MEM_RE = X"01" or OP_MEM_RE = X"02" then if OP_MEM_RE = X"06" or OP_MEM_RE = X"05" or OP_MEM_RE = X"01" or OP_MEM_RE = X"02" or OP_MEM_RE = X"03" then
W_ENABLE_HANDLE <= '1'; W_ENABLE_HANDLE <= '1';
else else
W_ENABLE_HANDLE <= '0'; W_ENABLE_HANDLE <= '0';

3
src/instruction_memory.vhd
View file

@ -45,6 +45,9 @@ entity instruction is
init_result(17) := X"01020505"; -- ADD 3 + 3 init_result(17) := X"01020505"; -- ADD 3 + 3
-- Multiplication -- Multiplication
init_result(18) := X"02020505"; -- MULTIPLICATION 3 * 3 init_result(18) := X"02020505"; -- MULTIPLICATION 3 * 3
-- Soustraction
init_result(19) := X"03020303"; -- Soustraction 1 - 1
init_result(20) := X"03020504"; -- Soustraction 3 - 2
return init_result; return init_result;