diff --git a/cpu_project/cpu_project.xpr b/cpu_project/cpu_project.xpr new file mode 100644 index 0000000..b855ad2 --- /dev/null +++ b/cpu_project/cpu_project.xpr @@ -0,0 +1,241 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/src/data_memory.vhd b/src/data_memory.vhd index dfd2b5a..6d890ce 100644 --- a/src/data_memory.vhd +++ b/src/data_memory.vhd @@ -3,16 +3,16 @@ use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; -entity DataMemory is +entity data_memory is Port ( CLK : in STD_LOGIC; RST : in STD_LOGIC; RW_ENABLE : in STD_LOGIC; ADDR : in STD_LOGIC_VECTOR(7 downto 0); DATA_IN : in STD_LOGIC_VECTOR(7 downto 0); DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0)); -end DataMemory; +end data_memory; -architecture Behavioral of DataMemory is +architecture Behavioral of data_memory is type MemoryArray is array (0 to 255) of STD_LOGIC_VECTOR(7 downto 0); signal Memory : MemoryArray := (others => X"00"); begin diff --git a/src/data_memory_tb.vhd b/src/data_memory_tb.vhd index 9d7d49f..efe4aac 100644 --- a/src/data_memory_tb.vhd +++ b/src/data_memory_tb.vhd @@ -3,10 +3,10 @@ use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; -entity DataMemory_TB is -end DataMemory_TB; +entity data_memory_TB is +end data_memory_TB; -architecture Behavioral of DataMemory_TB is +architecture Behavioral of data_memory_TB is signal CLK : STD_LOGIC := '0'; signal RST : STD_LOGIC := '0'; signal RW_ENABLE : STD_LOGIC := '0'; @@ -16,8 +16,8 @@ architecture Behavioral of DataMemory_TB is constant CLOCK_PERIOD : time := 10 ns; -- Define your clock period here begin - -- Instantiate the DataMemory component - UUT: entity work.DataMemory + -- Instantiate the data_memory component + UUT: entity work.data_memory port map ( CLK => CLK, RST => RST,