diff --git a/cpu_project/cpu_project.xpr b/cpu_project/cpu_project.xpr
index 8da78d5..e4b2453 100644
--- a/cpu_project/cpu_project.xpr
+++ b/cpu_project/cpu_project.xpr
@@ -60,7 +60,7 @@
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
     <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
-    <Option Name="WTXSimLaunchSim" Val="285"/>
+    <Option Name="WTXSimLaunchSim" Val="306"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
diff --git a/src/cpu.vhd b/src/cpu.vhd
index 247fd02..786c87f 100644
--- a/src/cpu.vhd
+++ b/src/cpu.vhd
@@ -85,16 +85,19 @@ ARCHITECTURE cpu_arch OF cpu IS
     signal B_RE  : STD_LOGIC_VECTOR (7 downto 0);
     signal C_RE  : STD_LOGIC_VECTOR (7 downto 0);
 
-    
+    signal W_ADDRESS_HANDLE : STD_LOGIC_VECTOR(3 DOWNTO 0);
+    signal W_DATA_HANDLE    : STD_LOGIC_VECTOR(7 DOWNTO 0);
+    signal W_ENABLE_HANDLE  : STD_LOGIC;
+
 BEGIN
    -- Instantiation des composants
    RegisterFile_Instance: reg PORT MAP (
     address_A => "0000",
     address_B => "0000",
-    address_W => "0000",
-    W_Enable  => '0',
-    W_Data    => "00000000",
-    reset     => '0',
+    address_W => W_ADDRESS_HANDLE,
+    W_Enable  => W_ENABLE_HANDLE,
+    W_Data    => W_DATA_HANDLE,
+    reset     => '1',
     clk       => clk,
     A_Data    => open,
     B_Data    => open
@@ -180,6 +183,10 @@ BEGIN
                     A_RE <= A_MEM;
                     B_RE <= B_MEM;
                     C_RE <= C_MEM;
+
+                    W_ENABLE_HANDLE  <= '1';
+                    W_ADDRESS_HANDLE <= A_RE(3 downto 0);
+                    W_DATA_HANDLE    <= B_RE;
                 when others =>
                     null;
             end case;
diff --git a/src/instruction_memory.vhd b/src/instruction_memory.vhd
index b7ba23a..3b568cc 100644
--- a/src/instruction_memory.vhd
+++ b/src/instruction_memory.vhd
@@ -23,9 +23,12 @@ entity instruction is
         for i in code_array'range loop
             init_result(i) := std_logic_vector(conv_unsigned(0, 32));
         end loop;
-        init_result(0) := X"060A0B0C";
-        init_result(1) := X"060F0F0F";
-        init_result(2) := X"060A0B0C";
+        init_result(0) := X"06000A0F";
+        init_result(1) := X"06010B0F";
+        init_result(2) := X"06020C0F";
+        init_result(3) := X"06030D0F";
+        init_result(4) := X"06040E0F";
+        init_result(5) := X"06050F0F";
         return init_result;
     end function init;
 end instruction;