Base CPU AFC Instruction wiring.

cpu_project/cpu_project.xpr

@@ -91,18 +91,6 @@
   <FileSets Version="1" Minor="31">
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
       <Filter Type="Srcs"/>
-      <File Path="$PPRDIR/../src/alu.vhd">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../src/data_memory.vhd">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
       <File Path="$PPRDIR/../src/instruction_memory.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -127,6 +115,20 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PPRDIR/../src/alu.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/data_memory.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="cpu"/>
@@ -157,6 +159,14 @@
     </FileSet>
     <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
       <Filter Type="Utils"/>
+      <File Path="$PSRCDIR/utils_1/imports/synth_1/data_memory.dcp">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedInSteps" Val="synth_1"/>
+          <Attr Name="AutoDcp" Val="1"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
@@ -184,7 +194,7 @@
     </Simulator>
   </Simulators>
   <Runs Version="1" Minor="20">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/data_memory.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
           <Desc>Vivado Synthesis Defaults</Desc>

src/cpu.vhd

@@ -4,6 +4,10 @@ use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 entity cpu is
+    Port (
+        clk : in STD_LOGIC;
+        instruction_pointer : in STD_LOGIC_VECTOR(7 downto 0)
+    );
 end cpu;
 
 ARCHITECTURE cpu_arch OF cpu IS
@@ -64,16 +68,25 @@ ARCHITECTURE cpu_arch OF cpu IS
     );
     END COMPONENT;
 
-	---FOR ALL : instruction USE ENTITY work.instruction;
+    signal li_A, di_A, ex_A, mem_A, re_A  : STD_LOGIC_VECTOR(7 downto 0);
-begin
+    signal li_B, di_B, ex_B, mem_B, re_B : STD_LOGIC_VECTOR(7 downto 0);
-    step1_lidi  : pipeline_step PORT MAP();
+    signal li_C, di_C, ex_C, mem_C, re_C : STD_LOGIC_VECTOR(7 downto 0);
-    step2_diex  : pipeline_step PORT MAP();
+    signal di_OP, ex_OP, mem_OP, re_OP : STD_LOGIC_VECTOR(3 downto 0);
-    step3_exmem : pipeline_step PORT MAP();
+    signal li_OP : STD_LOGIC_VECTOR(31 downto 0);
-    step4_memre : pipeline_step PORT MAP();
+    ---signal main_clk : STD_LOGIC;
     
-    instruction_memory_inst : instruction PORT MAP();
+    signal empty_8 : STD_LOGIC_VECTOR(7 downto 0);
-    memory_register_inst    : reg PORT MAP();
+    signal empty_4 : STD_LOGIC_VECTOR(3 downto 0);
-    alu_inst                : alu PORT_MAP();
+    
-    data_memory_inst        : data_memory PORT MAP();
+begin
+    step1_lidi  : pipeline_step PORT MAP(li_A, li_B, li_C, li_OP(7 downto 4), clk, di_A, di_B, di_C, di_OP);
+    step2_diex  : pipeline_step PORT MAP(di_A, di_B, di_C, di_OP, clk, ex_A, ex_B, ex_C, ex_OP);
+    step3_exmem : pipeline_step PORT MAP(ex_A, ex_B, ex_C, ex_OP, clk, mem_A, mem_B, mem_C, mem_OP);
+    step4_memre : pipeline_step PORT MAP(mem_A, mem_B, mem_C, mem_OP, clk, re_A, re_B, re_C, re_OP);
+    
+    instruction_memory_inst : instruction PORT MAP(instruction_pointer, li_OP , clk);
+    memory_register_inst    : reg PORT MAP(empty_4, empty_4, re_A(3 downto 0), re_OP(0), re_B, '0', clk, empty_8, empty_8);
+    -- alu_inst                : alu PORT MAP();
+    -- data_memory_inst        : data_memory PORT MAP();
 
 END cpu_arch;

src/pipeline_step.vhd

@@ -23,9 +23,9 @@ begin
         begin
             if clk'event and clk='1' then
                 A_out <= A_in;
-                A_out <= B_in;
+                B_out <= B_in;
-                A_out <= C_in;
+                C_out <= C_in;
-                A_out <= OP_in;
+                OP_out <= OP_in;
             end if;
     end process;
 end behavior_pipeline_step;