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ADD Done.

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Lemonochrome 2023-12-01 22:26:39 +01:00
parent 77791b514a
commit f65b4dfcd0
3 changed files with 64 additions and 49 deletions
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15
cpu_project/cpu_project.xpr
View file

@ -60,7 +60,7 @@
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="815"/>
<Option Name="WTXSimLaunchSim" Val="875"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@ -91,6 +91,12 @@
<FileSets Version="1" Minor="32">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../src/alu.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/instruction_memory.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@ -109,13 +115,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/alu.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/data_memory.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>

56
src/cpu.vhd
View file

@ -74,12 +74,10 @@ ARCHITECTURE cpu_arch OF cpu IS
signal OP_EX_MEM : STD_LOGIC_VECTOR (7 downto 0);
signal A_EX_MEM : STD_LOGIC_VECTOR (7 downto 0);
signal B_EX_MEM : STD_LOGIC_VECTOR (7 downto 0);
signal C_EX_MEM : STD_LOGIC_VECTOR (7 downto 0);
signal OP_MEM_RE: STD_LOGIC_VECTOR (7 downto 0);
signal A_MEM_RE : STD_LOGIC_VECTOR (7 downto 0);
signal B_MEM_RE : STD_LOGIC_VECTOR (7 downto 0);
signal C_MEM_RE : STD_LOGIC_VECTOR (7 downto 0);
@ -93,7 +91,12 @@ ARCHITECTURE cpu_arch OF cpu IS
signal A_DATA_OUT_HANDLE : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal B_DATA_OUT_HANDLE : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal TEST : STD_LOGIC_VECTOR(7 downto 0) := X"FF";
-- ALU specific signals
signal ALU_A_OPERAND : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal ALU_B_OPERAND : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal ALU_OP_TYPE : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Add, Soustraction, etc...
signal ALU_DATA_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal ALU_FLAGS : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
-- Instantiation des composants
@ -116,12 +119,16 @@ BEGIN
clk => clk
);
ALU_Instance: alu PORT MAP (
a => ALU_A_OPERAND,
b => ALU_B_OPERAND,
op => ALU_OP_TYPE,
s => ALU_DATA_OUT,
flags => ALU_FLAGS
);
-- Pipeline
OP_LI_DI <= IR(31 downto 24);
A_LI_DI <= IR(23 downto 16);
B_LI_DI <= IR(15 downto 8);
@ -135,12 +142,15 @@ BEGIN
A_DI_EX <= A_LI_DI;
B_DI_EX <= B_LI_DI;
C_DI_EX <= C_LI_DI;
elsif OP_LI_DI = X"05" then
elsif OP_LI_DI = X"05" then -- COPY
OP_DI_EX <= OP_LI_DI;
A_DI_EX <= A_LI_DI;
C_DI_EX <= C_LI_DI;
-- B_DI_EX <= A_DATA_OUT_HANDLE;
R_ADDRESS_A_HANDLE <= B_LI_DI(3 downto 0);
elsif OP_LI_DI = X"01" then -- ADD
OP_DI_EX <= OP_LI_DI;
A_DI_EX <= A_LI_DI;
R_ADDRESS_B_HANDLE <= C_LI_DI(3 downto 0);
R_ADDRESS_A_HANDLE <= B_LI_DI(3 downto 0);
else
OP_DI_EX <= X"00";
@ -154,22 +164,25 @@ BEGIN
DI_EX: process(clk)
begin
if rising_edge(clk) then
-- Executer instruction si nécéssaire (ALU)
if OP_DI_EX = X"06" then
OP_EX_MEM <= OP_DI_EX;
A_EX_MEM <= A_DI_EX;
B_EX_MEM <= B_DI_EX;
C_EX_MEM <= C_DI_EX;
elsif OP_DI_EX = X"05" then
OP_EX_MEM <= OP_DI_EX;
A_EX_MEM <= A_DI_EX;
B_EX_MEM <= A_DATA_OUT_HANDLE;
C_EX_MEM <= C_DI_EX;
B_EX_MEM <= A_DATA_OUT_HANDLE; -- Pour éviter décallage temporel on passe directement A_DATA_OUT_HANDLE au lieu de B_DI_EX
elsif OP_DI_EX = X"01" then
-- ALU
OP_EX_MEM <= OP_DI_EX;
A_EX_MEM <= A_DI_EX;
ALU_A_OPERAND <= A_DATA_OUT_HANDLE;
ALU_B_OPERAND <= B_DATA_OUT_HANDLE;
ALU_OP_TYPE <= "000"; -- ADD
else
OP_EX_MEM <= X"00";
A_EX_MEM <= X"00";
B_EX_MEM <= X"00";
C_EX_MEM <= X"00";
end if;
end if;
end process;
@ -182,12 +195,14 @@ BEGIN
OP_MEM_RE <= OP_EX_MEM;
A_MEM_RE <= A_EX_MEM;
B_MEM_RE <= B_EX_MEM;
C_MEM_RE <= C_EX_MEM;
elsif OP_EX_MEM = X"01" then
OP_MEM_RE <= OP_EX_MEM;
A_MEM_RE <= A_EX_MEM;
B_MEM_RE <= ALU_DATA_OUT;
else
OP_MEM_RE <= X"00";
A_MEM_RE <= X"00";
B_MEM_RE <= X"00";
C_MEM_RE <= X"00";
end if;
end if;
end process;
@ -197,10 +212,7 @@ BEGIN
begin
if rising_edge(clk) then
-- Ecrire dans les registres
if OP_MEM_RE = X"06" then
W_ADDRESS_HANDLE <= A_MEM_RE(3 downto 0);
W_DATA_HANDLE <= B_MEM_RE;
elsif OP_MEM_RE = X"05" then
if OP_MEM_RE = X"06" or OP_MEM_RE = X"05" or OP_MEM_RE = X"01" then
W_ADDRESS_HANDLE <= A_MEM_RE(3 downto 0);
W_DATA_HANDLE <= B_MEM_RE;
else
@ -214,7 +226,7 @@ BEGIN
process(clk)
begin
if rising_edge(clk) then
if OP_MEM_RE = X"06" or OP_MEM_RE = X"05" then
if OP_MEM_RE = X"06" or OP_MEM_RE = X"05" or OP_MEM_RE = X"01" then
W_ENABLE_HANDLE <= '1';
else
W_ENABLE_HANDLE <= '0';

18
src/instruction_memory.vhd
View file

@ -23,12 +23,12 @@ entity instruction is
for i in code_array'range loop
init_result(i) := std_logic_vector(conv_unsigned(0, 32));
end loop;
init_result(0) := X"0600AA00";
init_result(1) := X"0601BB00";
init_result(2) := X"0602CC00";
init_result(3) := X"0603DD00";
init_result(4) := X"0604EE00";
init_result(5) := X"0605FF00";
init_result(0) := X"06000200";
init_result(1) := X"06010300";
init_result(2) := X"06020200";
init_result(3) := X"06030100";
init_result(4) := X"06040200";
init_result(5) := X"06050300";
init_result(6) := X"00000000";
init_result(7) := X"00000000";
init_result(8) := X"00000000";
@ -38,8 +38,12 @@ entity instruction is
init_result(12) := X"00000000";
-- Copy
init_result(13) := X"05000300"; -- Copier ce qu'il y a à @03 à @00
init_result(14) := X"05010200"; -- Copier [@2] à @1
-- ADD
init_result(15) := X"01020404"; -- ADD 2 + 2
init_result(16) := X"01020405"; -- ADD 2 + 3
init_result(17) := X"01020505"; -- ADD 3 + 3
-- init_result(6) := X"0502010F";
return init_result;
end function init;
end instruction;