# Risc V VHDL 5 Stages Pipeline

![image (3)](https://github.com/user-attachments/assets/323dff06-e9e8-466a-80a0-488c203bee9c)


**Key Improvements in Develop Branch:**
- Better understanding of VHDL allowed for a more efficient design.
- The removal of redundant pipeline stage components streamlined the microprocessor, reducing bottlenecks and increasing operational frequency.


1. **Main Branch:**
   - Frequency: 68.19 MHz
   - Design philosophy:
     - Relied on components for pipeline stages.
     - These components added complexity and increased the number of logical gates required, leading to slower processing.

2. **Develop Branch:**
   - Frequency: 168.55 MHz
   - Design philosophy:
     - Simplified architecture by eliminating unnecessary pipeline stage components.
     - Optimized signal paths and reduced the number of logical gate transitions, leading to higher efficiency and speed.