mirror of
https://github.com/Lemonochrme/vhdl_processor.git
synced 2025-06-08 17:00:50 +02:00
129 lines
No EOL
3.5 KiB
VHDL
129 lines
No EOL
3.5 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity cpu is
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Port (
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clk : in STD_LOGIC
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);
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end cpu;
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ARCHITECTURE cpu_arch OF cpu IS
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-- Code memory
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COMPONENT instruction IS
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PORT (
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instruction : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Adresse de l'instruction
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code : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- Code de l'instruction
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clk : IN STD_LOGIC
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);
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END COMPONENT;
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-- Data memory
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COMPONENT data_memory IS
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PORT (
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clk : IN STD_LOGIC;
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rst : IN STD_LOGIC; -- Reset actif à '1'
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rw_enable : IN STD_LOGIC; -- Lecture: '1' Ecriture: '0'
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addr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Adresse de la zone mémoire
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data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Data écrite à l'adresse addr
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data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) -- Data présente à l'adresse addr
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);
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END COMPONENT;
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-- Register file
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COMPONENT reg IS
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PORT (
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address_A : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Permet de lire le registre à l'address_A sortie sur A_Data
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address_B : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Permet de lire le registre à l'address_B sortie sur B_Data
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address_W : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Permet d'écrire les données de W_Data à l'adresse address_W
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W_Enable : IN STD_LOGIC; -- Si W_Enable='1' alors écriture
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W_Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Données à écrire
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reset : IN STD_LOGIC; -- Reset actif à '0'
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clk : IN STD_LOGIC;
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A_Data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Sortie des données présentes à l'address_A
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B_Data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) -- Sortie des données présentes à l'address_B
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);
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END COMPONENT;
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-- Arithmentic Logic Unit
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COMPONENT alu IS
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PORT (
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a : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Opérande a
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b : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Opérande b
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op : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- Code de l'operation
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s : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Sortie de l'operation
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flags : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) -- Flags de l'ALU (C, N, Z, O)
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);
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END COMPONENT;
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-- Signaux internes
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signal PC : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; -- Program Counter
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signal IR : STD_LOGIC_VECTOR (31 downto 0); -- Instruction Register
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signal A : STD_LOGIC_VECTOR (7 downto 0);
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signal B : STD_LOGIC_VECTOR (7 downto 0);
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signal C : STD_LOGIC_VECTOR (7 downto 0);
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BEGIN
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-- Instantiation des composants
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RegisterFile_Instance: reg PORT MAP (
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address_A => "0000",
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address_B => "0000",
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address_W => "0000",
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W_Enable => '0',
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W_Data => "00000000",
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reset => '0',
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clk => clk,
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A_Data => open,
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B_Data => open
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);
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-- Pipeline
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-- Lecture Instruction (LI)
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LI: process(clk)
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begin
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if rising_edge(clk) then
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-- Charger les instruction
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end if;
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end process;
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DI: process(clk)
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begin
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if rising_edge(clk) then
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-- Decoder IR et init A B C
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end if;
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end process;
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EX: process(clk)
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begin
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if rising_edge(clk) then
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-- Executer instruction si nécéssaire
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end if;
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end process;
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MEM: process(clk)
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begin
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if rising_edge(clk) then
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-- Ecrire ou lire memoire des données
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end if;
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end process;
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RE: process(clk)
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begin
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if rising_edge(clk) then
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-- Ecrire dans les registres
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end if;
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end process;
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PC_UPDATE: process(clk)
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begin
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if rising_edge(clk) then
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PC <= PC + 1;
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end if;
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end process;
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END cpu_arch; |