diff --git a/exam/exo1.c b/exam/exo1.c
new file mode 100755
index 0000000..ee78042
--- /dev/null
+++ b/exam/exo1.c
@@ -0,0 +1,31 @@
+/*
+ * controletptestxddd.c
+ *
+ * Created: 04/04/2021 15:10:52
+ * Author : Alzyohan
+ */ 
+
+#include <avr/io.h>
+
+
+int main(void)
+{
+    DDRC=0xFF;	//en sortie (led)
+	DDRB=0x00;	//en entrée (bouton poussoir)
+    while (1) 
+    {
+		if((PINB & (1<<PB0))==0)
+		{
+			PORTC=~('<');
+		}
+		if((PINB & (1<<PB1))==0)
+		{
+			PORTC=~('>');
+		}
+		else
+		{
+			PORTC=0xFF;
+		};
+    };
+}
+
diff --git a/exam/exo2-partie2.c b/exam/exo2-partie2.c
new file mode 100755
index 0000000..d842d54
--- /dev/null
+++ b/exam/exo2-partie2.c
@@ -0,0 +1,50 @@
+/*
+ * controletptestxddd.c
+ *
+ * Created: 04/04/2021 15:10:52
+ * Author : Alzyohan
+ */ 
+
+#include <avr/io.h>
+#define F_CPU 3686400
+#include <util/delay.h>
+#define UBRR_THEO 47
+void uart_init(void);
+void emettre_can(char c);
+
+int main(void)
+{
+	unsigned char x='<';
+	unsigned char y='>';
+	uart_init();
+	DDRC=0xFF;	//en sortie (led)
+	DDRB=0x00;	//en entrée (bouton poussoir)
+    while (1) 
+    {
+		if((PINB & (1<<PB0))==0)
+		{
+			emettre_can(x);
+		}
+		if((PINB & (1<<PB1))==0)
+		{
+			emettre_can(y);
+		}
+		_delay_ms(1000);
+    };
+}
+
+void uart_init(void)
+{
+	DDRD |= (1<<PD1);
+	UBRRL = UBRR_THEO;
+	UCSRB |= (1<<TXEN);
+	UCSRC |= (1<<USBS)|(3<<UPM0)|(3<<UCSZ0);
+}
+
+void emettre_can(char c)
+{
+	do{
+	//rien	
+	}while ( !(UCSRA & (1<<UDRE)) );
+	UDR = c;
+}
\ No newline at end of file
diff --git a/exam/exo2.c b/exam/exo2.c
new file mode 100755
index 0000000..7ef0b73
--- /dev/null
+++ b/exam/exo2.c
@@ -0,0 +1,40 @@
+/*
+ * controletptestxddd.c
+ *
+ * Created: 04/04/2021 15:10:52
+ * Author : Alzyohan
+ */ 
+
+#include <avr/io.h>
+#define F_CPU 3686400
+#include <util/delay.h>
+#define UBRR_THEO 47
+void uart_init(void);
+void uart_putchar(char c);
+
+int main(void)
+{
+	unsigned char x='<';
+	uart_init();
+    while (1) 
+    {
+		uart_putchar(x);
+		_delay_ms(1000);
+    };
+}
+
+void uart_init(void)
+{
+	DDRD |= (1<<PD1);
+	UBRRL = UBRR_THEO;
+	UCSRB |= (1<<TXEN);
+	UCSRC |= (1<<USBS)|(3<<UPM0)|(3<<UCSZ0);
+}
+
+void uart_putchar(char c)
+{
+	do{
+	//rien	
+	}while ( !(UCSRA & (1<<UDRE)) );
+	UDR = c;
+}
\ No newline at end of file
diff --git a/exam/exo3.c b/exam/exo3.c
new file mode 100755
index 0000000..a044736
--- /dev/null
+++ b/exam/exo3.c
@@ -0,0 +1,37 @@
+/*
+ * controletptestxddd.c
+ *
+ * Created: 04/04/2021 15:10:52
+ * Author : Alzyohan
+ */ 
+
+#include <avr/io.h>
+void ADC_init(void);
+char ADC_read_value(void);
+
+int main(void)
+{
+	ADC_init();
+	DDRB=0xFF;
+	while(1){
+		PORTB=~ADC_read_value();
+    };
+}
+
+void ADC_init(void)
+{
+	DDRA &=~(1<<PA2);
+	ADMUX |= (2<<MUX0);
+	ADCSRA|=(1<<ADEN)|(3<<ADPS1);
+}
+
+char ADC_read_value(void)
+{
+	ADCSRA|=(1<<ADSC);
+	do{
+		//nothing
+	}while((ADCSRA&(1<<ADIF))==0);
+	
+	ADCSRA|=(1<<ADIF);
+	return ADCL;
+}
\ No newline at end of file
diff --git a/exam/exo4.c b/exam/exo4.c
new file mode 100755
index 0000000..c58183e
--- /dev/null
+++ b/exam/exo4.c
@@ -0,0 +1,78 @@
+/*
+ * controletptestxddd.c
+ *
+ * Created: 04/04/2021 15:10:52
+ * Author : Alzyohan
+ */ 
+
+#include <avr/io.h>
+#define F_CPU 3686400
+#include <util/delay.h>
+#define UBRR_THEO 47
+void ADC_init(void);
+char ADC_read_value(void);
+void uart_init(void);
+void emettre_can(char c);
+float converter(void);
+
+int main(void)
+{
+	unsigned char x='<';
+	unsigned char y='>';
+	float temp;
+	ADC_init();
+	uart_init();
+	DDRB=0xFF;
+	while(1){
+		_delay_ms(200);
+		temp = converter();
+		if(temp>1)
+		{
+			emettre_can(x);
+		}
+		else
+		{
+			emettre_can(y);
+		};
+    };
+}
+
+void ADC_init(void)
+{
+	DDRA &=~(1<<PA2);
+	ADMUX |= (2<<MUX0);
+	ADCSRA|=(1<<ADEN)|(3<<ADPS1);
+}
+
+char ADC_read_value(void)
+{
+	ADCSRA|=(1<<ADSC);
+	do{
+		//nothing
+	}while((ADCSRA&(1<<ADIF))==0);
+	
+	ADCSRA|=(1<<ADIF);
+	return ADC;
+}
+
+void uart_init(void)
+{
+	DDRD |= (1<<PD1);
+	UBRRL = UBRR_THEO;
+	UCSRB |= (1<<TXEN);
+	UCSRC |= (1<<USBS)|(3<<UPM0)|(3<<UCSZ0);
+}
+
+void emettre_can(char c)
+{
+	do{
+		//rien
+	}while ( !(UCSRA & (1<<UDRE)) );
+	UDR = c;
+}
+
+float converter(void)
+{
+	float x = (5/1024)*ADC_read_value();
+	return x;
+}
\ No newline at end of file
diff --git a/exam/exo5.c b/exam/exo5.c
new file mode 100755
index 0000000..b456cbc
--- /dev/null
+++ b/exam/exo5.c
@@ -0,0 +1,22 @@
+/*
+ * controletptestxddd.c
+ *
+ * Created: 04/04/2021 15:10:52
+ * Author : Alzyohan
+ */ 
+
+#include <avr/io.h>
+void timer0_init();
+
+int main(void)
+{
+	DDRB|=(1<<PB3);
+	timer0_init();
+	return 0;
+}
+
+void timer0_init()
+{
+	OCR0=153;
+	TCCR0|=(1<<CS01)|(1<<WGM01)|(1<<COM00);
+}
diff --git a/exam/exo6.c b/exam/exo6.c
new file mode 100755
index 0000000..2292bf3
--- /dev/null
+++ b/exam/exo6.c
@@ -0,0 +1,33 @@
+/*
+ * controletptestxddd.c
+ *
+ * Created: 04/04/2021 15:10:52
+ * Author : Alzyohan
+ */ 
+
+#include <avr/io.h>
+#define SIGNAL_1500 153
+#define SIGNAL_3000 76
+void timer0_init();
+
+int main(void)
+{
+	DDRB|=(1<<PB3);
+	DDRC=0x00;
+	while(1){
+		if((PINC & (1<<PC0))==0)
+		{
+			timer0_init(SIGNAL_1500);
+		}
+		if((PINC & (1<<PC1))==0)
+		{
+			timer0_init(SIGNAL_3000);
+		}
+	}
+}
+
+void timer0_init(unsigned int x)
+{
+	OCR0=x;
+	TCCR0|=(1<<CS01)|(1<<WGM01)|(1<<COM00);
+}
diff --git a/exam/main.c b/exam/main.c
new file mode 100755
index 0000000..2292bf3
--- /dev/null
+++ b/exam/main.c
@@ -0,0 +1,33 @@
+/*
+ * controletptestxddd.c
+ *
+ * Created: 04/04/2021 15:10:52
+ * Author : Alzyohan
+ */ 
+
+#include <avr/io.h>
+#define SIGNAL_1500 153
+#define SIGNAL_3000 76
+void timer0_init();
+
+int main(void)
+{
+	DDRB|=(1<<PB3);
+	DDRC=0x00;
+	while(1){
+		if((PINC & (1<<PC0))==0)
+		{
+			timer0_init(SIGNAL_1500);
+		}
+		if((PINC & (1<<PC1))==0)
+		{
+			timer0_init(SIGNAL_3000);
+		}
+	}
+}
+
+void timer0_init(unsigned int x)
+{
+	OCR0=x;
+	TCCR0|=(1<<CS01)|(1<<WGM01)|(1<<COM00);
+}