library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

Entity digit is
Port (	clk, raz,E : in std_logic;
			QA,QB,QC	: out std_logic_vector(3 downto 0));
End digit;

Architecture Behaviour of digit is
signal A : std_logic_vector(3 downto 0);
signal B : std_logic_vector(3 downto 0);
signal C : std_logic_vector(3 downto 0);

Begin
process(clk, raz)
Begin
	
If (raz = '1') then 
A <="0000";
B <="0000";
C <="0000";

Elsif (clk'event and clk='1') then
If(E='1') then

		Elsif (A < 9) then
				A <= A+1;
				
		Elsif (A >= 9 and B < 9) then 
				A <="0000";
				B <= B+1;
				
		Elsif (B >= 9 and C < 4) then 
				B <="0000";
				C <= C+1;
				
		End if;
		End if;
		
End process;

process(E)
begin
if(E'event and E ='0' ) then
QA <= A;
QB <= B;
QC <= C;
end if;
end process;
	
End Behaviour;