// Copyright (C) 2017  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "11/30/2020 15:11:41"
                                                                                
// Verilog Test Bench (with test vectors) for design :                          bcd2
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module bcd2_vlg_vec_tst();
// constants                                           
// general purpose registers
reg AA;
reg BB;
reg CC;
reg DD;
reg endis;
reg horloge;
reg remiseazero;
// wires                                               
wire [3:0] Data;
wire [3:0] Donne;
wire [6:0] sor;
wire [6:0] sortie;

// assign statements (if any)                          
bcd2 i1 (
// port map - connection between master ports and signals/registers   
	.AA(AA),
	.BB(BB),
	.CC(CC),
	.Data(Data),
	.DD(DD),
	.Donne(Donne),
	.endis(endis),
	.horloge(horloge),
	.remiseazero(remiseazero),
	.sor(sor),
	.sortie(sortie)
);
initial 
begin 
#1000000 $finish;
end 

// AA
initial
begin
	AA = 1'b0;
end 

// BB
initial
begin
	BB = 1'b0;
end 

// CC
initial
begin
	CC = 1'b0;
end 

// DD
initial
begin
	DD = 1'b0;
end 

// endis
initial
begin
	endis = 1'b0;
end 

// horloge
always
begin
	horloge = 1'b0;
	horloge = #10000 1'b1;
	#10000;
end 

// remiseazero
initial
begin
	remiseazero = 1'b0;
end 
endmodule