# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
# Date created = 14:23:11  December 09, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		telemetre_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C7G
set_global_assignment -name TOP_LEVEL_ENTITY final
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:23:11  DECEMBER 09, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name VHDL_FILE digit.vhd
set_global_assignment -name BDF_FILE telemetre.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name BDF_FILE compteur.bdf
set_location_assignment PIN_C14 -to Seg1[6]
set_location_assignment PIN_E15 -to Seg1[5]
set_location_assignment PIN_C15 -to Seg1[4]
set_location_assignment PIN_C16 -to Seg1[3]
set_location_assignment PIN_E16 -to Seg1[2]
set_location_assignment PIN_D17 -to Seg1[1]
set_location_assignment PIN_C17 -to Seg1[0]
set_location_assignment PIN_C18 -to Seg2[6]
set_location_assignment PIN_D18 -to Seg2[5]
set_location_assignment PIN_E18 -to Seg2[4]
set_location_assignment PIN_B16 -to Seg2[3]
set_location_assignment PIN_A17 -to Seg2[2]
set_location_assignment PIN_A18 -to Seg2[1]
set_location_assignment PIN_B17 -to Seg2[0]
set_location_assignment PIN_B20 -to Seg3[6]
set_location_assignment PIN_A20 -to Seg3[5]
set_location_assignment PIN_B19 -to Seg3[4]
set_location_assignment PIN_A21 -to Seg3[3]
set_location_assignment PIN_B21 -to Seg3[2]
set_location_assignment PIN_C22 -to Seg3[1]
set_location_assignment PIN_B22 -to Seg3[0]
set_global_assignment -name QIP_FILE div1.qip
set_location_assignment PIN_P11 -to Clock14Hz
set_location_assignment PIN_V10 -to Echo
set_location_assignment PIN_W10 -to TriggerOutput
set_global_assignment -name VHDL_FILE dec_7seg.vhd
set_global_assignment -name BDF_FILE sisamarchepas.bdf
set_global_assignment -name BDF_FILE final.bdf
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Clock14Hz
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Echo
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg1[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg1[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg1[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg1[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg1[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg1[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg1[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg2[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg2[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg2[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg2[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg2[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg2[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg2[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg3[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg3[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg3[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg3[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg3[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg3[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg3[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Seg3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TriggerOutput
set_global_assignment -name VHDL_FILE frequencydivider.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top