library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

Entity frequencydivider is
Port (	SignalEntree : in std_logic;
			SignalSortieClock,SignalSortieTrigg : out std_logic);
End frequencydivider;

Architecture Behaviour of frequencydivider is
signal clock : std_logic_vector(12 downto 0);
signal trigg : std_logic_vector(21 downto 0);

Begin

	Seq : process(SignalEntree)
	Begin
	
If (SignalEntree'event and SignalEntree='1') then

			If (clock < 2857) then
				clock <= clock+1;
			Elsif (clock >= 2857) then 
				clock <="0000000000000";
			End If;
			
			If (trigg < 2000000) then
				trigg <= trigg+1;
			Elsif (trigg >= 2000000) then 
				trigg <="0000000000000000000000";
			End If;			
			
		End If;
	End process seq;
	
SignalSortieClock <= '1' when (clock = 0) else '0';
SignalSortieTrigg <= '1' when (trigg < 500) else '0';

End Behaviour;