# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
# Date created = 14:15:07  November 26, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		bcd_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C7G
set_global_assignment -name TOP_LEVEL_ENTITY bcd2
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:15:07  NOVEMBER 26, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name BDF_FILE bcd.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_location_assignment PIN_C18 -to sortie[6]
set_location_assignment PIN_D18 -to sortie[5]
set_location_assignment PIN_E18 -to sortie[4]
set_location_assignment PIN_B16 -to sortie[3]
set_location_assignment PIN_A17 -to sortie[2]
set_location_assignment PIN_A18 -to sortie[1]
set_location_assignment PIN_B17 -to sortie[0]
set_global_assignment -name BDF_FILE bcd2.bdf
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_D12 -to remiseazero
set_location_assignment PIN_B8 -to horloge
set_location_assignment PIN_C11 -to endis
set_location_assignment PIN_E15 -to sor[5]
set_location_assignment PIN_C14 -to sor[6]
set_location_assignment PIN_C15 -to sor[4]
set_location_assignment PIN_C16 -to sor[3]
set_location_assignment PIN_E16 -to sor[2]
set_location_assignment PIN_D17 -to sor[1]
set_location_assignment PIN_C17 -to sor[0]
set_location_assignment PIN_F15 -to AA
set_location_assignment PIN_B14 -to BB
set_location_assignment PIN_A14 -to CC
set_location_assignment PIN_A13 -to DD
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BB
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CC
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DD
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to endis
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to horloge
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to remiseazero
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sor[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sor[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sor[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sor[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sor[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sor[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sor[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sor
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sortie[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sortie[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sortie[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sortie[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sortie[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sortie[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sortie[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sortie
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top