library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

Entity frequencydivider2 is
Port (	SignalEntree : in std_logic;
			Q : out std_logic_vector(20 downto 0);
			SignalSortie : out std_logic);
End frequencydivider2;

Architecture Behaviour of frequencydivider2 is
signal D : std_logic_vector(20 downto 0);

Begin

	Seq : process(SignalEntree)
	Begin
	
		If (SignalEntree'event and SignalEntree='1') then
			If (D < 1000000) then
				D <= D+1;
				SignalSortie <= '0';
			Elsif (D >= 1000000) then 
				D <="000000000000000000000";
				SignalSortie <= '1';
			End If;
		End If;
	End process seq;
	
	Q<=D;
	
End Behaviour;