32 lines
No EOL
712 B
VHDL
32 lines
No EOL
712 B
VHDL
library ieee ;
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use ieee.std_logic_1164.all ;
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entity dec_7seg is
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port (d :in std_logic_vector (3 downto 0);
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seg :out std_logic_vector (6 downto 0));
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end dec_7seg;
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architecture ARCH1 of dec_7seg is
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begin
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with d select
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seg <= "0000001" when "0000",
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"1001111" when "0001",
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"0010010" when "0010",
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"0000110" when "0011",
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"1001100" when "0100",
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"0100100" when "0101",
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"0100000" when "0110",
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"0001111" when "0111",
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"0000000" when "1000",
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"0000100" when "1001",
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"0000010" when "1010",
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"1100000" when "1011",
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"1110010" when "1100",
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"1000010" when "1101",
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"0110000" when "1110",
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"0111000" when "1111",
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"1111111" when others;
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end ARCH1; |