102 lines
No EOL
5.3 KiB
Text
102 lines
No EOL
5.3 KiB
Text
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2017 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel FPGA IP License Agreement, or other applicable license
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# agreement, including, without limitation, that your use is for
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# the sole purpose of programming logic devices manufactured by
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# Intel and sold by Intel or its authorized distributors. Please
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# refer to the applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
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# Date created = 14:15:07 November 26, 2020
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# bcd_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus Prime software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "MAX 10"
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set_global_assignment -name DEVICE 10M50DAF484C7G
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set_global_assignment -name TOP_LEVEL_ENTITY bcd2
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:15:07 NOVEMBER 26, 2020"
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set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
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set_global_assignment -name BDF_FILE bcd.bdf
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set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
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set_location_assignment PIN_C18 -to sortie[6]
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set_location_assignment PIN_D18 -to sortie[5]
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set_location_assignment PIN_E18 -to sortie[4]
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set_location_assignment PIN_B16 -to sortie[3]
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set_location_assignment PIN_A17 -to sortie[2]
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set_location_assignment PIN_A18 -to sortie[1]
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set_location_assignment PIN_B17 -to sortie[0]
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set_global_assignment -name BDF_FILE bcd2.bdf
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_location_assignment PIN_D12 -to remiseazero
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set_location_assignment PIN_B8 -to horloge
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set_location_assignment PIN_C11 -to endis
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set_location_assignment PIN_E15 -to sor[5]
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set_location_assignment PIN_C14 -to sor[6]
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set_location_assignment PIN_C15 -to sor[4]
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set_location_assignment PIN_C16 -to sor[3]
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set_location_assignment PIN_E16 -to sor[2]
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set_location_assignment PIN_D17 -to sor[1]
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set_location_assignment PIN_C17 -to sor[0]
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set_location_assignment PIN_F15 -to AA
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set_location_assignment PIN_B14 -to BB
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set_location_assignment PIN_A14 -to CC
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set_location_assignment PIN_A13 -to DD
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AA
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BB
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CC
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DD
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to endis
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set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to horloge
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to remiseazero
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sor[6]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sor[5]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sor[4]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sor[3]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sor[2]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sor[1]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sor[0]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sor
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sortie[6]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sortie[5]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sortie[4]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sortie[3]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sortie[2]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sortie[1]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sortie[0]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sortie
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |