109 lines
2.6 KiB
Text
109 lines
2.6 KiB
Text
// Copyright (C) 2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License
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// Subscription Agreement, the Intel Quartus Prime License Agreement,
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// the Intel FPGA IP License Agreement, or other applicable license
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// agreement, including, without limitation, that your use is for
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// the sole purpose of programming logic devices manufactured by
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// Intel and sold by Intel or its authorized distributors. Please
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// refer to the applicable agreement for further details.
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// *****************************************************************************
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// This file contains a Verilog test bench with test vectors .The test vectors
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// are exported from a vector file in the Quartus Waveform Editor and apply to
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// the top level entity of the current Quartus project .The user can use this
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// testbench to simulate his design using a third-party simulation tool .
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// *****************************************************************************
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// Generated on "11/30/2020 15:11:41"
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// Verilog Test Bench (with test vectors) for design : bcd2
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//
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// Simulation tool : 3rd Party
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//
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`timescale 1 ps/ 1 ps
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module bcd2_vlg_vec_tst();
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// constants
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// general purpose registers
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reg AA;
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reg BB;
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reg CC;
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reg DD;
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reg endis;
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reg horloge;
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reg remiseazero;
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// wires
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wire [3:0] Data;
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wire [3:0] Donne;
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wire [6:0] sor;
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wire [6:0] sortie;
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// assign statements (if any)
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bcd2 i1 (
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// port map - connection between master ports and signals/registers
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.AA(AA),
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.BB(BB),
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.CC(CC),
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.Data(Data),
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.DD(DD),
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.Donne(Donne),
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.endis(endis),
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.horloge(horloge),
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.remiseazero(remiseazero),
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.sor(sor),
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.sortie(sortie)
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);
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initial
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begin
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#1000000 $finish;
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end
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// AA
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initial
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begin
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AA = 1'b0;
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end
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// BB
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initial
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begin
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BB = 1'b0;
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end
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// CC
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initial
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begin
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CC = 1'b0;
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end
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// DD
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initial
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begin
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DD = 1'b0;
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end
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// endis
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initial
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begin
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endis = 1'b0;
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end
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// horloge
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always
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begin
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horloge = 1'b0;
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horloge = #10000 1'b1;
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#10000;
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end
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// remiseazero
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initial
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begin
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remiseazero = 1'b0;
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end
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endmodule
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