42 lines
No EOL
757 B
VHDL
42 lines
No EOL
757 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity Frequence is
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port
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(hor: in std_logic;
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compteur,trigger: out std_logic);
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end Frequence;
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architecture Compteur of Frequence is
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signal Trigg : std_logic_vector(23 downto 0);
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signal Echo: std_logic_vector(12 downto 0);
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begin
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process(hor)
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begin
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if(hor'event and hor ='0') then
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if(Trigg < 5000000) then
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Trigg <= Trigg +1;
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else
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Trigg <= "000000000000000000000000";
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end if;
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if(Echo < 2940) then
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Echo <= Echo + 1;
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else
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Echo <= "0000000000000";
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end if;
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end if;
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end process;
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compteur <= '1' when (Echo = 0) else '0';
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trigger <= '1' when (Trigg < 500) else '0';
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end Compteur; |