40 lines
No EOL
939 B
VHDL
40 lines
No EOL
939 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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Entity frequencydivider is
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Port ( SignalEntree : in std_logic;
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SignalSortieClock,SignalSortieTrigg : out std_logic);
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End frequencydivider;
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Architecture Behaviour of frequencydivider is
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signal clock : std_logic_vector(12 downto 0);
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signal trigg : std_logic_vector(21 downto 0);
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Begin
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Seq : process(SignalEntree)
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Begin
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If (SignalEntree'event and SignalEntree='1') then
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If (clock < 2857) then
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clock <= clock+1;
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Elsif (clock >= 2857) then
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clock <="0000000000000";
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End If;
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If (trigg < 2000000) then
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trigg <= trigg+1;
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Elsif (trigg >= 2000000) then
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trigg <="0000000000000000000000";
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End If;
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End If;
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End process seq;
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SignalSortieClock <= '1' when (clock = 0) else '0';
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SignalSortieTrigg <= '1' when (trigg < 500) else '0';
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End Behaviour; |