32 lines
No EOL
663 B
VHDL
32 lines
No EOL
663 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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Entity frequencydivider1 is
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Port ( SignalEntree : in std_logic;
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Q : out std_logic_vector(12 downto 0);
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SignalSortie : out std_logic);
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End frequencydivider1;
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Architecture Behaviour of frequencydivider1 is
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signal D : std_logic_vector(12 downto 0);
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Begin
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Seq : process(SignalEntree)
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Begin
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If (SignalEntree'event and SignalEntree='1') then
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If (D < 2857) then
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D <= D+1;
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SignalSortie <= '0';
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Elsif (D >= 2857) then
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D <="0000000000000";
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SignalSortie <= '1';
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End If;
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End If;
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End process seq;
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Q <= D;
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End Behaviour; |