mirror of
https://github.com/yoboujon/dumber.git
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premier script pour compilation automatique du noyau xenomai
This commit is contained in:
vezde
parent
2ddb454c38
commit
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8 changed files with 326772 additions and 0 deletions
214
kernel/build-kernel.py
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214
kernel/build-kernel.py
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@ -0,0 +1,214 @@
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#!/usr/bin/env python3
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import os
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from statistics import median
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import time
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import sys
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from datetime import datetime
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from shutil import copytree
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from shutil import rmtree
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import paramiko
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from getpass import getpass
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# Parameters to configure
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TEMPORARY_DIRECTORY = '~/tmp/rpi-kernel'
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BUILD_DIRECTORY = '/rt-kernel'
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GET_SOURCES_CMDS = ['git clone https://github.com/raspberrypi/linux.git',
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'git clone https://github.com/raspberrypi/tools.git --depth 3',
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'wget http://xenomai.org/downloads/xenomai/stable/xenomai-3.0.7.tar.bz2',
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'tar jxf xenomai-3.0.7.tar.bz2',
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'cp %s/ipipe-core-4.14.37-rpi.patch .',
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'cp %s/config-4.14.37-xenomai .']
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CONFIGURE_CMDS = ['cd ./linux',
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'git reset --hard 29653ef5475124316b9284adb6cbfc97e9cae48f',
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'cd ..',
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'xenomai-3.0.7/scripts/prepare-kernel.sh --linux=linux/ --arch=arm --ipipe=ipipe-core-4.14.37-rpi.patch --verbose',
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'cp config-4.14.37-xenomai ./linux/.config']
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BUILD_CMDS = ['cd ./linux',
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'make %s zImage',
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'make %s modules',
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'make %s dtbs',
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'make %s modules_install',
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'make %s dtbs_install',
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'mkdir $INSTALL_MOD_PATH/boot',
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'cp ./arch/arm/boot/zImage $INSTALL_MOD_PATH/boot/$KERNEL.img',
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'cd ..']
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XENOMAI_BUILD_CMDS = ['cd xenomai-3.0.7',
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'./scripts/bootstrap --with-core=cobalt –disable-debug',
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'mkdir ./build',
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'cd ./build',
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'../configure CFLAGS="-march=armv7-a -mfpu=vfp3" LDFLAGS="-mtune=cortex-a53" --build=i686-pc-linux-gnu --host=arm-linux-gnueabihf --with-core=cobalt --enable-smp CC=${CROSS_COMPILE}gcc LD=${CROSS_COMPILE}ld',
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'make -j4 install'
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]
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PATH_TO_IMAGE = '/media/dimercur'
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#
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# Nothing to configure or modify under this line
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#
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def getSources(tmp_dir, script_dir, sourcesCmd):
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for cmd in sourcesCmd:
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if "%s" in cmd:
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os.system (cmd % script_dir)
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else:
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os.system (cmd)
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def configureKernel(tmp_dir, build_dir, configureCmd):
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for cmd in configureCmd:
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if 'cd ' in cmd:
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os.chdir(cmd.split()[1])
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else:
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os.system (cmd)
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def buildKernel(tmp_dir, build_dir, buildCmd, nb_threads=4):
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# Set environment variables
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os.environ["ARCH"] = "arm"
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os.environ["CROSS_COMPILE"] = tmp_dir+"/tools/arm-bcm2708/gcc-linaro-arm-linux-gnueabihf-raspbian/bin/arm-linux-gnueabihf-"
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os.environ["INSTALL_MOD_PATH"] = build_dir
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os.environ["INSTALL_DTBS_PATH"] = build_dir
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os.environ["KERNEL"] = "kernel7"
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for cmd in buildCmd:
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if 'cd ' in cmd:
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os.chdir(cmd.split()[1])
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else:
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if '%s' in cmd:
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threadOption = '-j'+str(nb_threads)
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print (cmd%threadOption)
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os.system(cmd%threadOption)
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else:
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os.system (cmd)
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os.chdir(build_dir)
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os.system('tar czf ../xenomai-kernel.tgz *')
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os.chdir(tmp_dir)
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def installKernel(tmp_dir, build_dir, image_path):
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os.chdir(tmp_dir)
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print (".... Install *.dtb")
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os.system('sudo cp %s/*.dtb %s/boot/'%(build_dir,image_path))
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print (".... Install kernel")
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os.system('sudo cp -rd %s/boot/* %s/boot/'%(build_dir,image_path))
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print (".... Install libraries (modules)")
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os.system('sudo cp -rd %s/lib/* %s/rootfs/lib/'%(build_dir,image_path))
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print (".... Install overlays")
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os.system('sudo cp -d %s/overlays/* %s/boot/overlays/'%(build_dir,image_path))
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print (".... Install bcm* files")
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os.system('sudo cp -d %s/bcm** %s/boot/'%(build_dir,image_path))
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print (".... Update config.txt file")
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file = open("%s/boot/config.txt"%image_path, "a") # append mode
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file.write("kernel=${zImage name}\ndevice_tree=bcm2710-rpi-3-b.dtb\n")
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file.close()
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print (".... Update cmdline.txt file")
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file = open("%s/boot/cmdline.txt"%image_path, "a") # append mode
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file.write(" dwc_otg.fiq_enable=0 dwc_otg.fiq_fsm_enable=0 dwc_otg.nak_holdoff=0")
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file.close()
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def buildXenomai(tmp_dir, build_dir, buildCmd):
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os.chdir(tmp_dir+"/xenomai-3.0.7")
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#for cmd in buildCmd:
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# if 'cd ' in cmd:
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# os.chdir(cmd.split()[1])
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# else:
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# os.system (cmd)
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# Set environment variables
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os.environ["ARCH"] = "arm"
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os.environ["CROSS_COMPILE"] = tmp_dir+"/tools/arm-bcm2708/gcc-linaro-arm-linux-gnueabihf-raspbian/bin/arm-linux-gnueabihf-"
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os.environ["INSTALL_MOD_PATH"] = build_dir
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os.environ["INSTALL_DTBS_PATH"] = build_dir
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os.environ["KERNEL"] = "kernel7"
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print (".... Bootstrap")
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os.system("./scripts/bootstrap --with-core=cobalt –disable-debug")
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print (".... Configure")
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os.system ("mkdir ./build")
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os.chdir("./build")
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os.system('../configure CFLAGS="-march=armv7-a -mfpu=vfp3" LDFLAGS="-mtune=cortex-a53" --build=i686-pc-linux-gnu --host=arm-linux-gnueabihf --with-core=cobalt --enable-smp CC=${CROSS_COMPILE}gcc LD=${CROSS_COMPILE}ld')
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print (".... Building")
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os.system('make -j4 install DESTDIR=${PWD}/target')
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def installXenomai(tmp_dir, build_dir, image_path ):
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os.chdir(tmp_dir+"/xenomai-3.0.7/build/target")
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os.system('sudo cp -a dev/* %s/rootfs/dev/'%image_path)
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os.system('sudo cp -a usr/* %s/rootfs/usr/'%image_path)
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def main():
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# prepare build environment
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temp_dir = os.path.expanduser (TEMPORARY_DIRECTORY)
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build_dir = temp_dir + BUILD_DIRECTORY
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script_dir=""
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for arg in sys.argv:
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if os.path.basename(__file__) in arg:
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script_dir = os.path.dirname(arg)
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break
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if script_dir == "":
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print ("Can't find directory of script (%s). Exit"%os.path.basename(__file__))
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return 2
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print ("Temp directory : " + temp_dir)
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print ("Build directory : " + build_dir)
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print ("Script directory : " + script_dir)
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print()
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if not os.path.exists(temp_dir):
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print ('Create temp directory "%s"'%temp_dir)
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os.makedirs(build_dir)
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else:
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val=input('Directory "%s" already exists. Ok to remove all contents ? [Y/n/c] '%temp_dir)
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if val=='n' or val=='N':
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return 1
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elif val=='c' or val=='C':
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pass
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else:
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print ('Purge temp directory "%s"'%temp_dir)
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rmtree(temp_dir, ignore_errors=True)
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os.makedirs(build_dir)
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currentdir = os.getcwd()
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os.chdir(temp_dir)
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print ("Retrieve sources")
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getSources(temp_dir,script_dir,GET_SOURCES_CMDS)
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print ("\nConfigure kernel")
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configureKernel(temp_dir, build_dir, CONFIGURE_CMDS)
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print ("\nBuild kernel")
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buildKernel(temp_dir,build_dir,BUILD_CMDS,nb_threads=4)
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print ('\nBuild Xenomai libraries')
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buildXenomai(temp_dir, build_dir, [])
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print ('\nInstalling kernel')
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installKernel(temp_dir, build_dir, PATH_TO_IMAGE)
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print ('\nInstall Xenomai libraries')
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installXenomai(temp_dir, build_dir, PATH_TO_IMAGE)
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os.chdir(currentdir)
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if __name__ == '__main__':
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val=main()
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if val ==None:
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val =0
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print ("\nBye bye")
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exit(val)
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6349
kernel/config-4.14.37-rpi
Normal file
6349
kernel/config-4.14.37-rpi
Normal file
File diff suppressed because it is too large
Load diff
7128
kernel/config-5.4.83-xenomai
Normal file
7128
kernel/config-5.4.83-xenomai
Normal file
File diff suppressed because it is too large
Load diff
312428
kernel/ipipe-core-5.4.83-rpi.patch
Normal file
312428
kernel/ipipe-core-5.4.83-rpi.patch
Normal file
File diff suppressed because it is too large
Load diff
257
kernel/irq-bcm2835.c
Normal file
257
kernel/irq-bcm2835.c
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@ -0,0 +1,257 @@
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/*
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* Copyright 2010 Broadcom
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* Copyright 2012 Simon Arlott, Chris Boot, Stephen Warren
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Quirk 1: Shortcut interrupts don't set the bank 1/2 register pending bits
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*
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* If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
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* on bank 0 is set to signify that an interrupt in bank 1 has fired, and
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* to look in the bank 1 status register for more information.
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*
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* If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
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* shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
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* status register, but bank 0 bit 8 is _not_ set.
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*
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* Quirk 2: You can't mask the register 1/2 pending interrupts
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*
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* In a proper cascaded interrupt controller, the interrupt lines with
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* cascaded interrupt controllers on them are just normal interrupt lines.
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* You can mask the interrupts and get on with things. With this controller
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* you can't do that.
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*
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* Quirk 3: The shortcut interrupts can't be (un)masked in bank 0
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*
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* Those interrupts that have shortcuts can only be masked/unmasked in
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* their respective banks' enable/disable registers. Doing so in the bank 0
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* enable/disable registers has no effect.
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*
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* The FIQ control register:
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* Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
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* Bit 7: Enable FIQ generation
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* Bits 8+: Unused
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*
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* An interrupt must be disabled before configuring it for FIQ generation
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* otherwise both handlers will fire at the same time!
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*/
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <asm/exception.h>
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/* Put the bank and irq (32 bits) into the hwirq */
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#define MAKE_HWIRQ(b, n) ((b << 5) | (n))
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#define HWIRQ_BANK(i) (i >> 5)
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#define HWIRQ_BIT(i) BIT(i & 0x1f)
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#define NR_IRQS_BANK0 8
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#define BANK0_HWIRQ_MASK 0xff
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/* Shortcuts can't be disabled so any unknown new ones need to be masked */
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#define SHORTCUT1_MASK 0x00007c00
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#define SHORTCUT2_MASK 0x001f8000
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#define SHORTCUT_SHIFT 10
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#define BANK1_HWIRQ BIT(8)
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#define BANK2_HWIRQ BIT(9)
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#define BANK0_VALID_MASK (BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \
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| SHORTCUT1_MASK | SHORTCUT2_MASK)
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#define REG_FIQ_CONTROL 0x0c
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#define NR_BANKS 3
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#define IRQS_PER_BANK 32
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static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
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static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
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static const int reg_disable[] __initconst = { 0x24, 0x1c, 0x20 };
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static const int bank_irqs[] __initconst = { 8, 32, 32 };
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static const int shortcuts[] = {
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7, 9, 10, 18, 19, /* Bank 1 */
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21, 22, 23, 24, 25, 30 /* Bank 2 */
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};
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struct armctrl_ic {
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void __iomem *base;
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void __iomem *pending[NR_BANKS];
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void __iomem *enable[NR_BANKS];
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void __iomem *disable[NR_BANKS];
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struct irq_domain *domain;
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};
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static struct armctrl_ic intc __read_mostly;
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static void __exception_irq_entry bcm2835_handle_irq(
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struct pt_regs *regs);
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static void bcm2836_chained_handle_irq(struct irq_desc *desc);
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static void armctrl_mask_irq(struct irq_data *d)
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{
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writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);
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}
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static void armctrl_unmask_irq(struct irq_data *d)
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{
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writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);
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}
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static struct irq_chip armctrl_chip = {
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.name = "ARMCTRL-level",
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.irq_mask = armctrl_mask_irq,
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.irq_unmask = armctrl_unmask_irq
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};
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static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
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const u32 *intspec, unsigned int intsize,
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unsigned long *out_hwirq, unsigned int *out_type)
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{
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if (WARN_ON(intsize != 2))
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return -EINVAL;
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if (WARN_ON(intspec[0] >= NR_BANKS))
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return -EINVAL;
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||||||
|
|
||||||
|
if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
*out_hwirq = MAKE_HWIRQ(intspec[0], intspec[1]);
|
||||||
|
*out_type = IRQ_TYPE_NONE;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct irq_domain_ops armctrl_ops = {
|
||||||
|
.xlate = armctrl_xlate
|
||||||
|
};
|
||||||
|
|
||||||
|
static int __init armctrl_of_init(struct device_node *node,
|
||||||
|
struct device_node *parent,
|
||||||
|
bool is_2836)
|
||||||
|
{
|
||||||
|
void __iomem *base;
|
||||||
|
int irq, b, i;
|
||||||
|
|
||||||
|
base = of_iomap(node, 0);
|
||||||
|
if (!base)
|
||||||
|
panic("%pOF: unable to map IC registers\n", node);
|
||||||
|
|
||||||
|
intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),
|
||||||
|
&armctrl_ops, NULL);
|
||||||
|
if (!intc.domain)
|
||||||
|
panic("%pOF: unable to create IRQ domain\n", node);
|
||||||
|
|
||||||
|
for (b = 0; b < NR_BANKS; b++) {
|
||||||
|
intc.pending[b] = base + reg_pending[b];
|
||||||
|
intc.enable[b] = base + reg_enable[b];
|
||||||
|
intc.disable[b] = base + reg_disable[b];
|
||||||
|
|
||||||
|
for (i = 0; i < bank_irqs[b]; i++) {
|
||||||
|
irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));
|
||||||
|
BUG_ON(irq <= 0);
|
||||||
|
irq_set_chip_and_handler(irq, &armctrl_chip,
|
||||||
|
handle_level_irq);
|
||||||
|
irq_set_probe(irq);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (is_2836) {
|
||||||
|
int parent_irq = irq_of_parse_and_map(node, 0);
|
||||||
|
|
||||||
|
if (!parent_irq) {
|
||||||
|
panic("%pOF: unable to get parent interrupt.\n",
|
||||||
|
node);
|
||||||
|
}
|
||||||
|
irq_set_chained_handler(parent_irq, bcm2836_chained_handle_irq);
|
||||||
|
} else {
|
||||||
|
set_handle_irq(bcm2835_handle_irq);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int __init bcm2835_armctrl_of_init(struct device_node *node,
|
||||||
|
struct device_node *parent)
|
||||||
|
{
|
||||||
|
return armctrl_of_init(node, parent, false);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int __init bcm2836_armctrl_of_init(struct device_node *node,
|
||||||
|
struct device_node *parent)
|
||||||
|
{
|
||||||
|
return armctrl_of_init(node, parent, true);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Handle each interrupt across the entire interrupt controller. This reads the
|
||||||
|
* status register before handling each interrupt, which is necessary given that
|
||||||
|
* handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
|
||||||
|
*/
|
||||||
|
|
||||||
|
static u32 armctrl_translate_bank(int bank)
|
||||||
|
{
|
||||||
|
u32 stat = readl_relaxed(intc.pending[bank]);
|
||||||
|
|
||||||
|
return MAKE_HWIRQ(bank, ffs(stat) - 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
static u32 armctrl_translate_shortcut(int bank, u32 stat)
|
||||||
|
{
|
||||||
|
return MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]);
|
||||||
|
}
|
||||||
|
|
||||||
|
static u32 get_next_armctrl_hwirq(void)
|
||||||
|
{
|
||||||
|
u32 stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK;
|
||||||
|
|
||||||
|
if (stat == 0)
|
||||||
|
return ~0;
|
||||||
|
else if (stat & BANK0_HWIRQ_MASK)
|
||||||
|
return MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1);
|
||||||
|
else if (stat & SHORTCUT1_MASK)
|
||||||
|
return armctrl_translate_shortcut(1, stat & SHORTCUT1_MASK);
|
||||||
|
else if (stat & SHORTCUT2_MASK)
|
||||||
|
return armctrl_translate_shortcut(2, stat & SHORTCUT2_MASK);
|
||||||
|
else if (stat & BANK1_HWIRQ)
|
||||||
|
return armctrl_translate_bank(1);
|
||||||
|
else if (stat & BANK2_HWIRQ)
|
||||||
|
return armctrl_translate_bank(2);
|
||||||
|
else
|
||||||
|
BUG();
|
||||||
|
}
|
||||||
|
|
||||||
|
static void __exception_irq_entry bcm2835_handle_irq(
|
||||||
|
struct pt_regs *regs)
|
||||||
|
{
|
||||||
|
u32 hwirq;
|
||||||
|
|
||||||
|
while ((hwirq = get_next_armctrl_hwirq()) != ~0)
|
||||||
|
handle_domain_irq(intc.domain, hwirq, regs);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void bcm2836_chained_handle_irq(struct irq_desc *desc)
|
||||||
|
{
|
||||||
|
u32 hwirq;
|
||||||
|
|
||||||
|
while ((hwirq = get_next_armctrl_hwirq()) != ~0)
|
||||||
|
generic_handle_irq(irq_linear_revmap(intc.domain, hwirq));
|
||||||
|
}
|
||||||
|
|
||||||
|
IRQCHIP_DECLARE(bcm2835_armctrl_ic, "brcm,bcm2835-armctrl-ic",
|
||||||
|
bcm2835_armctrl_of_init);
|
||||||
|
IRQCHIP_DECLARE(bcm2836_armctrl_ic, "brcm,bcm2836-armctrl-ic",
|
||||||
|
bcm2836_armctrl_of_init);
|
||||||
316
kernel/irq-bcm2836.c
Normal file
316
kernel/irq-bcm2836.c
Normal file
|
|
@ -0,0 +1,316 @@
|
||||||
|
/*
|
||||||
|
* Root interrupt controller for the BCM2836 (Raspberry Pi 2).
|
||||||
|
*
|
||||||
|
* Copyright 2015 Broadcom
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/cpu.h>
|
||||||
|
#include <linux/of_address.h>
|
||||||
|
#include <linux/of_irq.h>
|
||||||
|
#include <linux/irqchip.h>
|
||||||
|
#include <linux/irqdomain.h>
|
||||||
|
#include <asm/exception.h>
|
||||||
|
|
||||||
|
#define LOCAL_CONTROL 0x000
|
||||||
|
#define LOCAL_PRESCALER 0x008
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The low 2 bits identify the CPU that the GPU IRQ goes to, and the
|
||||||
|
* next 2 bits identify the CPU that the GPU FIQ goes to.
|
||||||
|
*/
|
||||||
|
#define LOCAL_GPU_ROUTING 0x00c
|
||||||
|
/* When setting bits 0-3, enables PMU interrupts on that CPU. */
|
||||||
|
#define LOCAL_PM_ROUTING_SET 0x010
|
||||||
|
/* When setting bits 0-3, disables PMU interrupts on that CPU. */
|
||||||
|
#define LOCAL_PM_ROUTING_CLR 0x014
|
||||||
|
/*
|
||||||
|
* The low 4 bits of this are the CPU's timer IRQ enables, and the
|
||||||
|
* next 4 bits are the CPU's timer FIQ enables (which override the IRQ
|
||||||
|
* bits).
|
||||||
|
*/
|
||||||
|
#define LOCAL_TIMER_INT_CONTROL0 0x040
|
||||||
|
/*
|
||||||
|
* The low 4 bits of this are the CPU's per-mailbox IRQ enables, and
|
||||||
|
* the next 4 bits are the CPU's per-mailbox FIQ enables (which
|
||||||
|
* override the IRQ bits).
|
||||||
|
*/
|
||||||
|
#define LOCAL_MAILBOX_INT_CONTROL0 0x050
|
||||||
|
/*
|
||||||
|
* The CPU's interrupt status register. Bits are defined by the the
|
||||||
|
* LOCAL_IRQ_* bits below.
|
||||||
|
*/
|
||||||
|
#define LOCAL_IRQ_PENDING0 0x060
|
||||||
|
/* Same status bits as above, but for FIQ. */
|
||||||
|
#define LOCAL_FIQ_PENDING0 0x070
|
||||||
|
/*
|
||||||
|
* Mailbox write-to-set bits. There are 16 mailboxes, 4 per CPU, and
|
||||||
|
* these bits are organized by mailbox number and then CPU number. We
|
||||||
|
* use mailbox 0 for IPIs. The mailbox's interrupt is raised while
|
||||||
|
* any bit is set.
|
||||||
|
*/
|
||||||
|
#define LOCAL_MAILBOX0_SET0 0x080
|
||||||
|
#define LOCAL_MAILBOX3_SET0 0x08c
|
||||||
|
/* Mailbox write-to-clear bits. */
|
||||||
|
#define LOCAL_MAILBOX0_CLR0 0x0c0
|
||||||
|
#define LOCAL_MAILBOX3_CLR0 0x0cc
|
||||||
|
|
||||||
|
#define LOCAL_IRQ_CNTPSIRQ 0
|
||||||
|
#define LOCAL_IRQ_CNTPNSIRQ 1
|
||||||
|
#define LOCAL_IRQ_CNTHPIRQ 2
|
||||||
|
#define LOCAL_IRQ_CNTVIRQ 3
|
||||||
|
#define LOCAL_IRQ_MAILBOX0 4
|
||||||
|
#define LOCAL_IRQ_MAILBOX1 5
|
||||||
|
#define LOCAL_IRQ_MAILBOX2 6
|
||||||
|
#define LOCAL_IRQ_MAILBOX3 7
|
||||||
|
#define LOCAL_IRQ_GPU_FAST 8
|
||||||
|
#define LOCAL_IRQ_PMU_FAST 9
|
||||||
|
#define LAST_IRQ LOCAL_IRQ_PMU_FAST
|
||||||
|
|
||||||
|
struct bcm2836_arm_irqchip_intc {
|
||||||
|
struct irq_domain *domain;
|
||||||
|
void __iomem *base;
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct bcm2836_arm_irqchip_intc intc __read_mostly;
|
||||||
|
|
||||||
|
static void bcm2836_arm_irqchip_mask_per_cpu_irq(unsigned int reg_offset,
|
||||||
|
unsigned int bit,
|
||||||
|
int cpu)
|
||||||
|
{
|
||||||
|
void __iomem *reg = intc.base + reg_offset + 4 * cpu;
|
||||||
|
|
||||||
|
writel(readl(reg) & ~BIT(bit), reg);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void bcm2836_arm_irqchip_unmask_per_cpu_irq(unsigned int reg_offset,
|
||||||
|
unsigned int bit,
|
||||||
|
int cpu)
|
||||||
|
{
|
||||||
|
void __iomem *reg = intc.base + reg_offset + 4 * cpu;
|
||||||
|
|
||||||
|
writel(readl(reg) | BIT(bit), reg);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void bcm2836_arm_irqchip_mask_timer_irq(struct irq_data *d)
|
||||||
|
{
|
||||||
|
bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
|
||||||
|
d->hwirq - LOCAL_IRQ_CNTPSIRQ,
|
||||||
|
smp_processor_id());
|
||||||
|
}
|
||||||
|
|
||||||
|
static void bcm2836_arm_irqchip_unmask_timer_irq(struct irq_data *d)
|
||||||
|
{
|
||||||
|
bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
|
||||||
|
d->hwirq - LOCAL_IRQ_CNTPSIRQ,
|
||||||
|
smp_processor_id());
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct irq_chip bcm2836_arm_irqchip_timer = {
|
||||||
|
.name = "bcm2836-timer",
|
||||||
|
.irq_mask = bcm2836_arm_irqchip_mask_timer_irq,
|
||||||
|
.irq_unmask = bcm2836_arm_irqchip_unmask_timer_irq,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void bcm2836_arm_irqchip_mask_pmu_irq(struct irq_data *d)
|
||||||
|
{
|
||||||
|
writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void bcm2836_arm_irqchip_unmask_pmu_irq(struct irq_data *d)
|
||||||
|
{
|
||||||
|
writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET);
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct irq_chip bcm2836_arm_irqchip_pmu = {
|
||||||
|
.name = "bcm2836-pmu",
|
||||||
|
.irq_mask = bcm2836_arm_irqchip_mask_pmu_irq,
|
||||||
|
.irq_unmask = bcm2836_arm_irqchip_unmask_pmu_irq,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void bcm2836_arm_irqchip_mask_gpu_irq(struct irq_data *d)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
static void bcm2836_arm_irqchip_unmask_gpu_irq(struct irq_data *d)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct irq_chip bcm2836_arm_irqchip_gpu = {
|
||||||
|
.name = "bcm2836-gpu",
|
||||||
|
.irq_mask = bcm2836_arm_irqchip_mask_gpu_irq,
|
||||||
|
.irq_unmask = bcm2836_arm_irqchip_unmask_gpu_irq,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void bcm2836_arm_irqchip_register_irq(int hwirq, struct irq_chip *chip)
|
||||||
|
{
|
||||||
|
int irq = irq_create_mapping(intc.domain, hwirq);
|
||||||
|
|
||||||
|
irq_set_percpu_devid(irq);
|
||||||
|
irq_set_chip_and_handler(irq, chip, handle_percpu_devid_irq);
|
||||||
|
irq_set_status_flags(irq, IRQ_NOAUTOEN);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
__exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs)
|
||||||
|
{
|
||||||
|
int cpu = smp_processor_id();
|
||||||
|
u32 stat;
|
||||||
|
|
||||||
|
stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu);
|
||||||
|
if (stat & BIT(LOCAL_IRQ_MAILBOX0)) {
|
||||||
|
#ifdef CONFIG_SMP
|
||||||
|
void __iomem *mailbox0 = (intc.base +
|
||||||
|
LOCAL_MAILBOX0_CLR0 + 16 * cpu);
|
||||||
|
u32 mbox_val = readl(mailbox0);
|
||||||
|
u32 ipi = ffs(mbox_val) - 1;
|
||||||
|
|
||||||
|
writel(1 << ipi, mailbox0);
|
||||||
|
handle_IPI(ipi, regs);
|
||||||
|
#endif
|
||||||
|
} else if (stat) {
|
||||||
|
u32 hwirq = ffs(stat) - 1;
|
||||||
|
|
||||||
|
handle_domain_irq(intc.domain, hwirq, regs);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_SMP
|
||||||
|
static void bcm2836_arm_irqchip_send_ipi(const struct cpumask *mask,
|
||||||
|
unsigned int ipi)
|
||||||
|
{
|
||||||
|
int cpu;
|
||||||
|
void __iomem *mailbox0_base = intc.base + LOCAL_MAILBOX0_SET0;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Ensure that stores to normal memory are visible to the
|
||||||
|
* other CPUs before issuing the IPI.
|
||||||
|
*/
|
||||||
|
smp_wmb();
|
||||||
|
|
||||||
|
for_each_cpu(cpu, mask) {
|
||||||
|
writel(1 << ipi, mailbox0_base + 16 * cpu);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static int bcm2836_cpu_starting(unsigned int cpu)
|
||||||
|
{
|
||||||
|
bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
|
||||||
|
cpu);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int bcm2836_cpu_dying(unsigned int cpu)
|
||||||
|
{
|
||||||
|
bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
|
||||||
|
cpu);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_ARM
|
||||||
|
static int __init bcm2836_smp_boot_secondary(unsigned int cpu,
|
||||||
|
struct task_struct *idle)
|
||||||
|
{
|
||||||
|
unsigned long secondary_startup_phys =
|
||||||
|
(unsigned long)virt_to_phys((void *)secondary_startup);
|
||||||
|
|
||||||
|
writel(secondary_startup_phys,
|
||||||
|
intc.base + LOCAL_MAILBOX3_SET0 + 16 * cpu);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct smp_operations bcm2836_smp_ops __initconst = {
|
||||||
|
.smp_boot_secondary = bcm2836_smp_boot_secondary,
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
|
||||||
|
.xlate = irq_domain_xlate_onecell
|
||||||
|
};
|
||||||
|
|
||||||
|
static void
|
||||||
|
bcm2836_arm_irqchip_smp_init(void)
|
||||||
|
{
|
||||||
|
#ifdef CONFIG_SMP
|
||||||
|
/* Unmask IPIs to the boot CPU. */
|
||||||
|
cpuhp_setup_state(CPUHP_AP_IRQ_BCM2836_STARTING,
|
||||||
|
"irqchip/bcm2836:starting", bcm2836_cpu_starting,
|
||||||
|
bcm2836_cpu_dying);
|
||||||
|
|
||||||
|
set_smp_cross_call(bcm2836_arm_irqchip_send_ipi);
|
||||||
|
|
||||||
|
#ifdef CONFIG_ARM
|
||||||
|
smp_set_ops(&bcm2836_smp_ops);
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The LOCAL_IRQ_CNT* timer firings are based off of the external
|
||||||
|
* oscillator with some scaling. The firmware sets up CNTFRQ to
|
||||||
|
* report 19.2Mhz, but doesn't set up the scaling registers.
|
||||||
|
*/
|
||||||
|
static void bcm2835_init_local_timer_frequency(void)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* Set the timer to source from the 19.2Mhz crystal clock (bit
|
||||||
|
* 8 unset), and only increment by 1 instead of 2 (bit 9
|
||||||
|
* unset).
|
||||||
|
*/
|
||||||
|
writel(0, intc.base + LOCAL_CONTROL);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Set the timer prescaler to 1:1 (timer freq = input freq *
|
||||||
|
* 2**31 / prescaler)
|
||||||
|
*/
|
||||||
|
writel(0x80000000, intc.base + LOCAL_PRESCALER);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int __init bcm2836_arm_irqchip_l1_intc_of_init(struct device_node *node,
|
||||||
|
struct device_node *parent)
|
||||||
|
{
|
||||||
|
intc.base = of_iomap(node, 0);
|
||||||
|
if (!intc.base) {
|
||||||
|
panic("%pOF: unable to map local interrupt registers\n", node);
|
||||||
|
}
|
||||||
|
|
||||||
|
bcm2835_init_local_timer_frequency();
|
||||||
|
|
||||||
|
intc.domain = irq_domain_add_linear(node, LAST_IRQ + 1,
|
||||||
|
&bcm2836_arm_irqchip_intc_ops,
|
||||||
|
NULL);
|
||||||
|
if (!intc.domain)
|
||||||
|
panic("%pOF: unable to create IRQ domain\n", node);
|
||||||
|
|
||||||
|
bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTPSIRQ,
|
||||||
|
&bcm2836_arm_irqchip_timer);
|
||||||
|
bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTPNSIRQ,
|
||||||
|
&bcm2836_arm_irqchip_timer);
|
||||||
|
bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTHPIRQ,
|
||||||
|
&bcm2836_arm_irqchip_timer);
|
||||||
|
bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTVIRQ,
|
||||||
|
&bcm2836_arm_irqchip_timer);
|
||||||
|
bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_GPU_FAST,
|
||||||
|
&bcm2836_arm_irqchip_gpu);
|
||||||
|
bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_PMU_FAST,
|
||||||
|
&bcm2836_arm_irqchip_pmu);
|
||||||
|
|
||||||
|
bcm2836_arm_irqchip_smp_init();
|
||||||
|
|
||||||
|
set_handle_irq(bcm2836_arm_irqchip_handle_irq);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
IRQCHIP_DECLARE(bcm2836_arm_irqchip_l1_intc, "brcm,bcm2836-l1-intc",
|
||||||
|
bcm2836_arm_irqchip_l1_intc_of_init);
|
||||||
1
kernel/tuto.txt
Normal file
1
kernel/tuto.txt
Normal file
|
|
@ -0,0 +1 @@
|
||||||
|
https://lemariva.com/blog/2018/07/raspberry-pi-xenomai-patching-tutorial-for-kernel-4-14-y
|
||||||
79
software/robot/robot Release.launch
Normal file
79
software/robot/robot Release.launch
Normal file
|
|
@ -0,0 +1,79 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||||
|
<launchConfiguration type="com.st.stm32cube.ide.mcu.debug.launch.launchConfigurationType">
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.access_port_id" value="0"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.enable_live_expr" value="true"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.enable_swv" value="false"/>
|
||||||
|
<intAttribute key="com.st.stm32cube.ide.mcu.debug.launch.formatVersion" value="2"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.ip_address_local" value="localhost"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.limit_swo_clock.enabled" value="false"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.limit_swo_clock.value" value=""/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.loadList" value="{"fItems":[{"fIsFromMainTab":true,"fPath":"Debug/robot.elf","fProjectName":"robot","fPerformBuild":true,"fDownload":true,"fLoadSymbols":true}]}"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.override_start_address_mode" value="default"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.remoteCommand" value="target remote"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startServer" value="true"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startuptab.exception.divby0" value="true"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startuptab.exception.unaligned" value="false"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startuptab.haltonexception" value="true"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swd_mode" value="true"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_port" value="61235"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_trace_hclk" value="16000000"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.useRemoteTarget" value="true"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.vector_table" value=""/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.verify_flash_download" value="true"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.cti_allow_halt" value="false"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.cti_signal_halt" value="false"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_external_loader" value="false"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_logging" value="false"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_max_halt_delay" value="false"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_shared_stlink" value="false"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.external_loader" value=""/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.external_loader_init" value="false"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.frequency" value="0"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.halt_all_on_reset" value="false"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.log_file" value="/home/dimercur/Travail/git/dumber/software/robot/Release/st-link_gdbserver_log.txt"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.low_power_debug" value="enable"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.max_halt_delay" value="2"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.reset_strategy" value="connect_under_reset"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_check_serial_number" value="false"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_txt_serial_number" value=""/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.watchdog_config" value="none"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlinkenable_rtos" value="false"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlinkrestart_configurations" value="{"fItems":[{"fDisplayName":"Reset","fIsSuppressible":false,"fResetAttribute":"Software system reset","fResetStrategies":[{"fDisplayName":"Software system reset","fLaunchAttribute":"system_reset","fGdbCommands":["monitor reset\n"],"fCmdOptions":["-g"]},{"fDisplayName":"Hardware reset","fLaunchAttribute":"hardware_reset","fGdbCommands":["monitor reset hardware\n"],"fCmdOptions":["-g"]},{"fDisplayName":"Core reset","fLaunchAttribute":"core_reset","fGdbCommands":["monitor reset core\n"],"fCmdOptions":["-g"]},{"fDisplayName":"None","fLaunchAttribute":"no_reset","fGdbCommands":[],"fCmdOptions":["-g"]}],"fGdbCommandGroup":{"name":"Additional commands","commands":[]}}]}"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.enableRtosProxy" value="false"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyCustomProperties" value=""/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyDriver" value="threadx"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyDriverAuto" value="false"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyDriverPort" value="cortex_m0"/>
|
||||||
|
<intAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyPort" value="60000"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDeviceId" value="com.st.stm32cube.ide.mcu.debug.stlink"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
|
||||||
|
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="61234"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="true"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
|
||||||
|
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/robot.elf"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="robot"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.412926795"/>
|
||||||
|
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||||
|
<listEntry value="/robot"/>
|
||||||
|
</listAttribute>
|
||||||
|
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||||
|
<listEntry value="4"/>
|
||||||
|
</listAttribute>
|
||||||
|
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
|
||||||
|
</launchConfiguration>
|
||||||
Loading…
Add table
Reference in a new issue