Added basic behavior, Added Vivado Project file
This commit is contained in:
parent
f7cedc281e
commit
d823f37938
3 changed files with 262 additions and 10 deletions
234
memory_file.xpr
Normal file
234
memory_file.xpr
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@ -0,0 +1,234 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2023.1 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
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<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
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<Project Product="Vivado" Version="7" Minor="63" Path="D:/Data/Alzyohan/GEI/VHDL/memory_file_vivado/memory_file.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="0ce82e7a6509434fa74c68762fdc2cf1"/>
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<Option Name="Part" Val="xc7a35tcpg236-1"/>
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<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
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<Option Name="CompiledLibDirXSim" Val=""/>
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<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
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<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
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<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
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<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
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<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
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<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
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<Option Name="SimulatorInstallDirModelSim" Val=""/>
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<Option Name="SimulatorInstallDirQuesta" Val=""/>
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<Option Name="SimulatorInstallDirXcelium" Val=""/>
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<Option Name="SimulatorInstallDirVCS" Val=""/>
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<Option Name="SimulatorInstallDirRiviera" Val=""/>
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<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
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<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
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<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
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<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
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<Option Name="SimulatorGccInstallDirVCS" Val=""/>
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<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
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<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
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<Option Name="SimulatorVersionXsim" Val="2023.1"/>
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<Option Name="SimulatorVersionModelSim" Val="2022.3"/>
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<Option Name="SimulatorVersionQuesta" Val="2022.3"/>
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<Option Name="SimulatorVersionXcelium" Val="22.09.001"/>
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<Option Name="SimulatorVersionVCS" Val="T-2022.06-SP1"/>
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<Option Name="SimulatorVersionRiviera" Val="2022.04"/>
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<Option Name="SimulatorVersionActiveHdl" Val="13.1"/>
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<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
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<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
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<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
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<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
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<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
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<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
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<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
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<Option Name="TargetLanguage" Val="VHDL"/>
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<Option Name="SimulatorLanguage" Val="VHDL"/>
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<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
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<Option Name="BoardPartRepoPaths" Val="C:/Users/alzyo/AppData/Roaming/Xilinx/Vivado/2023.1/xhub/board_store/xilinx_board_store"/>
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<Option Name="ActiveSimSet" Val="sim_1"/>
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<Option Name="DefaultLib" Val="xil_defaultlib"/>
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<Option Name="ProjectType" Val="Default"/>
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<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
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<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
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<Option Name="IPCachePermission" Val="read"/>
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<Option Name="IPCachePermission" Val="write"/>
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<Option Name="EnableCoreContainer" Val="FALSE"/>
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<Option Name="EnableResourceEstimation" Val="FALSE"/>
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<Option Name="SimCompileState" Val="TRUE"/>
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<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
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<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
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<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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<Option Name="EnableBDX" Val="FALSE"/>
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<Option Name="DSABoardId" Val="basys3"/>
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<Option Name="WTXSimLaunchSim" Val="2"/>
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<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTQuestaLaunchSim" Val="0"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
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<Option Name="WTVcsLaunchSim" Val="0"/>
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<Option Name="WTRivieraLaunchSim" Val="0"/>
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<Option Name="WTActivehdlLaunchSim" Val="0"/>
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<Option Name="WTXSimExportSim" Val="0"/>
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<Option Name="WTModelSimExportSim" Val="0"/>
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<Option Name="WTQuestaExportSim" Val="0"/>
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<Option Name="WTIesExportSim" Val="0"/>
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<Option Name="WTVcsExportSim" Val="0"/>
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<Option Name="WTRivieraExportSim" Val="0"/>
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<Option Name="WTActivehdlExportSim" Val="0"/>
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<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
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<Option Name="XSimRadix" Val="hex"/>
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<Option Name="XSimTimeUnit" Val="ns"/>
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<Option Name="XSimArrayDisplayLimit" Val="1024"/>
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<Option Name="XSimTraceLimit" Val="65536"/>
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<Option Name="SimTypes" Val="rtl"/>
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<Option Name="SimTypes" Val="bfm"/>
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<Option Name="SimTypes" Val="tlm"/>
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<Option Name="SimTypes" Val="tlm_dpi"/>
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<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
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<Option Name="DcpsUptoDate" Val="TRUE"/>
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<Option Name="ClassicSocBoot" Val="FALSE"/>
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<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
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</Configuration>
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<FileSets Version="1" Minor="31">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
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<Filter Type="Srcs"/>
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<File Path="$PPRDIR/../memory_file/src/instruction.vhd">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="instruction"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</FileSet>
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<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
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<Filter Type="Constrs"/>
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<Config>
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<Option Name="ConstrsType" Val="XDC"/>
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</Config>
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</FileSet>
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<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
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<File Path="$PPRDIR/../memory_file/src/sim_instruction.vhd">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="test_instr"/>
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<Option Name="TopLib" Val="xil_defaultlib"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="TransportPathDelay" Val="0"/>
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<Option Name="TransportIntDelay" Val="0"/>
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<Option Name="SelectedSimModel" Val="rtl"/>
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<Option Name="PamDesignTestbench" Val=""/>
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<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
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<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
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<Option Name="PamPseudoTop" Val="pseudo_tb"/>
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<Option Name="SrcSet" Val="sources_1"/>
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</Config>
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</FileSet>
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<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
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<Filter Type="Utils"/>
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<File Path="$PSRCDIR/utils_1/imports/synth_1/instruction.dcp">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedInSteps" Val="synth_1"/>
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<Attr Name="AutoDcp" Val="1"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</FileSet>
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</FileSets>
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<Simulators>
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<Simulator Name="XSim">
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<Option Name="Description" Val="Vivado Simulator"/>
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<Option Name="CompiledLib" Val="0"/>
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</Simulator>
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<Simulator Name="ModelSim">
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<Option Name="Description" Val="ModelSim Simulator"/>
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</Simulator>
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<Simulator Name="Questa">
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<Option Name="Description" Val="Questa Advanced Simulator"/>
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</Simulator>
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<Simulator Name="Riviera">
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<Option Name="Description" Val="Riviera-PRO Simulator"/>
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</Simulator>
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<Simulator Name="ActiveHDL">
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<Option Name="Description" Val="Active-HDL Simulator"/>
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</Simulator>
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</Simulators>
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<Runs Version="1" Minor="20">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/instruction.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
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<Desc>Vivado Synthesis Defaults</Desc>
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</StratHandle>
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<Step Id="synth_design"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
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<Desc>Default settings for Implementation.</Desc>
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</StratHandle>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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<Step Id="place_design"/>
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<Step Id="post_place_power_opt_design"/>
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<Step Id="phys_opt_design"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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</Strategy>
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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</Runs>
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<Board>
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<Jumpers/>
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</Board>
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<DashboardSummary Version="1" Minor="0">
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<Dashboards>
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<Dashboard Name="default_dashboard">
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<Gadgets>
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<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
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</Gadget>
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<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
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</Gadget>
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<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
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</Gadget>
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<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
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</Gadget>
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<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
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<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
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<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
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<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
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</Gadget>
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<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
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</Gadget>
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</Gadgets>
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</Dashboard>
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<CurrentDashboard>default_dashboard</CurrentDashboard>
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</Dashboards>
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</DashboardSummary>
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</Project>
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@ -4,21 +4,37 @@ use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity instruction is
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entity instruction is
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port(
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port(
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instruction: in STD_LOGIC_VECTOR(7 downto 0);
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instruction: in STD_LOGIC_VECTOR(7 downto 0);
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code: out STD_LOGIC_VECTOR(31 downto 0);
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code: out STD_LOGIC_VECTOR(31 downto 0);
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clk: in STD_LOGIC
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clk: in STD_LOGIC
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);
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);
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-- Array of STD_LOGIC_VECTOR
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type code_array is array(0 to 256) of
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STD_LOGIC_VECTOR(31 downto 0);
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-- Initialize the code memory
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function init return code_array is
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variable init_result: code_array;
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begin
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--do something (e.g. read data from a file, perform some initialization calculation, ...)
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-- Exemple :
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for i in code_array'range loop
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init_result(i) := (others => '0');
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end loop;
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return init_result;
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end function init;
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end instruction;
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end instruction;
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architecture behavior_instr of instruction is
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architecture behavior_instr of instruction is
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-- Array of STD_LOGIC_VECTOR
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type code_array is array(0 to 15) of
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STD_LOGIC_VECTOR(7 downto 0);
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-- Memory variable
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-- Memory variable
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signal code_memory: code_array;
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signal code_memory: code_array := init;
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begin
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begin
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process(instruction, clk) is
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process(instruction, clk) is
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begin
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begin
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if clk'event AND clk = '1' then
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code <= code_memory(CONV_INTEGER(UNSIGNED(instruction)));
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end if;
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end process;
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end process;
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end behavior_instr;
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end behavior_instr;
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@ -11,7 +11,7 @@ architecture bench of test_instr is
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component instruction is
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component instruction is
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port(
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port(
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instruction: in STD_LOGIC_VECTOR(7 downto 0);
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instruction: in STD_LOGIC_VECTOR(7 downto 0);
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code: in STD_LOGIC_VECTOR(31 downto 0);
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code: out STD_LOGIC_VECTOR(31 downto 0);
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clk: in STD_LOGIC
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clk: in STD_LOGIC
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);
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);
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end component;
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end component;
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@ -24,6 +24,8 @@ architecture bench of test_instr is
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begin
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begin
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testeur: instruction PORT MAP(inAddress, outCode, inClock);
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testeur: instruction PORT MAP(inAddress, outCode, inClock);
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inClock <= not inClock after 1ns;
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inAddress <= X"00", X"0a" after 10ns;
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end bench;
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end bench;
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Add table
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