PC -1

juste
PC -1.

cpu_project/cpu_project.xpr

@@ -60,7 +60,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="199"/>
+    <Option Name="WTXSimLaunchSim" Val="258"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>

src/cpu.vhd

@@ -5,7 +5,8 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 entity cpu is
     Port (
-        clk : in STD_LOGIC
+        clk : in STD_LOGIC;
+        reset : in STD_LOGIC
   );
 end cpu;
 
@@ -120,14 +121,17 @@ ARCHITECTURE cpu_arch OF cpu IS
     signal W_enable: STD_LOGIC;
 
     --- internal component of cpu
-    signal inst : STD_LOGIC_VECTOR(31 downto 0);
-    signal PC : STD_LOGIC_VECTOR(7 downto 0) := X"00";
+    signal inst_in, inst_out : STD_LOGIC_VECTOR(31 downto 0);
+    signal PC, ALEA_COUNT : STD_LOGIC_VECTOR(7 downto 0) := X"00";
     
 begin
-    instruction_memory_inst : instruction PORT MAP(PC, inst , clk);
+    with ALEA_COUNT select
+        inst_out <= inst_in when X"00",
+                    X"00000000" when others;
+    instruction_memory_inst : instruction PORT MAP(PC, inst_in , clk);
     
     -- step1 pipeline
-    step1_lidi  :           pipeline_step PORT MAP(inst(23 downto 16), inst(15 downto 8), inst(7 downto 0), inst(27 downto 24), clk, di_A, di_B_out, di_C_out, di_OP);
+    step1_lidi  :           pipeline_step PORT MAP(inst_out(23 downto 16), inst_out(15 downto 8), inst_out(7 downto 0), inst_out(27 downto 24), clk, di_A, di_B_out, di_C_out, di_OP);
     memory_register_inst :  reg PORT MAP(di_B_out(3 downto 0), di_C_out(3 downto 0), re_A(3 downto 0), W_enable, re_B, '1', clk, qA, di_C_in);
     mux_bdr_inst :          mux_bdr PORT MAP(di_OP,di_B_out,qA,di_B_in);
 
@@ -165,8 +169,19 @@ begin
 
     process(clk)
         begin
-            if clk'event and clk='1' then
+            if clk'event and clk='1' and reset='0' then
+                if (di_OP = X"06" and inst_out(27 downto 24) = X"05" and di_A = inst_out(15 downto 8)) or (ALEA_COUNT > 0 and ALEA_COUNT < 5) then
+                    if ALEA_COUNT = 0 then
+                        PC <= PC-'1';
+                    end if;
+                    ALEA_COUNT <= ALEA_COUNT+'1';
+                else 
                     PC <= PC+'1';
+                    ALEA_COUNT <= X"00";
+                end if;
+            elsif reset ='1' then
+                PC <= X"00";
+                ALEA_COUNT <= X"00";
             end if;
     end process;
 

src/cpu_tb.vhd

@@ -8,11 +8,12 @@ end test_cpu;
 architecture bench of test_cpu is
     component cpu
         Port (
-            clk : in STD_LOGIC
+            clk : in STD_LOGIC;
+            reset : in STD_LOGIC
         );
     end component;
 
-    signal inClock : STD_LOGIC := '0';  
+    signal inClock, inReset : STD_LOGIC := '0';  
     
     -- Signals for monitoring internal states
     signal int_PC, int_re_A, int_re_B, int_re_C : STD_LOGIC_VECTOR(7 downto 0);
@@ -20,11 +21,13 @@ architecture bench of test_cpu is
     
 begin
     uut: cpu PORT MAP( 
-        inClock
+        inClock,
+        inReset
     );
 
     -- Clock generation
     inClock <= not inClock after 10 ns; -- Adjust clock period as necessary
+    inReset <= '1', '0' after 20ns;
 
 end bench;
 

src/data_memory.vhd

@@ -16,7 +16,7 @@ architecture Behavioral of data_memory is
     type MemoryArray is array (0 to 255) of STD_LOGIC_VECTOR(7 downto 0);
     signal Memory : MemoryArray := (others => X"00");
 begin
-    process(CLK, RST)
+    process(CLK)
     begin
         if RST = '1' then
             Memory <= (others => X"00");  -- Reset the memory to 0x00

src/instruction_memory.vhd

@@ -26,14 +26,12 @@ entity instruction is
         init_result(0) := X"06010A00"; -- AFC 0x0a to R01
         init_result(1) := X"06020B00"; -- AFC 0x0b to R02
         init_result(2) := X"06030200"; -- AFC 0x0c to R03
-        init_result(3) := X"06040D00"; -- AFC 0x0d to R04
-        init_result(4) := X"06050E00"; -- AFC 0x0e to R05
-        init_result(5) := X"05000100"; -- COPY R01 to R00
-        init_result(6) := X"01060102"; -- ADD R06=R01+R02
-        init_result(7) := X"02070103"; -- MUL R07=R01*R03
-        init_result(8) := X"03080201"; -- SOUS R08=R01-R02
-        init_result(9) := X"08010200"; -- STORE [@01] <- R02
-        init_result(20) := X"07090100"; -- LOAD R09 -< [@01]
+        init_result(3) := X"05000300"; -- COPY R03 to R00
+        init_result(4) := X"01060102"; -- ADD R06=R01+R02
+        init_result(5) := X"02070103"; -- MUL R07=R01*R03
+        init_result(6) := X"03080201"; -- SOUS R08=R01-R02
+        init_result(7) := X"08010200"; -- STORE [@01] <- R02
+        init_result(15) := X"07090100"; -- LOAD R09 -< [@01]
         return init_result;
     end function init;
 end instruction;
@@ -42,7 +40,7 @@ architecture behavior_instr of instruction is
     -- Memory variable
     signal code_memory: code_array := init;
 begin
-    process(instruction, clk) is
+    process(clk) is
     begin
         if clk'event AND clk = '1' then
             code <= code_memory(CONV_INTEGER(UNSIGNED(instruction)));

src/pipeline_step.vhd

@@ -19,7 +19,7 @@ end pipeline_step;
 
 architecture behavior_pipeline_step of pipeline_step is
 begin
-    process(clk, A_in, B_in, C_in, OP_in)
+    process(clk)
         begin
             if clk'event and clk='1' then
                 A_out <= A_in;

src/register.vhd

@@ -34,7 +34,7 @@ begin
         else W_Data;
     
     -- Write data synchronously
-    process(address_W, W_Enable, W_Data, reset, clk) is
+    process(clk) is
     begin
         -- Reset the memory if shutdown
         if reset = '0' then