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22 lines
908 B
Markdown
22 lines
908 B
Markdown
# Risc V VHDL 5 Stages Pipeline
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**Key Improvements in Develop Branch:**
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- Better understanding of VHDL allowed for a more efficient design.
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- The removal of redundant pipeline stage components streamlined the microprocessor, reducing bottlenecks and increasing operational frequency.
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1. **Main Branch:**
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- Frequency: 68.19 MHz
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- Design philosophy:
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- Relied on components for pipeline stages.
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- These components added complexity and increased the number of logical gates required, leading to slower processing.
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2. **Develop Branch:**
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- Frequency: 168.55 MHz
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- Design philosophy:
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- Simplified architecture by eliminating unnecessary pipeline stage components.
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- Optimized signal paths and reduced the number of logical gate transitions, leading to higher efficiency and speed.
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