52 lines
No EOL
862 B
VHDL
52 lines
No EOL
862 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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Entity digit is
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Port ( clk, raz,E : in std_logic;
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QA,QB,QC : out std_logic_vector(3 downto 0));
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End digit;
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Architecture Behaviour of digit is
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signal A : std_logic_vector(3 downto 0);
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signal B : std_logic_vector(3 downto 0);
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signal C : std_logic_vector(3 downto 0);
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Begin
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process(clk, raz)
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Begin
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If (raz = '1') then
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A <="0000";
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B <="0000";
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C <="0000";
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Elsif (clk'event and clk='1') then
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If(E='1') then
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Elsif (A < 9) then
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A <= A+1;
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Elsif (A >= 9 and B < 9) then
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A <="0000";
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B <= B+1;
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Elsif (B >= 9 and C < 4) then
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B <="0000";
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C <= C+1;
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End if;
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End if;
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End process;
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process(E)
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begin
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if(E'event and E ='0' ) then
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QA <= A;
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QB <= B;
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QC <= C;
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end if;
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end process;
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End Behaviour; |