Process based risc boiler plate

cpu_project/cpu_project.xpr

@@ -60,7 +60,7 @@
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
     <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
-    <Option Name="WTXSimLaunchSim" Val="175"/>
+    <Option Name="WTXSimLaunchSim" Val="219"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -91,6 +91,12 @@
   <FileSets Version="1" Minor="32">
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
       <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/../src/register.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PPRDIR/../src/cpu.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -104,13 +110,6 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PPRDIR/../src/data_memory.vhd">
-        <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
       <File Path="$PPRDIR/../src/instruction_memory.vhd">
         <FileInfo>
           <Attr Name="AutoDisabled" Val="1"/>
@@ -118,7 +117,7 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PPRDIR/../src/register.vhd">
+      <File Path="$PPRDIR/../src/data_memory.vhd">
         <FileInfo>
           <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>

src/cpu.vhd

@@ -57,8 +57,73 @@ ARCHITECTURE cpu_arch OF cpu IS
 	);
     END COMPONENT;
 
+    -- Signaux internes
+    signal PC : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; -- Program Counter
+    signal IR : STD_LOGIC_VECTOR (31 downto 0); -- Instruction Register
+    signal A : STD_LOGIC_VECTOR (7 downto 0);
+    signal B : STD_LOGIC_VECTOR (7 downto 0);
+    signal C : STD_LOGIC_VECTOR (7 downto 0);
 
-begin
     
+BEGIN
+   -- Instantiation des composants
+   RegisterFile_Instance: reg PORT MAP (
+    address_A => "0000",
+    address_B => "0000",
+    address_W => "0000",
+    W_Enable  => '0',
+    W_Data    => "00000000",
+    reset     => '0',
+    clk       => clk,
+    A_Data    => open,
+    B_Data    => open
+    );
+
+
+
+    -- Pipeline
+
+    -- Lecture Instruction (LI)
+    LI: process(clk)
+    begin
+        if rising_edge(clk) then
+            -- Charger les instruction
+        end if;
+    end process;
+
+    DI: process(clk)
+    begin
+        if rising_edge(clk) then
+            -- Decoder IR et init A B C
+        end if;
+    end process;
+
+    EX: process(clk)
+    begin
+        if rising_edge(clk) then
+            -- Executer instruction si nécéssaire
+        end if;
+    end process;
+
+    MEM: process(clk)
+    begin
+        if rising_edge(clk) then
+            -- Ecrire ou lire memoire des données
+        end if;
+    end process;
+
+    RE: process(clk)
+    begin
+        if rising_edge(clk) then
+            -- Ecrire dans les registres
+        end if;
+    end process;
+
+    PC_UPDATE: process(clk)
+    begin
+        if rising_edge(clk) then
+            PC <= PC + 1;
+        end if;
+    end process;
 
 END cpu_arch;